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Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r116-csrt-152666475000124
Last Updated
June 26, 2018

About the Execution of ITS-Tools for LamportFastMutEx-PT-4

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15752.340 5726.00 16293.00 107.90 FTTTTTFFTFFFFFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.................
/home/mcc/execution
total 368K
-rw-r--r-- 1 mcc users 6.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 30K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 29K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 8.9K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 40K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 110K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-PT-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475000124
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-4-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527165316280

FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-PT-4-ReachabilityCardinality-00 with value :((((((y_0+y_1)+y_2)+y_3)+y_4)>=1)&&(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)<=((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4))||(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)<=((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)))||(((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-01 with value :((((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)>=2)&&(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)>=1))||((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)>=1)&&(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=1)))&&((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=3)||((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)<=((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-02 with value :((!((((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4))||(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)>=3)))&&(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=1)||(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=3))&&((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)>=1)&&(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-03 with value :(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)>=3)
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-04 with value :(((!(((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)))||(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=2))&&((!(((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)>=3))&&(!(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)>=1))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-06 with value :((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)>=2)&&(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=3))
Read [invariant] property : LamportFastMutEx-PT-4-ReachabilityCardinality-07 with value :(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)<=((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4))
Read [invariant] property : LamportFastMutEx-PT-4-ReachabilityCardinality-08 with value :((P_wait_2_0<=P_awaity_1)||(P_ify0_4_1<=P_done_3_3))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-09 with value :((((P_awaity_3>=2)&&(P_ifxi_10_3<=P_CS_21_0))&&(!(P_CS_21_4<=P_b_3_false)))&&((P_setbi_24_1<=P_setbi_5_3)&&((P_b_2_true<=P_start_1_0)||(P_done_0_3<=P_done_2_3))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-10 with value :(!(P_sety_9_0<=P_setbi_24_3))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-11 with value :((P_setx_3_3<=P_done_4_3)&&(P_ifxi_10_3>=3))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-12 with value :((P_done_1_4<=P_done_0_0)&&(((y_2<=P_done_0_0)&&(P_b_4_true<=P_start_1_2))&&((P_fordo_12_0>=1)&&(P_ifyi_15_3>=1))))
Read [reachable] property : LamportFastMutEx-PT-4-ReachabilityCardinality-13 with value :(((P_ifxi_10_3>=1)&&((P_ify0_4_2>=3)&&(P_done_2_2<=P_wait_3_2)))&&(!((P_done_1_1>=3)&&(P_wait_4_4<=P_ify0_4_4))))
Read [invariant] property : LamportFastMutEx-PT-4-ReachabilityCardinality-14 with value :((!((P_wait_4_4>=3)&&(P_done_0_2<=P_wait_2_4)))||(((P_done_2_4<=P_wait_4_0)&&(P_sety_9_4<=P_ifxi_10_4))||(!(y_2<=P_wait_0_4))))
Read [invariant] property : LamportFastMutEx-PT-4-ReachabilityCardinality-15 with value :((((P_wait_4_4<=P_sety_9_2)||(y_3<=P_setbi_11_2))&&((P_CS_21_2>=2)||(P_done_0_4<=P_fordo_12_0)))||(y_0<=P_setx_3_2))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 185
// Phase 1: matrix 185 rows 135 cols
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 = 1
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_3_0 + P_done_3_0 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 185
// Phase 1: matrix 185 rows 135 cols
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 = 1
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_3_0 + P_done_3_0 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_PT\_4\_flat\_flat,1.91478e+06,2.60766,70808,2,15178,5,166402,6,0,753,279706,0
Total reachable state count : 1914784

Verifying 15 reachability properties.
Invariant property LamportFastMutEx-PT-4-ReachabilityCardinality-00 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-00,96,2.65448,71088,2,651,6,166402,7,0,971,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-01 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-01,1,2.68222,71192,2,136,7,166402,8,0,1016,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-02 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-02,14142,2.84551,71192,2,7751,8,166402,9,0,1721,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-03 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-03,1,2.84974,71192,2,136,9,166402,10,0,1732,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-04,1,2.85175,71192,2,136,10,166402,11,0,1748,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-06 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-06,0,2.87896,71192,1,0,10,166402,12,0,1773,279706,0
Invariant property LamportFastMutEx-PT-4-ReachabilityCardinality-07 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-07,1,2.87986,71192,2,136,11,166402,13,0,1783,279706,0
Invariant property LamportFastMutEx-PT-4-ReachabilityCardinality-08 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-08,0,2.90457,71192,1,0,11,166402,14,0,1795,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-09 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-09,0,2.90904,71192,1,0,11,166402,15,0,1806,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-10 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-10,0,2.91822,71192,1,0,11,166402,16,0,1811,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-11 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-11,0,2.92067,71192,1,0,11,166402,17,0,1820,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-12 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-12,0,2.92886,71192,1,0,11,166402,18,0,1832,279706,0
Reachability property LamportFastMutEx-PT-4-ReachabilityCardinality-13 does not hold.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-4-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-13,0,2.93283,71192,1,0,11,166402,19,0,1843,279706,0
Invariant property LamportFastMutEx-PT-4-ReachabilityCardinality-14 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-14,0,2.93357,71192,1,0,11,166402,20,0,1853,279706,0
Invariant property LamportFastMutEx-PT-4-ReachabilityCardinality-15 is true.
FORMULA LamportFastMutEx-PT-4-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-4-ReachabilityCardinality-15,0,2.95303,71192,1,0,11,166402,21,0,1880,279706,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527165322006

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:35:18 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:35:18 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:35:18 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 64 ms
May 24, 2018 12:35:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 135 places.
May 24, 2018 12:35:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 230 transitions.
May 24, 2018 12:35:18 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 19 ms
May 24, 2018 12:35:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 93 ms
May 24, 2018 12:35:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 68 ms
May 24, 2018 12:35:18 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 7 ms
May 24, 2018 12:35:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 62 ms
May 24, 2018 12:35:18 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:35:18 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 230 transitions.
May 24, 2018 12:35:18 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 230 transitions.
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 37 place invariants in 71 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 15 in 584 ms.
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-00(UNSAT) depth K=0 took 2 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-01(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-02(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-03(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 230 transitions.
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-04(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-06(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-07(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-08(UNSAT) depth K=0 took 13 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-09(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-10(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-11(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-12(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-13(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-14(UNSAT) depth K=0 took 19 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-15(UNSAT) depth K=0 took 14 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 37 place invariants in 26 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-00(UNSAT) depth K=1 took 21 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-01(UNSAT) depth K=1 took 10 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-02(UNSAT) depth K=1 took 21 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-03(UNSAT) depth K=1 took 13 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-04(UNSAT) depth K=1 took 22 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-06(UNSAT) depth K=1 took 16 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-07(UNSAT) depth K=1 took 16 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-08(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-09(UNSAT) depth K=1 took 20 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-10(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-11(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-12(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-13(UNSAT) depth K=1 took 20 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-14(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-15(UNSAT) depth K=1 took 20 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-00(UNSAT) depth K=2 took 120 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-01(UNSAT) depth K=2 took 72 ms
May 24, 2018 12:35:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-02(UNSAT) depth K=2 took 122 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-03(UNSAT) depth K=2 took 129 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-04(UNSAT) depth K=2 took 89 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-06(UNSAT) depth K=2 took 31 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-07(UNSAT) depth K=2 took 29 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-08(UNSAT) depth K=2 took 22 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-09(UNSAT) depth K=2 took 63 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-10(UNSAT) depth K=2 took 24 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-11(UNSAT) depth K=2 took 38 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 135 variables to be positive in 1353 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 230 transitions.
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/230 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-12(UNSAT) depth K=2 took 36 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 15 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 230 transitions.
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 14 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-13(UNSAT) depth K=2 took 66 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 135 variables to be positive in 1149 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-14(UNSAT) depth K=2 took 59 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-15(UNSAT) depth K=2 took 51 ms
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-4-ReachabilityCardinality-00
May 24, 2018 12:35:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-00(SAT) depth K=0 took 212 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-4-ReachabilityCardinality-01
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-01(SAT) depth K=0 took 332 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-00(UNSAT) depth K=3 took 728 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-4-ReachabilityCardinality-02
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-02(SAT) depth K=0 took 296 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-4-ReachabilityCardinality-03
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-03(SAT) depth K=0 took 120 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-4-ReachabilityCardinality-04
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-4-ReachabilityCardinality-04(SAT) depth K=0 took 244 ms
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeAblingForPredicate(NecessaryEnablingsolver.java:766)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:502)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-4-ReachabilityCardinality-01 SMT depth 3
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-4-ReachabilityCardinality-06 K-induction depth 0
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 3
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 3
May 24, 2018 12:35:21 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 15 properties. Interrupting other analysis methods.
May 24, 2018 12:35:21 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 3199ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-4"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-4.tgz
mv LamportFastMutEx-PT-4 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-4, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475000124"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;