fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r116-csrt-152666474900068
Last Updated
June 26, 2018

About the Execution of ITS-Tools for LamportFastMutEx-COL-3

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15743.140 5788.00 13208.00 172.00 TTTTFFTFFTTFTFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................................................................................
/home/mcc/execution
total 212K
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.1K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 39K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-COL-3, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666474900068
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-3-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527163208950

12:00:11.782 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
12:00:11.784 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-00 with value :((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)>=1)
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-01 with value :(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)>=3)||((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)<=(((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3))&&((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)<=(((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)))||(((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7))||((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)))))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-02 with value :(true)
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-03 with value :(((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)>=1)||((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)>=1))||(!((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7))))&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)<=(((y_0+y_1)+y_2)+y_3))&&((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)>=1))||(((((x_0+x_1)+x_2)+x_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7))||((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)>=2))))
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-04 with value :(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)>=3)&&((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)<=(((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-05 with value :((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)<=(((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-06 with value :((!(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)>=1)&&((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)>=3)))||((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)>=1)&&((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)<=(((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)))||(((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)<=(((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3))&&((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)>=3))))
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-07 with value :((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)>=2)
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-08 with value :(((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)>=1)&&((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)<=(((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)))
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-09 with value :(((((y_0+y_1)+y_2)+y_3)>=1)&&((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7))||((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)<=(((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)))&&(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)>=1)&&((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)>=2))))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-10 with value :(true)
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-11 with value :((!((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)>=2))||((!((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)>=3))||(!((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)>=1))))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-12 with value :(((!((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)<=(((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)))||(!((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)>=2)))||((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)))
Read [reachable] property : LamportFastMutEx-COL-3-ReachabilityCardinality-13 with value :(((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)<=(((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3))||((((y_0+y_1)+y_2)+y_3)<=(((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)))&&(((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)>=1)&&((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)>=2)))&&((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)>=1)||((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)<=(((x_0+x_1)+x_2)+x_3)))&&(!((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)<=(((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)))))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-14 with value :(((!((((x_0+x_1)+x_2)+x_3)<=(((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)))&&(((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)<=(((x_0+x_1)+x_2)+x_3))&&((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)>=2)))||(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)<=(((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15))||(!((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)>=1))))
Read [invariant] property : LamportFastMutEx-COL-3-ReachabilityCardinality-15 with value :(!((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)>=2))
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-02 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 132
// Phase 1: matrix 132 rows 100 cols
invariant :wait_11 + -1'P_await_13_2 + done_11 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_8 + done_8 = 0
invariant :wait_15 + -1'P_await_13_3 + done_15 = 0
invariant :b_0 + b_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :y_0 + y_1 + y_2 + y_3 = 1
invariant :b_6 + b_7 = 1
invariant :wait_4 + done_4 = 0
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :wait_13 + -1'P_await_13_3 + done_13 = 0
invariant :wait_14 + -1'P_await_13_3 + done_14 = 0
invariant :b_4 + b_5 = 1
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_0 + done_0 = 0
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_12 + done_12 = 0
invariant :wait_10 + -1'P_await_13_2 + done_10 = 0
invariant :b_2 + b_3 = 1
invariant :wait_9 + -1'P_await_13_2 + done_9 = 0
invariant :wait_6 + -1'P_await_13_1 + done_6 = 0
invariant :x_0 + x_1 + x_2 + x_3 = 1
invariant :wait_5 + -1'P_await_13_1 + done_5 = 0
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-10 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 132
// Phase 1: matrix 132 rows 100 cols
invariant :wait_11 + -1'P_await_13_2 + done_11 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_8 + done_8 = 0
invariant :wait_15 + -1'P_await_13_3 + done_15 = 0
invariant :b_0 + b_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :y_0 + y_1 + y_2 + y_3 = 1
invariant :b_6 + b_7 = 1
invariant :wait_4 + done_4 = 0
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :wait_13 + -1'P_await_13_3 + done_13 = 0
invariant :wait_14 + -1'P_await_13_3 + done_14 = 0
invariant :b_4 + b_5 = 1
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_0 + done_0 = 0
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_12 + done_12 = 0
invariant :wait_10 + -1'P_await_13_2 + done_10 = 0
invariant :b_2 + b_3 = 1
invariant :wait_9 + -1'P_await_13_2 + done_9 = 0
invariant :wait_6 + -1'P_await_13_1 + done_6 = 0
invariant :x_0 + x_1 + x_2 + x_3 = 1
invariant :wait_5 + -1'P_await_13_1 + done_5 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_COL\_3\_flat\_flat,19742,0.846021,29688,2,4025,5,91808,6,0,588,104107,0
Total reachable state count : 19742

Verifying 16 reachability properties.
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-00 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-00,1,0.847094,29716,2,101,6,91808,7,0,593,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-01 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-01,0,0.853841,29756,1,0,6,91808,8,0,641,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-02 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-02,0,0.854008,29820,1,0,6,91808,8,0,641,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-03 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-03,0,0.866311,29820,1,0,6,91808,9,0,726,104107,0
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-04 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-3-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-04,0,0.871035,29820,1,0,6,91808,10,0,763,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-05 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-05,1,0.873112,29820,2,101,7,91808,11,0,791,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-06 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-06,0,0.884041,29820,1,0,7,91808,12,0,883,104107,0
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-07 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-3-ReachabilityCardinality-07

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-07,0,0.886543,29820,1,0,7,91808,13,0,890,104107,0
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-08 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-3-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-08,0,0.891971,29820,1,0,7,91808,14,0,946,104107,0
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-09 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-09,24,0.900902,29820,2,328,8,91808,15,0,1005,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-10 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-10,0,0.901075,29820,1,0,8,91808,15,0,1005,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-11 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-11,315,0.917068,29820,2,491,9,91808,16,0,1153,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-12 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-12,0,0.924679,29820,1,0,9,91808,17,0,1221,104107,0
Reachability property LamportFastMutEx-COL-3-ReachabilityCardinality-13 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-3-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-13,0,0.93464,29820,1,0,9,91808,18,0,1320,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-14 does not hold.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-14,1,0.937729,29820,2,101,9,91808,19,0,1379,104107,0
Invariant property LamportFastMutEx-COL-3-ReachabilityCardinality-15 is true.
FORMULA LamportFastMutEx-COL-3-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-3-ReachabilityCardinality-15,0,0.937943,29820,1,0,9,91808,19,0,1379,104107,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527163214738

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:00:11 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:00:11 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:00:11 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 811 ms
May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 24, 2018 12:00:12 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 24, 2018 12:00:12 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 6 ms
May 24, 2018 12:00:12 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 24, 2018 12:00:12 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 24, 2018 12:00:12 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 9.0 instantiations of transitions. Total transitions/syncs built is 175
May 24, 2018 12:00:12 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 143 ms
May 24, 2018 12:00:13 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 39 ms
May 24, 2018 12:00:13 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 5 ms
May 24, 2018 12:00:13 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 32 ms
May 24, 2018 12:00:13 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:00:13 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 48 transitions. Expanding to a total of 203 deterministic transitions.
May 24, 2018 12:00:13 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 3 ms.
May 24, 2018 12:00:13 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 48 transitions. Expanding to a total of 203 deterministic transitions.
May 24, 2018 12:00:13 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 18 ms.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 26 place invariants in 20 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 2 / 16 in 999 ms.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-00(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-01(UNSAT) depth K=0 took 19 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 48 transitions. Expanding to a total of 203 deterministic transitions.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 2 ms.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-03(UNSAT) depth K=0 took 15 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-04(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-05(UNSAT) depth K=0 took 3 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-06(UNSAT) depth K=0 took 19 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-07(UNSAT) depth K=0 took 2 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-08(UNSAT) depth K=0 took 8 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-09(UNSAT) depth K=0 took 2 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-11(UNSAT) depth K=0 took 6 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-12(UNSAT) depth K=0 took 10 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-13(UNSAT) depth K=0 took 8 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-14(UNSAT) depth K=0 took 9 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 26 place invariants in 16 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-15(UNSAT) depth K=0 took 18 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-00(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-01(UNSAT) depth K=1 took 5 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-03(UNSAT) depth K=1 took 4 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-04(UNSAT) depth K=1 took 17 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-05(UNSAT) depth K=1 took 13 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-06(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-07(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-08(UNSAT) depth K=1 took 19 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-09(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-11(UNSAT) depth K=1 took 20 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-12(UNSAT) depth K=1 took 15 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-13(UNSAT) depth K=1 took 19 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-14(UNSAT) depth K=1 took 35 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-3-ReachabilityCardinality-15(UNSAT) depth K=1 took 2 ms
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Failed to check-sat")
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Exception in thread "Thread-8" java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:00:14 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 2/ 16 properties. Interrupting other analysis methods.
May 24, 2018 12:00:14 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1023ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-3"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-3.tgz
mv LamportFastMutEx-COL-3 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-3, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666474900068"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;