About the Execution of Irma.full for Peterson-PT-5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3484.880 | 228380.00 | 467626.00 | 795.40 | ???????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
..................................................
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 90K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 242K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 63K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 204K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 32K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 22K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 69K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 230K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 9.5K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 911K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool irma4mcc-full
Input is Peterson-PT-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r114-csrt-152666472900579
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-00
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-01
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-02
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-03
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-04
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-05
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-06
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-07
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-08
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-09
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-10
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-11
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-12
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-13
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-14
FORMULA_NAME Peterson-PT-5-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1527142946148
BK_STOP 1527143174528
--------------------
content from stderr:
Prefix is 65b80f64.
Reading known information in /usr/share/mcc4mcc/65b80f64-known.json.
Reading learned information in /usr/share/mcc4mcc/65b80f64-learned.json.
Reading value translations in /usr/share/mcc4mcc/65b80f64-values.json.
Using directory /home/mcc/execution for input, as it contains a model.pnml file.
Using Peterson-PT-5 as instance name.
Using Peterson as model name.
Using algorithm or tool bmdt.
Model characteristics are: {'Examination': 'ReachabilityCardinality', 'Place/Transition': True, 'Colored': True, 'Relative-Time': 1, 'Relative-Memory': 1, 'Ordinary': True, 'Simple Free Choice': False, 'Extended Free Choice': False, 'State Machine': False, 'Marked Graph': False, 'Connected': True, 'Strongly Connected': True, 'Source Place': False, 'Sink Place': False, 'Source Transition': False, 'Sink Transition': False, 'Loop Free': False, 'Conservative': True, 'Sub-Conservative': True, 'Nested Units': False, 'Safe': True, 'Deadlock': False, 'Reversible': True, 'Quasi Live': None, 'Live': None}.
Known tools are: [{'Time': 324621, 'Memory': 5812.61, 'Tool': 'lola'}, {'Time': 324916, 'Memory': 9368.96, 'Tool': 'lola'}].
Learned tools are: [{'Tool': 'gspn'}].
ReachabilityCardinality lola Peterson-PT-5...
Time: 3600 - MCC
----- Start make prepare stdout -----
----- Start make prepare stderr -----
===========================================================================================
Peterson-PT-5: translating PT Petri net model.pnml into LoLA format
===========================================================================================
translating PT Petri net complete
checking for too many tokens
===========================================================================================
Peterson-PT-5: translating PT formula ReachabilityCardinality into LoLA format
===========================================================================================
translating formula complete
touch formulae;
----- Start make result stderr -----
----- Start make result stdout -----
ReachabilityCardinality @ Peterson-PT-5 @ 3539 seconds
Makefile:222: recipe for target 'verify' failed
----- Start make result stdout -----
make: [verify] Error 134 (ignored)
----- Start make result stderr -----
lola: LoLA will run for 3539 seconds at most (--timelimit)
lola: NET
lola: reading net from model.pnml.lola
lola: finished parsing
lola: closed net file model.pnml.lola
lola: 2076/65536 symbol table entries, 0 collisions
lola: preprocessing...
lola: finding significant places
lola: 834 places, 1242 transitions, 811 significant places
lola: computing forward-conflicting sets
lola: computing back-conflicting sets
lola: 1908 transition conflict sets
lola: TASK
lola: reading formula from Peterson-PT-5-ReachabilityCardinality.task
lola: E (F (((WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_0_5 + TestIdentity_3_4_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_1_1_5 + TestIdentity_3_4_3 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_4_0_5 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_1_2_5 + TestIdentity_3_4_2 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_4_1_5 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_1_3_5 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_2_5 + TestIdentity_1_4_0 + TestIdentity_1_4_1 + TestIdentity_1_4_2 + TestIdentity_1_4_3 + TestIdentity_1_4_4 + TestIdentity_1_4_5 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_4_3_5 + TestIdentity_4_4_0 + TestIdentity_4_4_1 + TestIdentity_4_4_2 + TestIdentity_4_4_3 + TestIdentity_4_4_4 + TestIdentity_4_4_5 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_0_5 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_1_5 + TestIdentity_3_4_1 + TestIdentity_3_4_0 + TestIdentity_5_0_0 + TestIdentity_5_0_1 + TestIdentity_5_0_2 + TestIdentity_5_0_3 + TestIdentity_5_0_4 + TestIdentity_5_0_5 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_2_5 + TestIdentity_5_1_0 + TestIdentity_5_1_1 + TestIdentity_5_1_2 + TestIdentity_5_1_3 + TestIdentity_5_1_4 + TestIdentity_5_1_5 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_2_3_5 + TestIdentity_5_2_0 + TestIdentity_5_2_1 + TestIdentity_5_2_2 + TestIdentity_5_2_3 + TestIdentity_5_2_4 + TestIdentity_5_2_5 + TestIdentity_2_4_0 + TestIdentity_2_4_1 + TestIdentity_2_4_2 + TestIdentity_2_4_3 + TestIdentity_2_4_4 + TestIdentity_2_4_5 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_0_5 + TestIdentity_5_3_0 + TestIdentity_5_3_1 + TestIdentity_5_3_2 + TestIdentity_5_3_3 + TestIdentity_5_3_4 + TestIdentity_5_3_5 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_0_1_5 + TestIdentity_5_4_0 + TestIdentity_5_4_1 + TestIdentity_5_4_2 + TestIdentity_5_4_3 + TestIdentity_5_4_4 + TestIdentity_5_4_5 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_3_0_5 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_0_2_5 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_3_1_5 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_0_3_5 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_2_5 + TestIdentity_0_4_0 + TestIdentity_0_4_1 + TestIdentity_0_4_2 + TestIdentity_0_4_3 + TestIdentity_0_4_4 + TestIdentity_0_4_5 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 + TestIdentity_3_3_5 + TestIdentity_3_4_5) OR (WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F + 1 <= AskForSection_5_0 + AskForSection_5_1 + AskForSection_5_2 + AskForSection_5_3 + AskForSection_5_4 + AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_0_4 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_1_4 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_2_4 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_3_4 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 + AskForSection_4_3 + AskForSection_4_4) OR (Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_2_4 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_3_4 + Turn_4_0 + Turn_4_1 + Turn_4_2 + Turn_4_3 + Turn_4_4 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_0 + Turn_1_1 + Turn_1_2 + Turn_1_3 + Turn_1_4 + Turn_1_5 + Turn_0_5 + Turn_4_5 + Turn_3_5 + Turn_2_5 + 1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4 + CS_5)))) : E (F ((WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 2))) : E (F (((Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 + Idle_5 <= 0) AND (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 + CS_5 <= 1) AND (AskForSection_5_0 + AskForSection_5_1 + AskForSection_5_2 + AskForSection_5_3 + AskForSection_5_4 + AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_0_4 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_1_4 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_2_4 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_3_4 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 + AskForSection_4_3 + AskForSection_4_4 + 1 <= TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_0_4 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_1_4 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_2_4 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_3_4 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + TestTurn_4_4 + TestTurn_5_0 + TestTurn_5_1 + TestTurn_5_2 + TestTurn_5_3 + TestTurn_5_4)))) : A (G (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_0_4 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_1_4 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_2_4 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_3_4 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + TestTurn_4_4 + TestTurn_5_0 + TestTurn_5_1 + TestTurn_5_2 + TestTurn_5_3 + TestTurn_5_4 + 1 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_0_5 + IsEndLoop_5_3_0 + IsEndLoop_5_3_1 + IsEndLoop_5_3_2 + IsEndLoop_5_3_3 + IsEndLoop_5_3_4 + IsEndLoop_5_3_5 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_0_1_5 + IsEndLoop_5_4_0 + IsEndLoop_5_4_1 + IsEndLoop_5_4_2 + IsEndLoop_5_4_3 + IsEndLoop_5_4_4 + IsEndLoop_5_4_5 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_3_0_5 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_0_2_5 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_3_1_5 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_0_3_5 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_2_5 + IsEndLoop_0_4_0 + IsEndLoop_0_4_1 + IsEndLoop_0_4_2 + IsEndLoop_0_4_3 + IsEndLoop_0_4_4 + IsEndLoop_0_4_5 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_3_3_5 + IsEndLoop_3_4_0 + IsEndLoop_3_4_1 + IsEndLoop_3_4_2 + IsEndLoop_3_4_3 + IsEndLoop_3_4_4 + IsEndLoop_3_4_5 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_0_5 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_1_1_5 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_4_0_5 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_1_2_5 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_4_1_5 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_1_3_5 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_2_5 + IsEndLoop_1_4_0 + IsEndLoop_1_4_1 + IsEndLoop_1_4_2 + IsEndLoop_1_4_3 + IsEndLoop_1_4_4 + IsEndLoop_1_4_5 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_4_3_5 + IsEndLoop_4_4_0 + IsEndLoop_4_4_1 + IsEndLoop_4_4_2 + IsEndLoop_4_4_3 + IsEndLoop_4_4_4 + IsEndLoop_4_4_5 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_0_5 + IsEndLoop_2_4_4 + IsEndLoop_2_4_3 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_1_5 + IsEndLoop_5_0_0 + IsEndLoop_5_0_1 + IsEndLoop_5_0_2 + IsEndLoop_5_0_3 + IsEndLoop_5_0_4 + IsEndLoop_5_0_5 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_2_5 + IsEndLoop_2_4_2 + IsEndLoop_5_1_0 + IsEndLoop_5_1_1 + IsEndLoop_5_1_2 + IsEndLoop_5_1_3 + IsEndLoop_5_1_4 + IsEndLoop_5_1_5 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 + IsEndLoop_2_3_5 + IsEndLoop_2_4_1 + IsEndLoop_5_2_0 + IsEndLoop_5_2_1 + IsEndLoop_5_2_2 + IsEndLoop_5_2_3 + IsEndLoop_5_2_4 + IsEndLoop_2_4_0 + IsEndLoop_5_2_5 + IsEndLoop_2_4_5) OR (EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_1_4 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_2_4 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_3_4 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_4_4 + EndTurn_5_0 + EndTurn_5_1 + EndTurn_5_2 + EndTurn_5_3 + EndTurn_5_4 + EndTurn_0_3 + EndTurn_0_2 + EndTurn_0_1 + EndTurn_0_0 + EndTurn_0_4 <= 0) OR (2 <= Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 + Idle_5)))) : A (G (((EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_1_4 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_2_4 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_3_4 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_4_4 + EndTurn_5_0 + EndTurn_5_1 + EndTurn_5_2 + EndTurn_5_3 + EndTurn_5_4 + EndTurn_0_3 + EndTurn_0_2 + EndTurn_0_1 + EndTurn_0_0 + EndTurn_0_4 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_2_4 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_3_4 + Turn_4_0 + Turn_4_1 + Turn_4_2 + Turn_4_3 + Turn_4_4 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_0 + Turn_1_1 + Turn_1_2 + Turn_1_3 + Turn_1_4 + Turn_1_5 + Turn_0_5 + Turn_4_5 + Turn_3_5 + Turn_2_5) OR (((2 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_0_5 + IsEndLoop_5_3_0 + IsEndLoop_5_3_1 + IsEndLoop_5_3_2 + IsEndLoop_5_3_3 + IsEndLoop_5_3_4 + IsEndLoop_5_3_5 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_0_1_5 + IsEndLoop_5_4_0 + IsEndLoop_5_4_1 + IsEndLoop_5_4_2 + IsEndLoop_5_4_3 + IsEndLoop_5_4_4 + IsEndLoop_5_4_5 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_3_0_5 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_0_2_5 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_3_1_5 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_0_3_5 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_2_5 + IsEndLoop_0_4_0 + IsEndLoop_0_4_1 + IsEndLoop_0_4_2 + IsEndLoop_0_4_3 + IsEndLoop_0_4_4 + IsEndLoop_0_4_5 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_3_3_5 + IsEndLoop_3_4_0 + IsEndLoop_3_4_1 + IsEndLoop_3_4_2 + IsEndLoop_3_4_3 + IsEndLoop_3_4_4 + IsEndLoop_3_4_5 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_0_5 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_1_1_5 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_4_0_5 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_1_2_5 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_4_1_5 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_1_3_5 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_2_5 + IsEndLoop_1_4_0 + IsEndLoop_1_4_1 + IsEndLoop_1_4_2 + IsEndLoop_1_4_3 + IsEndLoop_1_4_4 + IsEndLoop_1_4_5 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_4_3_5 + IsEndLoop_4_4_0 + IsEndLoop_4_4_1 + IsEndLoop_4_4_2 + IsEndLoop_4_4_3 + IsEndLoop_4_4_4 + IsEndLoop_4_4_5 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_0_5 + IsEndLoop_2_4_4 + IsEndLoop_2_4_3 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_1_5 + IsEndLoop_5_0_0 + IsEndLoop_5_0_1 + IsEndLoop_5_0_2 + IsEndLoop_5_0_3 + IsEndLoop_5_0_4 + IsEndLoop_5_0_5 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_2_5 + IsEndLoop_2_4_2 + IsEndLoop_5_1_0 + IsEndLoop_5_1_1 + IsEndLoop_5_1_2 + IsEndLoop_5_1_3 + IsEndLoop_5_1_4 + IsEndLoop_5_1_5 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 + IsEndLoop_2_3_5 + IsEndLoop_2_4_1 + IsEndLoop_5_2_0 + IsEndLoop_5_2_1 + IsEndLoop_5_2_2 + IsEndLoop_5_2_3 + IsEndLoop_5_2_4 + IsEndLoop_2_4_0 + IsEndLoop_5_2_5 + IsEndLoop_2_4_5) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 + CS_5 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_4_3_5 + TestAlone_4_4_0 + TestAlone_4_4_1 + TestAlone_4_4_2 + TestAlone_4_4_3 + TestAlone_4_4_5 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_0_5 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_1_5 + TestAlone_5_0_0 + TestAlone_5_0_1 + TestAlone_5_0_2 + TestAlone_5_0_3 + TestAlone_5_0_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_2_5 + TestAlone_5_1_0 + TestAlone_5_1_1 + TestAlone_5_1_2 + TestAlone_5_1_3 + TestAlone_5_1_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_2_3_5 + TestAlone_5_2_0 + TestAlone_5_2_1 + TestAlone_5_2_2 + TestAlone_5_2_3 + TestAlone_5_2_4 + TestAlone_2_4_0 + TestAlone_2_4_1 + TestAlone_2_4_3 + TestAlone_2_4_4 + TestAlone_2_4_5 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_0_5 + TestAlone_5_3_0 + TestAlone_5_3_1 + TestAlone_5_3_2 + TestAlone_5_3_3 + TestAlone_5_3_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_0_1_5 + TestAlone_5_4_0 + TestAlone_5_4_1 + TestAlone_5_4_2 + TestAlone_5_4_3 + TestAlone_5_4_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_3_0_5 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_0_2_5 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1
_2 + TestAlone_3_1_4 + TestAlone_3_1_5 + TestAlone_1_4_4 + TestAlone_1_4_3 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_0_3_5 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_2_5 + TestAlone_1_4_2 + TestAlone_1_4_0 + TestAlone_0_4_1 + TestAlone_0_4_2 + TestAlone_0_4_3 + TestAlone_0_4_4 + TestAlone_0_4_5 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_3_3_5 + TestAlone_3_4_0 + TestAlone_3_4_1 + TestAlone_3_4_2 + TestAlone_3_4_4 + TestAlone_3_4_5 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_0_5 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_1_1_5 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_4_0_5 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_1_2_5 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_4_1_5 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_1_3_5 + TestAlone_4_2_0 + TestAlone_4_2_1 + TestAlone_4_2_2 + TestAlone_4_2_3 + TestAlone_4_2_5 + TestAlone_1_4_5)) AND (Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_2_4 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_3_4 + Turn_4_0 + Turn_4_1 + Turn_4_2 + Turn_4_3 + Turn_4_4 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_0 + Turn_1_1 + Turn_1_2 + Turn_1_3 + Turn_1_4 + Turn_1_5 + Turn_0_5 + Turn_4_5 + Turn_3_5 + Turn_2_5 <= 1))))) : E (F (((3 <= AskForSection_5_0 + AskForSection_5_1 + AskForSection_5_2 + AskForSection_5_3 + AskForSection_5_4 + AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_0_4 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_1_4 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_2_4 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_3_4 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 + AskForSection_4_3 + AskForSection_4_4) AND (BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_4_3_5 + BeginLoop_4_4_0 + BeginLoop_4_4_1 + BeginLoop_4_4_2 + BeginLoop_4_4_3 + BeginLoop_4_4_4 + BeginLoop_4_4_5 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_0_5 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_1_5 + BeginLoop_5_0_0 + BeginLoop_5_0_1 + BeginLoop_5_0_2 + BeginLoop_5_0_3 + BeginLoop_5_0_4 + BeginLoop_5_0_5 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_2_5 + BeginLoop_5_1_0 + BeginLoop_5_1_1 + BeginLoop_5_1_2 + BeginLoop_5_1_3 + BeginLoop_5_1_4 + BeginLoop_5_1_5 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_2_3_5 + BeginLoop_5_2_0 + BeginLoop_5_2_1 + BeginLoop_5_2_2 + BeginLoop_5_2_3 + BeginLoop_5_2_4 + BeginLoop_5_2_5 + BeginLoop_2_4_0 + BeginLoop_2_4_1 + BeginLoop_2_4_2 + BeginLoop_2_4_3 + BeginLoop_2_4_4 + BeginLoop_2_4_5 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_0_5 + BeginLoop_5_3_0 + BeginLoop_5_3_1 + BeginLoop_5_3_2 + BeginLoop_5_3_3 + BeginLoop_5_3_4 + BeginLoop_5_3_5 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_0_1_5 + BeginLoop_5_4_0 + BeginLoop_5_4_1 + BeginLoop_5_4_2 + BeginLoop_5_4_3 + BeginLoop_5_4_4 + BeginLoop_5_4_5 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_3_0_5 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_0_2_5 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_3_1_5 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_0_3_5 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_2_5 + BeginLoop_0_4_0 + BeginLoop_0_4_1 + BeginLoop_0_4_2 + BeginLoop_0_4_3 + BeginLoop_0_4_4 + BeginLoop_0_4_5 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_3_3_5 + BeginLoop_3_4_0 + BeginLoop_3_4_1 + BeginLoop_3_4_2 + BeginLoop_3_4_3 + BeginLoop_3_4_4 + BeginLoop_3_4_5 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_0_5 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_1_1_5 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_4_0_5 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_1_2_5 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_1_5 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_1_3_5 + BeginLoop_4_2_0 + BeginLoop_4_2_1 + BeginLoop_4_2_2 + BeginLoop_4_2_3 + BeginLoop_4_2_4 + BeginLoop_4_2_5 + BeginLoop_1_4_0 + BeginLoop_1_4_1 + BeginLoop_1_4_2 + BeginLoop_1_4_3 + BeginLoop_1_4_4 + BeginLoop_1_4_5 <= 1) AND (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_0_4 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_1_4 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_2_4 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_3_4 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + TestTurn_4_4 + TestTurn_5_0 + TestTurn_5_1 + TestTurn_5_2 + TestTurn_5_3 + TestTurn_5_4 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_0_5 + IsEndLoop_5_3_0 + IsEndLoop_5_3_1 + IsEndLoop_5_3_2 + IsEndLoop_5_3_3 + IsEndLoop_5_3_4 + IsEndLoop_5_3_5 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_0_1_5 + IsEndLoop_5_4_0 + IsEndLoop_5_4_1 + IsEndLoop_5_4_2 + IsEndLoop_5_4_3 + IsEndLoop_5_4_4 + IsEndLoop_5_4_5 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_3_0_5 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_0_2_5 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_3_1_5 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_0_3_5 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_2_5 + IsEndLoop_0_4_0 + IsEndLoop_0_4_1 + IsEndLoop_0_4_2 + IsEndLoop_0_4_3 + IsEndLoop_0_4_4 + IsEndLoop_0_4_5 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_3_3_5 + IsEndLoop_3_4_0 + IsEndLoop_3_4_1 + IsEndLoop_3_4_2 + IsEndLoop_3_4_3 + IsEndLoop_3_4_4 + IsEndLoop_3_4_5 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_0_5 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_1_1_5 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_4_0_5 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_1_2_5 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_4_1_5 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_1_3_5 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_2_5 + IsEndLoop_1_4_0 + IsEndLoop_1_4_1 + IsEndLoop_1_4_2 + IsEndLoop_1_4_3 + IsEndLoop_1_4_4 + IsEndLoop_1_4_5 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_4_3_5 + IsEndLoop_4_4_0 + IsEndLoop_4_4_1 + IsEndLoop_4_4_2 + IsEndLoop_4_4_3 + IsEndLoop_4_4_4 + IsEndLoop_4_4_5 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_0_5 + IsEndLoop_2_4_4 + IsEndLoop_2_4_3 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_1_5 + IsEndLoop_5_0_0 + IsEndLoop_5_0_1 + IsEndLoop_5_0_2 + IsEndLoop_5_0_3 + IsEndLoop_5_0_4 + IsEndLoop_5_0_5 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_2_5 + IsEndLoop_2_4_2 + IsEndLoop_5_1_0 + IsEndLoop_5_1_1 + IsEndLoop_5_1_2 + IsEndLoop_5_1_3 + IsEndLoop_5_1_4 + IsEndLoop_5_1_5 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 + IsEndLoop_2_3_5 + IsEndLoop_2_4_1 + IsEndLoop_5_2_0 + IsEndLoop_5_2_1 + IsEndLoop_5_2_2 + IsEndLoop_5_2_3 + IsEndLoop_5_2_4 + IsEndLoop_2_4_0 + IsEndLoop_5_2_5 + IsEndLoop_2_4_5) AND (WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_4_3_5 + TestAlone_4_4_0 + TestAlone_4_4_1 + TestAlone_4_4_2 + TestAlone_4_4_3 + TestAlone_4_4_5 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_0_5 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_1_5 + TestAlone_5_0_0 + TestAlone_5_0_1 + TestAlone_5_0_2 + TestAlone_5_0_3 + TestAlone_5_0_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_2_5 + TestAlone_5_1_0 + TestAlone_5_1_1 + TestAlone_5_1_2 + TestAlone_5_1_3 + TestAlone_5_1_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_2_3_5 + TestAlone_5_2_0 + TestAlone_5_2_1 + TestAlone_5_2_2 + TestAlone_5_2_3 + TestAlone_5_2_4 + TestAlone_2_4_0 + TestAlone_2_4_1 + TestAlone_2_4_3 + TestAlone_2_4_4 + TestAlone_2_4_5 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_0_5 + TestAlone_5_3_0 + TestAlone_5_3_1 + TestAlone_5_3_2 + TestAlone_5_3_3 + TestAlone_5_3_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_0_1_5 + TestAlone_5_4_0 + TestAlone_5_4_1 + TestAlone_5_4_2 + TestAlone_5_4_3 + TestAlone_5_4_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_3_0_5 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_0_2_5 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_3_1_5 + TestAlone_1_4_4 + TestAlone_1_4_3 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_0_3_5 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_2_5 + TestAlone_1_4_2 + TestAlone_1_4_0 + TestAlone_0_4_1 + TestAlone_0_4_2 + TestAlone_0_4_3 + TestAlone_0_4_4 + TestAlone_0_4_5 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_3_3_5 + TestAlone_3_4_0 + TestAlone_3_4_1 + TestAlone_3_4_2 + TestAlone_3_4_4 + TestAlone_3_4_5 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_0_5 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_1_1_5 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_4_0_5 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_1_2_5 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_4_1_5 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_1_3_5 + TestAlone_4_2_0 + TestAlone_4_2_1 + TestAlone_4_2_2 + TestAlone_4_2_3 + TestAlone_4_2_5 + TestAlone_1_4_5)) OR (1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4 + CS_5))))) : A (G ((1 <= WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F))) : E (F (FALSE)) : E (F ((((BeginLoop_2_3_0 + 1 <= IsEndLoop_0_1_3) OR (IsEndLoop_4_0_5 + 1 <= AskForSection_2_4)) AND (IsEndLoop_4_4_5 <= BeginLoop_0_4_0)))) : A (G ((TestIdentity_5_3_3 <= BeginLoop_2_3_4))) : E (F ((((1 <= TestIdentity_2_3_1) OR (BeginLoop_5_1_3 <= IsEndLoop_3_4_1)) AND (TestAlone_0_2_4 + 1 <= CS_4) AND (2 <= TestIdentity_0_3_0)))) : E (F ((1 <= BeginLoop_1_2_0))) : A (G ((TestIdentity_0_0_4 <= TestTurn_2_3))) : E (F ((IsEndLoop_2_3_3 + 1 <= Turn_3_4))) : A (G ((((TestIdentity_5_3_3 <= 2) OR (CS_0 <= 1)) AND (TestIdentity_0_4_1 <= BeginLoop_3_1_0)))) : E (F ((2 <= TestIdentity_3_3_0)))
lola: computing a collection of formulas
lola: RUNNING
lola: subprocess 0 will run for 221 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((WantSection_5_T + WantSection_5_F + WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_0_5 + TestIdentity_3_4_4 + TestIdentity_1_1_0 + Tes... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 104 bytes per marking, with 21 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 3 literals and 3 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-PT-5-ReachabilityCardinality.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-PT-5-ReachabilityCardinality.sara.
sara: place or transition ordering is non-deterministic
lola: sara is running 0 secs || 116122 markings, 311303 edges, 23224 markings/sec, 0 secs
lola: sara is running 5 secs || 228530 markings, 722905 edges, 22482 markings/sec, 5 secs
lola: sara is running 10 secs || 326309 markings, 1310505 edges, 19556 markings/sec, 10 secs
lola: sara is running 15 secs || 418543 markings, 1864500 edges, 18447 markings/sec, 15 secs
lola: sara is running 20 secs || 512577 markings, 2429597 edges, 18807 markings/sec, 20 secs
lola: sara is running 25 secs || 608132 markings, 3002831 edges, 19111 markings/sec, 25 secs
lola: sara is running 30 secs || 702754 markings, 3570359 edges, 18924 markings/sec, 30 secs
lola: sara is running 35 secs || 797001 markings, 4135621 edges, 18849 markings/sec, 35 secs
lola: sara is running 40 secs || 892578 markings, 4707636 edges, 19115 markings/sec, 40 secs
lola: sara is running 45 secs || 987987 markings, 5272747 edges, 19082 markings/sec, 45 secs
lola: sara is running 50 secs || 1057232 markings, 5696353 edges, 13849 markings/sec, 50 secs
lola: sara is running 55 secs || 1138222 markings, 6459908 edges, 16198 markings/sec, 55 secs
lola: sara is running 60 secs || 1209859 markings, 7014076 edges, 14327 markings/sec, 60 secs
lola: sara is running 65 secs || 1267009 markings, 7177584 edges, 11430 markings/sec, 65 secs
lola: sara is running 70 secs || 1326227 markings, 7360053 edges, 11844 markings/sec, 70 secs
lola: sara is running 75 secs || 1376449 markings, 7620171 edges, 10044 markings/sec, 75 secs
lola: sara is running 80 secs || 1423997 markings, 7905332 edges, 9510 markings/sec, 80 secs
lola: sara is running 85 secs || 1476148 markings, 8216969 edges, 10430 markings/sec, 85 secs
lola: sara is running 90 secs || 1527471 markings, 8527366 edges, 10265 markings/sec, 90 secs
lola: sara is running 95 secs || 1581864 markings, 8853968 edges, 10879 markings/sec, 95 secs
lola: sara is running 100 secs || 1633647 markings, 9162765 edges, 10357 markings/sec, 100 secs
lola: sara is running 105 secs || 1683266 markings, 9459688 edges, 9924 markings/sec, 105 secs
lola: sara is running 110 secs || 1732712 markings, 9757704 edges, 9889 markings/sec, 110 secs
lola: sara is running 115 secs || 1783519 markings, 10063589 edges, 10161 markings/sec, 115 secs
lola: sara is running 120 secs || 1830619 markings, 10345989 edges, 9420 markings/sec, 120 secs
lola: sara is running 125 secs || 1878713 markings, 10634154 edges, 9619 markings/sec, 125 secs
lola: sara is running 130 secs || 1925126 markings, 10911632 edges, 9283 markings/sec, 130 secs
lola: sara is running 135 secs || 1971975 markings, 11193036 edges, 9370 markings/sec, 135 secs
lola: sara is running 140 secs || 2020952 markings, 11486647 edges, 9795 markings/sec, 140 secs
lola: sara is running 145 secs || 2069638 markings, 11776479 edges, 9737 markings/sec, 145 secs
lola: sara is running 150 secs || 2116544 markings, 12054894 edges, 9381 markings/sec, 150 secs
lola: sara is running 155 secs || 2168839 markings, 12291263 edges, 10459 markings/sec, 155 secs
lola: sara is running 160 secs || 2213220 markings, 12640757 edges, 8876 markings/sec, 160 secs
lola: sara is running 165 secs || 2263545 markings, 12944798 edges, 10065 markings/sec, 165 secs
lola: sara is running 170 secs || 2276401 markings, 13580486 edges, 2571 markings/sec, 170 secs
lola: sara is running 175 secs || 2324474 markings, 13942917 edges, 9615 markings/sec, 175 secs
lola: sara is running 180 secs || 2385380 markings, 14139603 edges, 12181 markings/sec, 180 secs
lola: sara is running 185 secs || 2444991 markings, 14305664 edges, 11922 markings/sec, 185 secs
lola: sara is running 190 secs || 2503341 markings, 14482848 edges, 11670 markings/sec, 190 secs
lola: sara is running 195 secs || 2554958 markings, 14723705 edges, 10323 markings/sec, 195 secs
lola: sara is running 200 secs || 2601664 markings, 15006667 edges, 9341 markings/sec, 200 secs
lola: sara is running 205 secs || 2649885 markings, 15295933 edges, 9644 markings/sec, 205 secs
lola: sara is running 210 secs || 2699343 markings, 15591955 edges, 9892 markings/sec, 210 secs
lola: sara is running 215 secs || 2748791 markings, 15888269 edges, 9890 markings/sec, 215 secs
lola: local time limit reached - aborting
lola: Child process aborted or communication problem between parent and child process
terminate called after throwing an instance of 'std::runtime_error'
what(): parse error at position 0: unexpected character, last read: '\ufffd'
Aborted (core dumped)
FORMULA Peterson-PT-5-ReachabilityCardinality-0 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-1 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-2 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-3 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-4 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-5 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-6 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-7 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-8 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-9 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-10 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-11 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-12 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-13 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-14 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-PT-5-ReachabilityCardinality-15 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
----- Kill lola and sara stdout -----
----- Kill lola and sara stderr -----
----- Finished stdout -----
----- Finished stderr -----
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="irma4mcc-full"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-5.tgz
mv Peterson-PT-5 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool irma4mcc-full"
echo " Input is Peterson-PT-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r114-csrt-152666472900579"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;