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Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r069-smll-152649742000187
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for DLCshifumi-PT-4a

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15752.780 41187.00 152066.00 408.20 TFFTFFTTFTTTFTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 107 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 345 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 1.9M May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DLCshifumi-PT-4a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r069-smll-152649742000187
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-00
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-01
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-02
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-03
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-04
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-05
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-06
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-07
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-08
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-09
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-10
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-11
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-12
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-13
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-14
FORMULA_NAME DLCshifumi-PT-4a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527321565815

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-00 with value :(((u607.p1093==0)||(u422.p908==1))&&(((u107.p593>=1)||(u31.p217>=3))||(!(u10.p69>=2))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-01 with value :(u64.p443>=2)
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-02 with value :(((u18.p124>=2)&&(((u679.p1165==0)||(u142.p628==1))&&((u4.p23==0)||(u538.p1024==1))))&&(u370.p856>=1))
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-03 with value :(((u341.p827==0)||(u285.p771==1))||(((u57.p396>=1)||((u66.p457==0)||(u436.p922==1)))&&((u36.p251>=3)&&((u53.p368==0)||(u47.p323==1)))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-04 with value :(!((u586.p1072==0)||(u652.p1138==1)))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-05 with value :(u51.p357>=2)
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-06 with value :((u165.p651==0)||(u437.p923==1))
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-07 with value :(!((!((u258.p744==0)||(u42.p293==1)))&&(!((u2.p11==0)||(u309.p795==1)))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-08 with value :(u646.p1132>=2)
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-09 with value :((!((u48.p335>=2)&&((u209.p695==0)||(u7.p48==1))))&&((u670.p1156==0)||(u690.p1176==1)))
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-10 with value :((((u15.p101>=3)||(u29.p197>=2))||((u30.p206==0)||(u652.p1138==1)))||(((u125.p611==0)||(u45.p310==1))||((u316.p802==0)||(u629.p1115==1))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-11 with value :(((u423.p909>=2)||(((u603.p1089==0)||(u37.p257==1))&&((u28.p196==0)||(u582.p1068==1))))&&(!((u341.p827==0)||(u33.p231==1))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-12 with value :((u678.p1164>=2)&&(u72.p503>=2))
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-13 with value :(((u46.p317==0)||(u345.p831==1))||(!((u25.p169==0)||(u75.p519==1))))
Read [reachable] property : DLCshifumi-PT-4a-ReachabilityCardinality-14 with value :(!((u592.p1078==0)||(u125.p611==1)))
Read [invariant] property : DLCshifumi-PT-4a-ReachabilityCardinality-15 with value :(!(u38.p266>=2))
built 1225 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 816
// Phase 1: matrix 816 rows 1178 cols
invariant :p833 + -1'p1177 = 0
invariant :p1028 + -1'p1177 = 0
invariant :p999 + -1'p1177 = 0
invariant :p379 + p380 + p381 + p382 + p383 + p384 + p385 + -1'p1177 = 0
invariant :p865 + -1'p1177 = 0
invariant :p1117 + -1'p1177 = 0
invariant :p585 + -1'p1177 = 0
invariant :p225 + p226 + p227 + p228 + p229 + p230 + p231 + -1'p1177 = 0
invariant :p715 + -1'p1177 = 0
invariant :p985 + -1'p1177 = 0
invariant :p218 + p219 + p220 + p221 + p222 + p223 + p224 + -1'p1177 = 0
invariant :p858 + -1'p1177 = 0
invariant :p253 + p254 + p255 + p256 + p257 + p258 + p259 + -1'p1177 = 0
invariant :p43 + p44 + p45 + p46 + p47 + p48 + p49 + -1'p1177 = 0
invariant :p862 + -1'p1177 = 0
invariant :p937 + -1'p1177 = 0
invariant :p758 + -1'p1177 = 0
invariant :p728 + -1'p1177 = 0
invariant :p967 + -1'p1177 = 0
invariant :p759 + -1'p1177 = 0
invariant :p1167 + -1'p1177 = 0
invariant :p78 + p79 + p80 + p81 + p82 + p83 + p84 + -1'p1177 = 0
invariant :p740 + -1'p1177 = 0
invariant :p586 + -1'p1177 = 0
invariant :p661 + -1'p1177 = 0
invariant :p1004 + -1'p1177 = 0
invariant :p760 + -1'p1177 = 0
invariant :p785 + -1'p1177 = 0
invariant :p592 + -1'p1177 = 0
invariant :p603 + -1'p1177 = 0
invariant :p956 + -1'p1177 = 0
invariant :p778 + -1'p1177 = 0
invariant :p1109 + -1'p1177 = 0
invariant :p344 + p345 + p346 + p347 + p348 + p349 + p350 + -1'p1177 = 0
invariant :p965 + -1'p1177 = 0
invariant :p1003 + -1'p1177 = 0
invariant :p1145 + -1'p1177 = 0
invariant :p570 + -1'p1177 = 0
invariant :p806 + -1'p1177 = 0
invariant :p913 + -1'p1177 = 0
invariant :p749 + -1'p1177 = 0
invariant :p767 + -1'p1177 = 0
invariant :p1093 + -1'p1177 = 0
invariant :p246 + p247 + p248 + p249 + p250 + p251 + p252 + -1'p1177 = 0
invariant :p1071 + -1'p1177 = 0
invariant :p652 + -1'p1177 = 0
invariant :p1053 + -1'p1177 = 0
invariant :p647 + -1'p1177 = 0
invariant :p1035 + -1'p1177 = 0
invariant :p1166 + -1'p1177 = 0
invariant :p1104 + -1'p1177 = 0
invariant :p1065 + -1'p1177 = 0
invariant :p621 + -1'p1177 = 0
invariant :p169 + p170 + p171 + p172 + p173 + p174 + p175 + -1'p1177 = 0
invariant :p988 + -1'p1177 = 0
invariant :p855 + -1'p1177 = 0
invariant :p978 + -1'p1177 = 0
invariant :p992 + -1'p1177 = 0
invariant :p598 + -1'p1177 = 0
invariant :p1060 + -1'p1177 = 0
invariant :p669 + -1'p1177 = 0
invariant :p739 + -1'p1177 = 0
invariant :p790 + -1'p1177 = 0
invariant :p904 + -1'p1177 = 0
invariant :p852 + -1'p1177 = 0
invariant :p643 + -1'p1177 = 0
invariant :p1137 + -1'p1177 = 0
invariant :p814 + -1'p1177 = 0
invariant :p910 + -1'p1177 = 0
invariant :p957 + -1'p1177 = 0
invariant :p1118 + -1'p1177 = 0
invariant :p800 + -1'p1177 = 0
invariant :p1026 + -1'p1177 = 0
invariant :p837 + -1'p1177 = 0
invariant :p113 + p114 + p115 + p116 + p117 + p118 + p119 + -1'p1177 = 0
invariant :p626 + -1'p1177 = 0
invariant :p629 + -1'p1177 = 0
invariant :p792 + -1'p1177 = 0
invariant :p1101 + -1'p1177 = 0
invariant :p723 + -1'p1177 = 0
invariant :p659 + -1'p1177 = 0
invariant :p685 + -1'p1177 = 0
invariant :p748 + -1'p1177 = 0
invariant :p880 + -1'p1177 = 0
invariant :p1103 + -1'p1177 = 0
invariant :p1068 + -1'p1177 = 0
invariant :p667 + -1'p1177 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p1177 = 0
invariant :p651 + -1'p1177 = 0
invariant :p690 + -1'p1177 = 0
invariant :p787 + -1'p1177 = 0
invariant :p869 + -1'p1177 = 0
invariant :p720 + -1'p1177 = 0
invariant :p618 + -1'p1177 = 0
invariant :p1020 + -1'p1177 = 0
invariant :p595 + -1'p1177 = 0
invariant :p642 + -1'p1177 = 0
invariant :p693 + -1'p1177 = 0
invariant :p1025 + -1'p1177 = 0
invariant :p302 + p303 + p304 + p305 + p306 + p307 + p308 + -1'p1177 = 0
invariant :p610 + -1'p1177 = 0
invariant :p1161 + -1'p1177 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + -1'p1177 = 0
invariant :p596 + -1'p1177 = 0
invariant :p732 + -1'p1177 = 0
invariant :p840 + -1'p1177 = 0
invariant :p568 + -1'p1177 = 0
invariant :p600 + -1'p1177 = 0
invariant :p692 + -1'p1177 = 0
invariant :p1158 + -1'p1177 = 0
invariant :p902 + -1'p1177 = 0
invariant :p141 + p142 + p143 + p144 + p145 + p146 + p147 + -1'p1177 = 0
invariant :p889 + -1'p1177 = 0
invariant :p933 + -1'p1177 = 0
invariant :p969 + -1'p1177 = 0
invariant :p863 + -1'p1177 = 0
invariant :p742 + -1'p1177 = 0
invariant :p997 + -1'p1177 = 0
invariant :p664 + -1'p1177 = 0
invariant :p922 + -1'p1177 = 0
invariant :p699 + -1'p1177 = 0
invariant :p1097 + -1'p1177 = 0
invariant :p805 + -1'p1177 = 0
invariant :p1072 + -1'p1177 = 0
invariant :p908 + -1'p1177 = 0
invariant :p484 + p485 + p486 + p487 + p488 + p489 + p490 + -1'p1177 = 0
invariant :p851 + -1'p1177 = 0
invariant :p120 + p121 + p122 + p123 + p124 + p125 + p126 + -1'p1177 = 0
invariant :p386 + p387 + p388 + p389 + p390 + p391 + p392 + -1'p1177 = 0
invariant :p781 + -1'p1177 = 0
invariant :p1073 + -1'p1177 = 0
invariant :p1114 + -1'p1177 = 0
invariant :p1033 + -1'p1177 = 0
invariant :p632 + -1'p1177 = 0
invariant :p1151 + -1'p1177 = 0
invariant :p640 + -1'p1177 = 0
invariant :p775 + -1'p1177 = 0
invariant :p673 + -1'p1177 = 0
invariant :p1160 + -1'p1177 = 0
invariant :p750 + -1'p1177 = 0
invariant :p546 + p547 + p548 + p549 + p550 + p551 + p552 + p553 + p554 + p555 + -1'p1177 = 0
invariant :p512 + p513 + p514 + p515 + p516 + p517 + p518 + -1'p1177 = 0
invariant :p709 + -1'p1177 = 0
invariant :p619 + -1'p1177 = 0
invariant :p986 + -1'p1177 = 0
invariant :p1094 + -1'p1177 = 0
invariant :p1085 + -1'p1177 = 0
invariant :p1061 + -1'p1177 = 0
invariant :p966 + -1'p1177 = 0
invariant :p566 + -1'p1177 = 0
invariant :p1013 + -1'p1177 = 0
invariant :p948 + -1'p1177 = 0
invariant :p1172 + -1'p1177 = 0
invariant :p929 + -1'p1177 = 0
invariant :p1112 + -1'p1177 = 0
invariant :p872 + -1'p1177 = 0
invariant :p1074 + -1'p1177 = 0
invariant :p899 + -1'p1177 = 0
invariant :p960 + -1'p1177 = 0
invariant :p1030 + -1'p1177 = 0
invariant :p996 + -1'p1177 = 0
invariant :p1045 + -1'p1177 = 0
invariant :p1050 + -1'p1177 = 0
invariant :p766 + -1'p1177 = 0
invariant :p810 + -1'p1177 = 0
invariant :p958 + -1'p1177 = 0
invariant :p696 + -1'p1177 = 0
invariant :p653 + -1'p1177 = 0
invariant :p755 + -1'p1177 = 0
invariant :p801 + -1'p1177 = 0
invariant :p1142 + -1'p1177 = 0
invariant :p634 + -1'p1177 = 0
invariant :p627 + -1'p1177 = 0
invariant :p571 + -1'p1177 = 0
invariant :p918 + -1'p1177 = 0
invariant :p127 + p128 + p129 + p130 + p131 + p132 + p133 + -1'p1177 = 0
invariant :p1119 + -1'p1177 = 0
invariant :p1039 + -1'p1177 = 0
invariant :p337 + p338 + p339 + p340 + p341 + p342 + p343 + -1'p1177 = 0
invariant :p943 + -1'p1177 = 0
invariant :p1047 + -1'p1177 = 0
invariant :p1165 + -1'p1177 = 0
invariant :p1089 + -1'p1177 = 0
invariant :p1048 + -1'p1177 = 0
invariant :p1105 + -1'p1177 = 0
invariant :p897 + -1'p1177 = 0
invariant :p463 + p464 + p465 + p466 + p467 + p468 + p469 + -1'p1177 = 0
invariant :p197 + p198 + p199 + p200 + p201 + p202 + p203 + -1'p1177 = 0
invariant :p738 + -1'p1177 = 0
invariant :p1130 + -1'p1177 = 0
invariant :p678 + -1'p1177 = 0
invariant :p1133 + -1'p1177 = 0
invariant :p687 + -1'p1177 = 0
invariant :p1075 + -1'p1177 = 0
invariant :p973 + -1'p1177 = 0
invariant :p944 + -1'p1177 = 0
invariant :p1009 + -1'p1177 = 0
invariant :p970 + -1'p1177 = 0
invariant :p569 + -1'p1177 = 0
invariant :p1098 + -1'p1177 = 0
invariant :p1052 + -1'p1177 = 0
invariant :p1081 + -1'p1177 = 0
invariant :p591 + -1'p1177 = 0
invariant :p915 + -1'p1177 = 0
invariant :p1175 + -1'p1177 = 0
invariant :p1049 + -1'p1177 = 0
invariant :p768 + -1'p1177 = 0
invariant :p577 + -1'p1177 = 0
invariant :p971 + -1'p1177 = 0
invariant :p930 + -1'p1177 = 0
invariant :p764 + -1'p1177 = 0
invariant :p1076 + -1'p1177 = 0
invariant :p572 + -1'p1177 = 0
invariant :p1046 + -1'p1177 = 0
invariant :p1014 + -1'p1177 = 0
invariant :p50 + p51 + p52 + p53 + p54 + p55 + p56 + -1'p1177 = 0
invariant :p587 + -1'p1177 = 0
invariant :p684 + -1'p1177 = 0
invariant :p625 + -1'p1177 = 0
invariant :p932 + -1'p1177 = 0
invariant :p1002 + -1'p1177 = 0
invariant :p935 + -1'p1177 = 0
invariant :p211 + p212 + p213 + p214 + p215 + p216 + p217 + -1'p1177 = 0
invariant :p734 + -1'p1177 = 0
invariant :p789 + -1'p1177 = 0
invariant :p655 + -1'p1177 = 0
invariant :p1000 + -1'p1177 = 0
invariant :p839 + -1'p1177 = 0
invariant :p695 + -1'p1177 = 0
invariant :p926 + -1'p1177 = 0
invariant :p624 + -1'p1177 = 0
invariant :p770 + -1'p1177 = 0
invariant :p964 + -1'p1177 = 0
invariant :p815 + -1'p1177 = 0
invariant :p874 + -1'p1177 = 0
invariant :p763 + -1'p1177 = 0
invariant :p962 + -1'p1177 = 0
invariant :p708 + -1'p1177 = 0
invariant :p925 + -1'p1177 = 0
invariant :p940 + -1'p1177 = 0
invariant :p1067 + -1'p1177 = 0
invariant :p1084 + -1'p1177 = 0
invariant :p1147 + -1'p1177 = 0
invariant :p689 + -1'p1177 = 0
invariant :p838 + -1'p1177 = 0
invariant :p1080 + -1'p1177 = 0
invariant :p757 + -1'p1177 = 0
invariant :p449 + p450 + p451 + p452 + p453 + p454 + p455 + -1'p1177 = 0
invariant :p916 + -1'p1177 = 0
invariant :p593 + -1'p1177 = 0
invariant :p974 + -1'p1177 = 0
invariant :p727 + -1'p1177 = 0
invariant :p650 + -1'p1177 = 0
invariant :p694 + -1'p1177 = 0
invariant :p1164 + -1'p1177 = 0
invariant :p1031 + -1'p1177 = 0
invariant :p609 + -1'p1177 = 0
invariant :p883 + -1'p1177 = 0
invariant :p811 + -1'p1177 = 0
invariant :p803 + -1'p1177 = 0
invariant :p1168 + -1'p1177 = 0
invariant :p745 + -1'p1177 = 0
invariant :p719 + -1'p1177 = 0
invariant :p796 + -1'p1177 = 0
invariant :p1016 + -1'p1177 = 0
invariant :p597 + -1'p1177 = 0
invariant :p1155 + -1'p1177 = 0
invariant :p579 + -1'p1177 = 0
invariant :p900 + -1'p1177 = 0
invariant :p665 + -1'p1177 = 0
invariant :p936 + -1'p1177 = 0
invariant :p556 + p557 + p558 + p559 + p560 + p561 + p562 + p563 + p564 + p565 + -1'p1177 = 0
invariant :p1170 + -1'p1177 = 0
invariant :p928 + -1'p1177 = 0
invariant :p945 + -1'p1177 = 0
invariant :p981 + -1'p1177 = 0
invariant :p835 + -1'p1177 = 0
invariant :p817 + -1'p1177 = 0
invariant :p631 + -1'p1177 = 0
invariant :p878 + -1'p1177 = 0
invariant :p1116 + -1'p1177 = 0
invariant :p638 + -1'p1177 = 0
invariant :p645 + -1'p1177 = 0
invariant :p765 + -1'p1177 = 0
invariant :p979 + -1'p1177 = 0
invariant :p1131 + -1'p1177 = 0
invariant :p601 + -1'p1177 = 0
invariant :p602 + -1'p1177 = 0
invariant :p881 + -1'p1177 = 0
invariant :p1012 + -1'p1177 = 0
invariant :p608 + -1'p1177 = 0
invariant :p975 + -1'p1177 = 0
invariant :p753 + -1'p1177 = 0
invariant :p831 + -1'p1177 = 0
invariant :p1152 + -1'p1177 = 0
invariant :p799 + -1'p1177 = 0
invariant :p752 + -1'p1177 = 0
invariant :p914 + -1'p1177 = 0
invariant :p295 + p296 + p297 + p298 + p299 + p300 + p301 + -1'p1177 = 0
invariant :p1122 + -1'p1177 = 0
invariant :p267 + p268 + p269 + p270 + p271 + p272 + p273 + -1'p1177 = 0
invariant :p606 + -1'p1177 = 0
invariant :p912 + -1'p1177 = 0
invariant :p1135 + -1'p1177 = 0
invariant :p1023 + -1'p1177 = 0
invariant :p190 + p191 + p192 + p193 + p194 + p195 + p196 + -1'p1177 = 0
invariant :p1136 + -1'p1177 = 0
invariant :p1077 + -1'p1177 = 0
invariant :p847 + -1'p1177 = 0
invariant :p682 + -1'p1177 = 0
invariant :p660 + -1'p1177 = 0
invariant :p821 + -1'p1177 = 0
invariant :p844 + -1'p1177 = 0
invariant :p1163 + -1'p1177 = 0
invariant :p783 + -1'p1177 = 0
invariant :p891 + -1'p1177 = 0
invariant :p1019 + -1'p1177 = 0
invariant :p649 + -1'p1177 = 0
invariant :p1174 + -1'p1177 = 0
invariant :p676 + -1'p1177 = 0
invariant :p989 + -1'p1177 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p1177 = 0
invariant :p697 + -1'p1177 = 0
invariant :p886 + -1'p1177 = 0
invariant :p1010 + -1'p1177 = 0
invariant :p968 + -1'p1177 = 0
invariant :p421 + p422 + p423 + p424 + p425 + p426 + p427 + -1'p1177 = 0
invariant :p1148 + -1'p1177 = 0
invariant :p1134 + -1'p1177 = 0
invariant :p607 + -1'p1177 = 0
invariant :p919 + -1'p1177 = 0
invariant :p911 + -1'p1177 = 0
invariant :p604 + -1'p1177 = 0
invariant :p756 + -1'p1177 = 0
invariant :p774 + -1'p1177 = 0
invariant :p977 + -1'p1177 = 0
invariant :p1027 + -1'p1177 = 0
invariant :p0 + p1177 = 1
invariant :p57 + p58 + p59 + p60 + p61 + p62 + p63 + -1'p1177 = 0
invariant :p309 + p310 + p311 + p312 + p313 + p314 + p315 + -1'p1177 = 0
invariant :p882 + -1'p1177 = 0
invariant :p711 + -1'p1177 = 0
invariant :p901 + -1'p1177 = 0
invariant :p1022 + -1'p1177 = 0
invariant :p736 + -1'p1177 = 0
invariant :p718 + -1'p1177 = 0
invariant :p980 + -1'p1177 = 0
invariant :p1006 + -1'p1177 = 0
invariant :p721 + -1'p1177 = 0
invariant :p845 + -1'p1177 = 0
invariant :p1120 + -1'p1177 = 0
invariant :p1029 + -1'p1177 = 0
invariant :p807 + -1'p1177 = 0
invariant :p581 + -1'p1177 = 0
invariant :p828 + -1'p1177 = 0
invariant :p176 + p177 + p178 + p179 + p180 + p181 + p182 + -1'p1177 = 0
invariant :p816 + -1'p1177 = 0
invariant :p868 + -1'p1177 = 0
invariant :p737 + -1'p1177 = 0
invariant :p442 + p443 + p444 + p445 + p446 + p447 + p448 + -1'p1177 = 0
invariant :p589 + -1'p1177 = 0
invariant :p849 + -1'p1177 = 0
invariant :p991 + -1'p1177 = 0
invariant :p1001 + -1'p1177 = 0
invariant :p896 + -1'p1177 = 0
invariant :p825 + -1'p1177 = 0
invariant :p931 + -1'p1177 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p1177 = 0
invariant :p1064 + -1'p1177 = 0
invariant :p1113 + -1'p1177 = 0
invariant :p644 + -1'p1177 = 0
invariant :p1021 + -1'p1177 = 0
invariant :p232 + p233 + p234 + p235 + p236 + p237 + p238 + -1'p1177 = 0
invariant :p1138 + -1'p1177 = 0
invariant :p907 + -1'p1177 = 0
invariant :p1017 + -1'p1177 = 0
invariant :p984 + -1'p1177 = 0
invariant :p639 + -1'p1177 = 0
invariant :p1087 + -1'p1177 = 0
invariant :p148 + p149 + p150 + p151 + p152 + p153 + p154 + -1'p1177 = 0
invariant :p477 + p478 + p479 + p480 + p481 + p482 + p483 + -1'p1177 = 0
invariant :p875 + -1'p1177 = 0
invariant :p1043 + -1'p1177 = 0
invariant :p683 + -1'p1177 = 0
invariant :p895 + -1'p1177 = 0
invariant :p729 + -1'p1177 = 0
invariant :p698 + -1'p1177 = 0
invariant :p578 + -1'p1177 = 0
invariant :p1036 + -1'p1177 = 0
invariant :p923 + -1'p1177 = 0
invariant :p987 + -1'p1177 = 0
invariant :p1129 + -1'p1177 = 0
invariant :p654 + -1'p1177 = 0
invariant :p1057 + -1'p1177 = 0
invariant :p1069 + -1'p1177 = 0
invariant :p735 + -1'p1177 = 0
invariant :p635 + -1'p1177 = 0
invariant :p1106 + -1'p1177 = 0
invariant :p656 + -1'p1177 = 0
invariant :p876 + -1'p1177 = 0
invariant :p614 + -1'p1177 = 0
invariant :p830 + -1'p1177 = 0
invariant :p771 + -1'p1177 = 0
invariant :p963 + -1'p1177 = 0
invariant :p710 + -1'p1177 = 0
invariant :p628 + -1'p1177 = 0
invariant :p1095 + -1'p1177 = 0
invariant :p611 + -1'p1177 = 0
invariant :p724 + -1'p1177 = 0
invariant :p1169 + -1'p1177 = 0
invariant :p859 + -1'p1177 = 0
invariant :p777 + -1'p1177 = 0
invariant :p1011 + -1'p1177 = 0
invariant :p1127 + -1'p1177 = 0
invariant :p866 + -1'p1177 = 0
invariant :p1051 + -1'p1177 = 0
invariant :p786 + -1'p1177 = 0
invariant :p613 + -1'p1177 = 0
invariant :p746 + -1'p1177 = 0
invariant :p372 + p373 + p374 + p375 + p376 + p377 + p378 + -1'p1177 = 0
invariant :p590 + -1'p1177 = 0
invariant :p976 + -1'p1177 = 0
invariant :p1099 + -1'p1177 = 0
invariant :p641 + -1'p1177 = 0
invariant :p1038 + -1'p1177 = 0
invariant :p134 + p135 + p136 + p137 + p138 + p139 + p140 + -1'p1177 = 0
invariant :p1055 + -1'p1177 = 0
invariant :p1088 + -1'p1177 = 0
invariant :p1079 + -1'p1177 = 0
invariant :p990 + -1'p1177 = 0
invariant :p183 + p184 + p185 + p186 + p187 + p188 + p189 + -1'p1177 = 0
invariant :p567 + -1'p1177 = 0
invariant :p351 + p352 + p353 + p354 + p355 + p356 + p357 + -1'p1177 = 0
invariant :p573 + -1'p1177 = 0
invariant :p599 + -1'p1177 = 0
invariant :p871 + -1'p1177 = 0
invariant :p829 + -1'p1177 = 0
invariant :p836 + -1'p1177 = 0
invariant :p1143 + -1'p1177 = 0
invariant :p1157 + -1'p1177 = 0
invariant :p917 + -1'p1177 = 0
invariant :p1015 + -1'p1177 = 0
invariant :p860 + -1'p1177 = 0
invariant :p725 + -1'p1177 = 0
invariant :p1154 + -1'p1177 = 0
invariant :p428 + p429 + p430 + p431 + p432 + p433 + p434 + -1'p1177 = 0
invariant :p842 + -1'p1177 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p1177 = 0
invariant :p575 + -1'p1177 = 0
invariant :p155 + p156 + p157 + p158 + p159 + p160 + p161 + -1'p1177 = 0
invariant :p576 + -1'p1177 = 0
invariant :p898 + -1'p1177 = 0
invariant :p873 + -1'p1177 = 0
invariant :p773 + -1'p1177 = 0
invariant :p1149 + -1'p1177 = 0
invariant :p605 + -1'p1177 = 0
invariant :p435 + p436 + p437 + p438 + p439 + p440 + p441 + -1'p1177 = 0
invariant :p1140 + -1'p1177 = 0
invariant :p1037 + -1'p1177 = 0
invariant :p798 + -1'p1177 = 0
invariant :p646 + -1'p1177 = 0
invariant :p636 + -1'p1177 = 0
invariant :p1100 + -1'p1177 = 0
invariant :p867 + -1'p1177 = 0
invariant :p726 + -1'p1177 = 0
invariant :p946 + -1'p1177 = 0
invariant :p784 + -1'p1177 = 0
invariant :p706 + -1'p1177 = 0
invariant :p780 + -1'p1177 = 0
invariant :p64 + p65 + p66 + p67 + p68 + p69 + p70 + -1'p1177 = 0
invariant :p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p1177 = 0
invariant :p791 + -1'p1177 = 0
invariant :p588 + -1'p1177 = 0
invariant :p762 + -1'p1177 = 0
invariant :p1007 + -1'p1177 = 0
invariant :p1121 + -1'p1177 = 0
invariant :p713 + -1'p1177 = 0
invariant :p1032 + -1'p1177 = 0
invariant :p952 + -1'p1177 = 0
invariant :p820 + -1'p1177 = 0
invariant :p456 + p457 + p458 + p459 + p460 + p461 + p462 + -1'p1177 = 0
invariant :p704 + -1'p1177 = 0
invariant :p942 + -1'p1177 = 0
invariant :p666 + -1'p1177 = 0
invariant :p358 + p359 + p360 + p361 + p362 + p363 + p364 + -1'p1177 = 0
invariant :p330 + p331 + p332 + p333 + p334 + p335 + p336 + -1'p1177 = 0
invariant :p885 + -1'p1177 = 0
invariant :p470 + p471 + p472 + p473 + p474 + p475 + p476 + -1'p1177 = 0
invariant :p323 + p324 + p325 + p326 + p327 + p328 + p329 + -1'p1177 = 0
invariant :p1005 + -1'p1177 = 0
invariant :p850 + -1'p1177 = 0
invariant :p1058 + -1'p1177 = 0
invariant :p526 + p527 + p528 + p529 + p530 + p531 + p532 + p533 + p534 + p535 + -1'p1177 = 0
invariant :p793 + -1'p1177 = 0
invariant :p85 + p86 + p87 + p88 + p89 + p90 + p91 + -1'p1177 = 0
invariant :p691 + -1'p1177 = 0
invariant :p623 + -1'p1177 = 0
invariant :p717 + -1'p1177 = 0
invariant :p681 + -1'p1177 = 0
invariant :p864 + -1'p1177 = 0
invariant :p674 + -1'p1177 = 0
invariant :p861 + -1'p1177 = 0
invariant :p1159 + -1'p1177 = 0
invariant :p1176 + -1'p1177 = 0
invariant :p1107 + -1'p1177 = 0
invariant :p892 + -1'p1177 = 0
invariant :p1132 + -1'p1177 = 0
invariant :p1070 + -1'p1177 = 0
invariant :p827 + -1'p1177 = 0
invariant :p846 + -1'p1177 = 0
invariant :p769 + -1'p1177 = 0
invariant :p731 + -1'p1177 = 0
invariant :p744 + -1'p1177 = 0
invariant :p1086 + -1'p1177 = 0
invariant :p1111 + -1'p1177 = 0
invariant :p1056 + -1'p1177 = 0
invariant :p1083 + -1'p1177 = 0
invariant :p288 + p289 + p290 + p291 + p292 + p293 + p294 + -1'p1177 = 0
invariant :p617 + -1'p1177 = 0
invariant :p671 + -1'p1177 = 0
invariant :p99 + p100 + p101 + p102 + p103 + p104 + p105 + -1'p1177 = 0
invariant :p1123 + -1'p1177 = 0
invariant :p938 + -1'p1177 = 0
invariant :p162 + p163 + p164 + p165 + p166 + p167 + p168 + -1'p1177 = 0
invariant :p730 + -1'p1177 = 0
invariant :p887 + -1'p1177 = 0
invariant :p1156 + -1'p1177 = 0
invariant :p804 + -1'p1177 = 0
invariant :p941 + -1'p1177 = 0
invariant :p274 + p275 + p276 + p277 + p278 + p279 + p280 + -1'p1177 = 0
invariant :p536 + p537 + p538 + p539 + p540 + p541 + p542 + p543 + p544 + p545 + -1'p1177 = 0
invariant :p400 + p401 + p402 + p403 + p404 + p405 + p406 + -1'p1177 = 0
invariant :p890 + -1'p1177 = 0
invariant :p809 + -1'p1177 = 0
invariant :p819 + -1'p1177 = 0
invariant :p1110 + -1'p1177 = 0
invariant :p662 + -1'p1177 = 0
invariant :p1125 + -1'p1177 = 0
invariant :p893 + -1'p1177 = 0
invariant :p1128 + -1'p1177 = 0
invariant :p950 + -1'p1177 = 0
invariant :p983 + -1'p1177 = 0
invariant :p939 + -1'p1177 = 0
invariant :p888 + -1'p1177 = 0
invariant :p754 + -1'p1177 = 0
invariant :p407 + p408 + p409 + p410 + p411 + p412 + p413 + -1'p1177 = 0
invariant :p633 + -1'p1177 = 0
invariant :p1034 + -1'p1177 = 0
invariant :p686 + -1'p1177 = 0
invariant :p615 + -1'p1177 = 0
invariant :p1078 + -1'p1177 = 0
invariant :p1066 + -1'p1177 = 0
invariant :p281 + p282 + p283 + p284 + p285 + p286 + p287 + -1'p1177 = 0
invariant :p982 + -1'p1177 = 0
invariant :p905 + -1'p1177 = 0
invariant :p788 + -1'p1177 = 0
invariant :p204 + p205 + p206 + p207 + p208 + p209 + p210 + -1'p1177 = 0
invariant :p612 + -1'p1177 = 0
invariant :p239 + p240 + p241 + p242 + p243 + p244 + p245 + -1'p1177 = 0
invariant :p658 + -1'p1177 = 0
invariant :p951 + -1'p1177 = 0
invariant :p393 + p394 + p395 + p396 + p397 + p398 + p399 + -1'p1177 = 0
invariant :p260 + p261 + p262 + p263 + p264 + p265 + p266 + -1'p1177 = 0
invariant :p707 + -1'p1177 = 0
invariant :p1059 + -1'p1177 = 0
invariant :p675 + -1'p1177 = 0
invariant :p1173 + -1'p1177 = 0
invariant :p1090 + -1'p1177 = 0
invariant :p701 + -1'p1177 = 0
invariant :p71 + p72 + p73 + p74 + p75 + p76 + p77 + -1'p1177 = 0
invariant :p733 + -1'p1177 = 0
invariant :p36 + p37 + p38 + p39 + p40 + p41 + p42 + -1'p1177 = 0
invariant :p776 + -1'p1177 = 0
invariant :p848 + -1'p1177 = 0
invariant :p812 + -1'p1177 = 0
invariant :p843 + -1'p1177 = 0
invariant :p826 + -1'p1177 = 0
invariant :p927 + -1'p1177 = 0
invariant :p1141 + -1'p1177 = 0
invariant :p879 + -1'p1177 = 0
invariant :p920 + -1'p1177 = 0
invariant :p491 + p492 + p493 + p494 + p495 + p496 + p497 + -1'p1177 = 0
invariant :p741 + -1'p1177 = 0
invariant :p1153 + -1'p1177 = 0
invariant :p1042 + -1'p1177 = 0
invariant :p751 + -1'p1177 = 0
invariant :p857 + -1'p1177 = 0
invariant :p1063 + -1'p1177 = 0
invariant :p702 + -1'p1177 = 0
invariant :p668 + -1'p1177 = 0
invariant :p808 + -1'p1177 = 0
invariant :p703 + -1'p1177 = 0
invariant :p1108 + -1'p1177 = 0
invariant :p688 + -1'p1177 = 0
invariant :p622 + -1'p1177 = 0
invariant :p1040 + -1'p1177 = 0
invariant :p906 + -1'p1177 = 0
invariant :p594 + -1'p1177 = 0
invariant :p1102 + -1'p1177 = 0
invariant :p1162 + -1'p1177 = 0
invariant :p959 + -1'p1177 = 0
invariant :p822 + -1'p1177 = 0
invariant :p580 + -1'p1177 = 0
invariant :p670 + -1'p1177 = 0
invariant :p1054 + -1'p1177 = 0
invariant :p824 + -1'p1177 = 0
invariant :p772 + -1'p1177 = 0
invariant :p823 + -1'p1177 = 0
invariant :p1092 + -1'p1177 = 0
invariant :p1144 + -1'p1177 = 0
invariant :p414 + p415 + p416 + p417 + p418 + p419 + p420 + -1'p1177 = 0
invariant :p106 + p107 + p108 + p109 + p110 + p111 + p112 + -1'p1177 = 0
invariant :p794 + -1'p1177 = 0
invariant :p949 + -1'p1177 = 0
invariant :p716 + -1'p1177 = 0
invariant :p802 + -1'p1177 = 0
invariant :p1041 + -1'p1177 = 0
invariant :p620 + -1'p1177 = 0
invariant :p782 + -1'p1177 = 0
invariant :p870 + -1'p1177 = 0
invariant :p972 + -1'p1177 = 0
invariant :p677 + -1'p1177 = 0
invariant :p637 + -1'p1177 = 0
invariant :p779 + -1'p1177 = 0
invariant :p714 + -1'p1177 = 0
invariant :p909 + -1'p1177 = 0
invariant :p743 + -1'p1177 = 0
invariant :p1096 + -1'p1177 = 0
invariant :p813 + -1'p1177 = 0
invariant :p365 + p366 + p367 + p368 + p369 + p370 + p371 + -1'p1177 = 0
invariant :p584 + -1'p1177 = 0
invariant :p995 + -1'p1177 = 0
invariant :p616 + -1'p1177 = 0
invariant :p795 + -1'p1177 = 0
invariant :p993 + -1'p1177 = 0
invariant :p854 + -1'p1177 = 0
invariant :p519 + p520 + p521 + p522 + p523 + p524 + p525 + -1'p1177 = 0
invariant :p583 + -1'p1177 = 0
invariant :p1091 + -1'p1177 = 0
invariant :p663 + -1'p1177 = 0
invariant :p1115 + -1'p1177 = 0
invariant :p924 + -1'p1177 = 0
invariant :p761 + -1'p1177 = 0
invariant :p832 + -1'p1177 = 0
invariant :p818 + -1'p1177 = 0
invariant :p797 + -1'p1177 = 0
invariant :p1024 + -1'p1177 = 0
invariant :p834 + -1'p1177 = 0
invariant :p884 + -1'p1177 = 0
invariant :p700 + -1'p1177 = 0
invariant :p672 + -1'p1177 = 0
invariant :p961 + -1'p1177 = 0
invariant :p1146 + -1'p1177 = 0
invariant :p856 + -1'p1177 = 0
invariant :p921 + -1'p1177 = 0
invariant :p630 + -1'p1177 = 0
invariant :p657 + -1'p1177 = 0
invariant :p894 + -1'p1177 = 0
invariant :p955 + -1'p1177 = 0
invariant :p680 + -1'p1177 = 0
invariant :p747 + -1'p1177 = 0
invariant :p1124 + -1'p1177 = 0
invariant :p1126 + -1'p1177 = 0
invariant :p574 + -1'p1177 = 0
invariant :p934 + -1'p1177 = 0
invariant :p1150 + -1'p1177 = 0
invariant :p498 + p499 + p500 + p501 + p502 + p503 + p504 + -1'p1177 = 0
invariant :p648 + -1'p1177 = 0
invariant :p722 + -1'p1177 = 0
invariant :p1171 + -1'p1177 = 0
invariant :p679 + -1'p1177 = 0
invariant :p1082 + -1'p1177 = 0
invariant :p316 + p317 + p318 + p319 + p320 + p321 + p322 + -1'p1177 = 0
invariant :p505 + p506 + p507 + p508 + p509 + p510 + p511 + -1'p1177 = 0
invariant :p903 + -1'p1177 = 0
invariant :p947 + -1'p1177 = 0
invariant :p953 + -1'p1177 = 0
invariant :p1008 + -1'p1177 = 0
invariant :p841 + -1'p1177 = 0
invariant :p712 + -1'p1177 = 0
invariant :p582 + -1'p1177 = 0
invariant :p994 + -1'p1177 = 0
invariant :p1139 + -1'p1177 = 0
invariant :p954 + -1'p1177 = 0
invariant :p877 + -1'p1177 = 0
invariant :p1062 + -1'p1177 = 0
invariant :p998 + -1'p1177 = 0
invariant :p705 + -1'p1177 = 0
invariant :p1018 + -1'p1177 = 0
invariant :p1044 + -1'p1177 = 0
invariant :p853 + -1'p1177 = 0
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-00 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-01 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi\_PT\_4a\_flat\_flat\_flat\_flat\_mod,2.41187e+67,26.3146,146320,1390,21,77401,2809,7835,75449,68,2508,0
Total reachable state count : 2.411865032257058774852760846768617816824e+67

Verifying 16 reachability properties.
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-00 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-00,0,26.3265,146352,1,0,77401,2809,7852,75449,78,2508,1556
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-01 does not hold.
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-01

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-01,0,26.3274,146448,1,0,77401,2809,7854,75449,79,2508,1556
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-02 does not hold.
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-02,0,26.3385,146448,1,0,77401,2809,7871,75449,82,2508,3699
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-03 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-03,0,26.3466,146448,1,0,77401,2809,7891,75449,86,2508,4840
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-04 does not hold.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-04,0,26.3473,146448,1,0,77401,2809,7895,75449,86,2508,4984
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-05 does not hold.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-05,0,26.3481,146448,1,0,77401,2809,7897,75449,87,2508,4984
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-06 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-06,0,26.3504,146448,1,0,77401,2809,7901,75449,87,2508,5666
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-07 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-07,0,26.355,146448,1,0,77401,2809,7913,75449,88,2508,6126
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-08 does not hold.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-08,0,26.3554,146448,1,0,77401,2809,7915,75449,89,2508,6126
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-09 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-09,0,26.3591,146448,1,0,77401,2809,7928,75449,89,2508,7010
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-10 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-10,0,26.3711,146448,1,0,77401,2809,7952,75449,94,2508,8260
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-11 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-11,2.9533e+66,26.3807,146448,699,25,77401,2809,7970,75449,100,2508,10457
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-12 does not hold.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-12,0,26.3811,146448,1,0,77401,2809,7974,75449,100,2508,10457
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-13 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-13,0,26.3864,146448,1,0,77401,2809,7983,75449,100,2508,11313
Reachability property DLCshifumi-PT-4a-ReachabilityCardinality-14 does not hold.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCshifumi-PT-4a-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-14,0,26.389,146448,1,0,77401,2809,7987,75449,100,2508,12409
Invariant property DLCshifumi-PT-4a-ReachabilityCardinality-15 is true.
FORMULA DLCshifumi-PT-4a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCshifumi-PT-4a-ReachabilityCardinality-15,0,26.39,146448,1,0,77401,2809,7990,75449,101,2508,12409
ITS tools runner thread asked to quit. Dying gracefully.
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527321607002

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 26, 2018 7:59:27 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 26, 2018 7:59:27 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 26, 2018 7:59:28 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 442 ms
May 26, 2018 7:59:28 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1178 places.
May 26, 2018 7:59:28 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 7504 transitions.
May 26, 2018 7:59:28 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 26, 2018 7:59:30 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1630 ms
May 26, 2018 7:59:30 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 26, 2018 7:59:31 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 7504 transitions.
May 26, 2018 7:59:31 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (7504) to apply POR reductions. Disabling POR matrices.
May 26, 2018 7:59:31 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1165 ms
May 26, 2018 7:59:31 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1181 ms
May 26, 2018 7:59:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 7504 transitions.
May 26, 2018 7:59:32 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1631ms conformant to PINS in folder :/home/mcc/execution
May 26, 2018 7:59:33 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1173 ms
May 26, 2018 7:59:33 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 26, 2018 7:59:34 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 736 ms
May 26, 2018 7:59:34 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 4450 ms.
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-00(UNSAT) depth K=0 took 60 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-01(UNSAT) depth K=0 took 11 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-02(UNSAT) depth K=0 took 11 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-03(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-04(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-05(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-06(UNSAT) depth K=0 took 16 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-07(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-08(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-09(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-10(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-11(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-12(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-13(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-14(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-15(UNSAT) depth K=0 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-00(UNSAT) depth K=1 took 47 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-01(UNSAT) depth K=1 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-02(UNSAT) depth K=1 took 16 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-03(UNSAT) depth K=1 took 14 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-04(UNSAT) depth K=1 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-05(UNSAT) depth K=1 took 20 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-06(UNSAT) depth K=1 took 11 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-07(UNSAT) depth K=1 took 28 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-08(UNSAT) depth K=1 took 15 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-09(UNSAT) depth K=1 took 57 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 7504 transitions.
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-10(UNSAT) depth K=1 took 56 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-11(UNSAT) depth K=1 took 17 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-12(UNSAT) depth K=1 took 17 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-13(UNSAT) depth K=1 took 20 ms
May 26, 2018 7:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-14(UNSAT) depth K=1 took 14 ms
May 26, 2018 7:59:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-15(UNSAT) depth K=1 took 20 ms
May 26, 2018 7:59:37 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 11802 redundant transitions.
May 26, 2018 7:59:37 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 182 ms
May 26, 2018 7:59:37 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 0 ms
May 26, 2018 7:59:40 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 691 place invariants in 743 ms
May 26, 2018 7:59:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-00(UNSAT) depth K=2 took 7924 ms
May 26, 2018 7:59:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-01(UNSAT) depth K=2 took 676 ms
May 26, 2018 7:59:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-02(UNSAT) depth K=2 took 401 ms
May 26, 2018 7:59:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-03(UNSAT) depth K=2 took 380 ms
May 26, 2018 7:59:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-04(UNSAT) depth K=2 took 376 ms
May 26, 2018 7:59:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-05(UNSAT) depth K=2 took 408 ms
May 26, 2018 7:59:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-06(UNSAT) depth K=2 took 359 ms
May 26, 2018 7:59:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-07(UNSAT) depth K=2 took 347 ms
May 26, 2018 7:59:48 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-08(UNSAT) depth K=2 took 363 ms
May 26, 2018 7:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-09(UNSAT) depth K=2 took 818 ms
May 26, 2018 7:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-10(UNSAT) depth K=2 took 415 ms
May 26, 2018 7:59:50 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-11(UNSAT) depth K=2 took 749 ms
May 26, 2018 7:59:50 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-12(UNSAT) depth K=2 took 383 ms
May 26, 2018 7:59:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-13(UNSAT) depth K=2 took 420 ms
May 26, 2018 7:59:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-14(UNSAT) depth K=2 took 431 ms
May 26, 2018 7:59:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCshifumi-PT-4a-ReachabilityCardinality-15(UNSAT) depth K=2 took 498 ms
May 26, 2018 7:59:56 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 1178 variables to be positive in 16812 ms
May 26, 2018 7:59:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant DLCshifumi-PT-4a-ReachabilityCardinality-00
May 26, 2018 7:59:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for DLCshifumi-PT-4a-ReachabilityCardinality-00
May 26, 2018 7:59:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property DLCshifumi-PT-4a-ReachabilityCardinality-00(TRUE) depth K=0 took 2872 ms
May 26, 2018 8:00:01 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate DLCshifumi-PT-4a-ReachabilityCardinality-01
May 26, 2018 8:00:01 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for DLCshifumi-PT-4a-ReachabilityCardinality-01
May 26, 2018 8:00:01 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property DLCshifumi-PT-4a-ReachabilityCardinality-01(FALSE) depth K=0 took 2356 ms
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate DLCshifumi-PT-4a-ReachabilityCardinality-02
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for DLCshifumi-PT-4a-ReachabilityCardinality-02
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property DLCshifumi-PT-4a-ReachabilityCardinality-02(FALSE) depth K=0 took 4094 ms
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying DLCshifumi-PT-4a-ReachabilityCardinality-03 K-induction depth 0
Exception in thread "Thread-6" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying DLCshifumi-PT-4a-ReachabilityCardinality-00 SMT depth 3
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 3
May 26, 2018 8:00:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 3
May 26, 2018 8:00:05 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 3/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-4a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-4a.tgz
mv DLCshifumi-PT-4a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DLCshifumi-PT-4a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r069-smll-152649742000187"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;