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Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r069-smll-152649741800075
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for DLCround-PT-08a

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15751.790 8053.00 22220.00 396.00 TFTFFFTTTFFTFFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 644K
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.7K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.4K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 479K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DLCround-PT-08a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r069-smll-152649741800075
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-08a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527256350290

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-00 with value :((((u44.p149==0)||(u6.p48==1))||(!(u7.p52>=3)))||(!(u84.p189>=1)))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-01 with value :(!((u2.p11==0)||(u156.p261==1)))
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-02 with value :(!(((u95.p200>=3)&&((u8.p61==0)||(u31.p136==1)))&&((u96.p201==0)||(u104.p209==1))))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-03 with value :((u11.p95>=2)||(u5.p29>=2))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-04 with value :(u36.p141>=3)
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-05 with value :(((((u7.p57==0)||(u99.p204==1))&&((u8.p65==0)||(u134.p239==1)))||(!(u125.p230>=3)))&&(u4.p24>=3))
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-06 with value :(((u15.p120==0)||(u27.p132==1))||((u128.p233==0)||(u44.p149==1)))
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-07 with value :(!(((u11.p95>=3)||((u11.p92==0)||(u11.p95==1)))&&(!((u13.p118==0)||(u122.p227==1)))))
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-08 with value :(((u4.p27==0)||(u44.p149==1))&&((u121.p226==0)||(u108.p213==1)))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-09 with value :(((u43.p148==0)||(u10.p82==1))&&(((u60.p165==0)||(u6.p46==1))&&(u9.p72>=2)))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-10 with value :(((u12.p102>=2)||((u142.p247>=2)||(u1.p6>=2)))||(!((u11.p98==0)||(u113.p218==1))))
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-11 with value :((u2.p12==0)||(u147.p252==1))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-12 with value :(u111.p216>=3)
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-13 with value :(((!((u10.p82==0)||(u92.p197==1)))&&((u79.p184>=2)&&((u155.p260==0)||(u30.p135==1))))&&(((u118.p223>=3)||(u106.p211>=1))||(!((u146.p251==0)||(u7.p55==1)))))
Read [reachable] property : DLCround-PT-08a-ReachabilityCardinality-14 with value :(u6.p44>=3)
Read [invariant] property : DLCround-PT-08a-ReachabilityCardinality-15 with value :(!(((u144.p249>=2)&&((u9.p69==0)||(u9.p69==1)))&&(((u119.p224==0)||(u64.p169==1))||((u2.p10==0)||(u11.p95==1)))))
built 289 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 186
// Phase 1: matrix 186 rows 263 cols
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_08a\_flat\_flat\_flat\_flat\_mod,2.401e+12,1.07874,13232,322,21,4700,797,2039,4197,68,891,0
Total reachable state count : 2401000000001

Verifying 16 reachability properties.
Invariant property DLCround-PT-08a-ReachabilityCardinality-00 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-00,0,1.08084,13264,1,0,4700,797,2053,4197,77,891,116
Reachability property DLCround-PT-08a-ReachabilityCardinality-01 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-01

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-01,0,1.08204,13360,1,0,4700,797,2059,4197,80,891,438
Invariant property DLCround-PT-08a-ReachabilityCardinality-02 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-02,0,1.08306,13360,1,0,4700,797,2072,4197,81,891,462
Reachability property DLCround-PT-08a-ReachabilityCardinality-03 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-03

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-03,0,1.08383,13360,1,0,4700,797,2077,4197,83,891,462
Reachability property DLCround-PT-08a-ReachabilityCardinality-04 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-04,0,1.08418,13360,1,0,4700,797,2078,4197,83,891,462
Reachability property DLCround-PT-08a-ReachabilityCardinality-05 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-05,0,1.08649,13360,1,0,4700,797,2095,4197,88,891,796
Invariant property DLCround-PT-08a-ReachabilityCardinality-06 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-06,0,1.08772,13360,1,0,4700,797,2104,4197,88,891,1056
Invariant property DLCround-PT-08a-ReachabilityCardinality-07 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-07,0,1.08848,13360,1,0,4700,797,2121,4197,94,891,1086
Invariant property DLCround-PT-08a-ReachabilityCardinality-08 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-08,0,1.08976,13360,1,0,4700,797,2129,4197,94,891,1362
Reachability property DLCround-PT-08a-ReachabilityCardinality-09 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-09,0,1.09086,13360,1,0,4700,797,2142,4197,96,891,1462
Reachability property DLCround-PT-08a-ReachabilityCardinality-10 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-10,0,1.09257,13360,1,0,4700,797,2154,4197,97,891,1512
Invariant property DLCround-PT-08a-ReachabilityCardinality-11 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-11,0,1.09408,13360,1,0,4700,797,2158,4197,97,891,1812
Reachability property DLCround-PT-08a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-12,0,1.09431,13360,1,0,4700,797,2159,4197,97,891,1812
Reachability property DLCround-PT-08a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-13,0,1.09664,13360,1,0,4700,797,2182,4197,98,891,2349
Reachability property DLCround-PT-08a-ReachabilityCardinality-14 does not hold.
FORMULA DLCround-PT-08a-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-08a-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-14,0,1.09697,13360,1,0,4700,797,2184,4197,99,891,2349
Invariant property DLCround-PT-08a-ReachabilityCardinality-15 is true.
FORMULA DLCround-PT-08a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-08a-ReachabilityCardinality-15,0,1.09777,13360,1,0,4700,797,2203,4197,103,891,2349
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
invariant :p173 + -1'p262 = 0
invariant :p234 + -1'p262 = 0
invariant :p136 + -1'p262 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p262 = 0
invariant :p237 + -1'p262 = 0
invariant :p187 + -1'p262 = 0
invariant :p135 + -1'p262 = 0
invariant :p225 + -1'p262 = 0
invariant :p240 + -1'p262 = 0
invariant :p140 + -1'p262 = 0
invariant :p188 + -1'p262 = 0
invariant :p184 + -1'p262 = 0
invariant :p167 + -1'p262 = 0
invariant :p203 + -1'p262 = 0
invariant :p201 + -1'p262 = 0
invariant :p122 + -1'p262 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p262 = 0
invariant :p206 + -1'p262 = 0
invariant :p181 + -1'p262 = 0
invariant :p258 + -1'p262 = 0
invariant :p154 + -1'p262 = 0
invariant :p158 + -1'p262 = 0
invariant :p255 + -1'p262 = 0
invariant :p164 + -1'p262 = 0
invariant :p182 + -1'p262 = 0
invariant :p145 + -1'p262 = 0
invariant :p245 + -1'p262 = 0
invariant :p246 + -1'p262 = 0
invariant :p123 + -1'p262 = 0
invariant :p139 + -1'p262 = 0
invariant :p228 + -1'p262 = 0
invariant :p207 + -1'p262 = 0
invariant :p130 + -1'p262 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p262 = 0
invariant :p157 + -1'p262 = 0
invariant :p200 + -1'p262 = 0
invariant :p231 + -1'p262 = 0
invariant :p176 + -1'p262 = 0
invariant :p221 + -1'p262 = 0
invariant :p243 + -1'p262 = 0
invariant :p223 + -1'p262 = 0
invariant :p260 + -1'p262 = 0
invariant :p216 + -1'p262 = 0
invariant :p119 + -1'p262 = 0
invariant :p129 + -1'p262 = 0
invariant :p151 + -1'p262 = 0
invariant :p257 + -1'p262 = 0
invariant :p236 + -1'p262 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p262 = 0
invariant :p143 + -1'p262 = 0
invariant :p197 + -1'p262 = 0
invariant :p190 + -1'p262 = 0
invariant :p219 + -1'p262 = 0
invariant :p233 + -1'p262 = 0
invariant :p174 + -1'p262 = 0
invariant :p159 + -1'p262 = 0
invariant :p177 + -1'p262 = 0
invariant :p199 + -1'p262 = 0
invariant :p220 + -1'p262 = 0
invariant :p133 + -1'p262 = 0
invariant :p211 + -1'p262 = 0
invariant :p235 + -1'p262 = 0
invariant :p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + -1'p262 = 0
invariant :p146 + -1'p262 = 0
invariant :p170 + -1'p262 = 0
invariant :p256 + -1'p262 = 0
invariant :p261 + -1'p262 = 0
invariant :p248 + -1'p262 = 0
invariant :p153 + -1'p262 = 0
invariant :p242 + -1'p262 = 0
invariant :p230 + -1'p262 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p262 = 0
invariant :p217 + -1'p262 = 0
invariant :p155 + -1'p262 = 0
invariant :p194 + -1'p262 = 0
invariant :p205 + -1'p262 = 0
invariant :p212 + -1'p262 = 0
invariant :p171 + -1'p262 = 0
invariant :p141 + -1'p262 = 0
invariant :p224 + -1'p262 = 0
invariant :p161 + -1'p262 = 0
invariant :p134 + -1'p262 = 0
invariant :p198 + -1'p262 = 0
invariant :p148 + -1'p262 = 0
invariant :p180 + -1'p262 = 0
invariant :p210 + -1'p262 = 0
invariant :p147 + -1'p262 = 0
invariant :p124 + -1'p262 = 0
invariant :p204 + -1'p262 = 0
invariant :p202 + -1'p262 = 0
invariant :p247 + -1'p262 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p262 = 0
invariant :p192 + -1'p262 = 0
invariant :p244 + -1'p262 = 0
invariant :p259 + -1'p262 = 0
invariant :p179 + -1'p262 = 0
invariant :p109 + p110 + p111 + p112 + p113 + p114 + p115 + p116 + p117 + p118 + -1'p262 = 0
invariant :p137 + -1'p262 = 0
invariant :p208 + -1'p262 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p262 = 0
invariant :p183 + -1'p262 = 0
invariant :p195 + -1'p262 = 0
invariant :p142 + -1'p262 = 0
invariant :p149 + -1'p262 = 0
invariant :p162 + -1'p262 = 0
invariant :p213 + -1'p262 = 0
invariant :p214 + -1'p262 = 0
invariant :p168 + -1'p262 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p262 = 0
invariant :p132 + -1'p262 = 0
invariant :p196 + -1'p262 = 0
invariant :p99 + p100 + p101 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + -1'p262 = 0
invariant :p150 + -1'p262 = 0
invariant :p209 + -1'p262 = 0
invariant :p166 + -1'p262 = 0
invariant :p215 + -1'p262 = 0
invariant :p160 + -1'p262 = 0
invariant :p252 + -1'p262 = 0
invariant :p185 + -1'p262 = 0
invariant :p222 + -1'p262 = 0
invariant :p227 + -1'p262 = 0
invariant :p189 + -1'p262 = 0
invariant :p251 + -1'p262 = 0
invariant :p186 + -1'p262 = 0
invariant :p121 + -1'p262 = 0
invariant :p254 + -1'p262 = 0
invariant :p249 + -1'p262 = 0
invariant :p193 + -1'p262 = 0
invariant :p131 + -1'p262 = 0
invariant :p0 + p262 = 1
invariant :p120 + -1'p262 = 0
invariant :p125 + -1'p262 = 0
invariant :p128 + -1'p262 = 0
invariant :p138 + -1'p262 = 0
invariant :p163 + -1'p262 = 0
invariant :p178 + -1'p262 = 0
invariant :p156 + -1'p262 = 0
invariant :p253 + -1'p262 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p262 = 0
invariant :p172 + -1'p262 = 0
invariant :p239 + -1'p262 = 0
invariant :p169 + -1'p262 = 0
invariant :p89 + p90 + p91 + p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p262 = 0
invariant :p126 + -1'p262 = 0
invariant :p127 + -1'p262 = 0
invariant :p165 + -1'p262 = 0
invariant :p144 + -1'p262 = 0
invariant :p250 + -1'p262 = 0
invariant :p229 + -1'p262 = 0
invariant :p175 + -1'p262 = 0
invariant :p238 + -1'p262 = 0
invariant :p191 + -1'p262 = 0
invariant :p232 + -1'p262 = 0
invariant :p226 + -1'p262 = 0
invariant :p241 + -1'p262 = 0
invariant :p152 + -1'p262 = 0
invariant :p218 + -1'p262 = 0

BK_STOP 1527256358343

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 1:52:32 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 1:52:32 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 1:52:32 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 216 ms
May 25, 2018 1:52:32 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 263 places.
May 25, 2018 1:52:32 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1907 transitions.
May 25, 2018 1:52:32 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 25, 2018 1:52:33 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 58 ms
May 25, 2018 1:52:33 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 476 ms
May 25, 2018 1:52:33 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 25, 2018 1:52:34 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1907 transitions.
May 25, 2018 1:52:34 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1907) to apply POR reductions. Disabling POR matrices.
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 421 ms
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 449 ms
May 25, 2018 1:52:34 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1907 transitions.
May 25, 2018 1:52:34 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 567ms conformant to PINS in folder :/home/mcc/execution
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 314 ms
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 373 ms
May 25, 2018 1:52:34 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 25, 2018 1:52:35 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 3108 redundant transitions.
May 25, 2018 1:52:35 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 15 ms
May 25, 2018 1:52:35 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1753 ms.
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-00(UNSAT) depth K=0 took 35 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-01(UNSAT) depth K=0 took 1 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-02(UNSAT) depth K=0 took 11 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-03(UNSAT) depth K=0 took 13 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-04(UNSAT) depth K=0 took 11 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-05(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-06(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-07(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-08(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-09(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-10(UNSAT) depth K=0 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-11(UNSAT) depth K=0 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-12(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-13(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-14(UNSAT) depth K=0 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-15(UNSAT) depth K=0 took 14 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1907 transitions.
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-00(UNSAT) depth K=1 took 12 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-01(UNSAT) depth K=1 took 20 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-02(UNSAT) depth K=1 took 19 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-03(UNSAT) depth K=1 took 16 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-04(UNSAT) depth K=1 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-05(UNSAT) depth K=1 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-06(UNSAT) depth K=1 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-07(UNSAT) depth K=1 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-08(UNSAT) depth K=1 took 12 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-09(UNSAT) depth K=1 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-10(UNSAT) depth K=1 took 12 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-11(UNSAT) depth K=1 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-12(UNSAT) depth K=1 took 19 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-13(UNSAT) depth K=1 took 7 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-14(UNSAT) depth K=1 took 19 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-15(UNSAT) depth K=1 took 15 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-00(UNSAT) depth K=2 took 427 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-01(UNSAT) depth K=2 took 9 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-02(UNSAT) depth K=2 took 9 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-03(UNSAT) depth K=2 took 20 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-04(UNSAT) depth K=2 took 9 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-05(UNSAT) depth K=2 took 9 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-06(UNSAT) depth K=2 took 10 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-07(UNSAT) depth K=2 took 9 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-08(UNSAT) depth K=2 took 17 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-09(UNSAT) depth K=2 took 10 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-10(UNSAT) depth K=2 took 53 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-11(UNSAT) depth K=2 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-12(UNSAT) depth K=2 took 10 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-13(UNSAT) depth K=2 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-14(UNSAT) depth K=2 took 11 ms
May 25, 2018 1:52:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-08a-ReachabilityCardinality-15(UNSAT) depth K=2 took 10 ms
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 157 place invariants in 138 ms
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying DLCround-PT-08a-ReachabilityCardinality-00 SMT depth 3
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 3
May 25, 2018 1:52:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 3
Exception in thread "Thread-8" java.lang.RuntimeException: SMT solver raised an error :(error "Error writing to Z3 solver: java.io.IOException: Stream closed")
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.computeAndDeclareInvariants(KInductionSolver.java:293)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:71)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 1:52:37 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DLCround-PT-08a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r069-smll-152649741800075"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;