About the Execution of ITS-Tools.L for CircularTrains-PT-096
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15775.160 | 7108.00 | 20075.00 | 336.40 | TFTTFFFFTFFTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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/home/mcc/execution
total 248K
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
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-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLCardinality.txt
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-rw-r--r-- 1 mcc users 4.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
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-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
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=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is CircularTrains-PT-096, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r045-smll-152646361500026
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-00
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-01
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-02
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-03
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-04
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-05
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-06
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-07
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-08
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-09
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-10
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-11
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-12
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-13
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-14
FORMULA_NAME CircularTrains-PT-096-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1527198161192
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
its-reach command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : CircularTrains-PT-096-ReachabilityCardinality-00 with value :(!(F81>=3))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-01 with value :(F93>=2)
Read [invariant] property : CircularTrains-PT-096-ReachabilityCardinality-02 with value :(!(((Section_44>=2)&&(F50<=Section_38))&&((F23<=F93)&&(Section_36>=1))))
Read [invariant] property : CircularTrains-PT-096-ReachabilityCardinality-03 with value :(((!(Section_27>=2))||((F3<=Section_60)&&(F52>=2)))||((!(F2<=F95))||(Section_56>=2)))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-04 with value :((((F41<=Section_24)&&(Section_58>=2))&&((Section_34>=3)||(F18>=2)))&&(Section_89>=2))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-05 with value :(((Section_4<=Section_8)&&((Section_66>=2)&&(F29>=3)))&&(((F34<=Section_32)||(F92<=Section_32))||((Section_78<=F54)||(Section_75>=1))))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-06 with value :(((!(F39>=1))&&((F47<=Section_86)&&(F77>=1)))&&((Section_58>=1)&&(Section_19>=3)))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-07 with value :(((!(Section_64>=2))&&(F31>=2))&&(((F47>=3)||(F73>=1))&&(!(Section_32<=Section_55))))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-08 with value :(((!(F84<=F93))&&(!(Section_34<=Section_84)))&&((F29>=3)||(!(F43<=Section_48))))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-09 with value :(F87>=2)
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-10 with value :((((F51>=3)||(F81>=2))&&((Section_65>=1)||(F84>=2)))||(Section_72>=2))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-11 with value :(((!(F75<=Section_87))||((Section_41<=Section_60)||(F54<=F72)))&&(((Section_77<=F26)&&(F73<=F81))&&((F67>=2)||(Section_59>=1))))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-12 with value :(!((!(F10>=3))||((F91<=Section_87)||(Section_54<=F79))))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-13 with value :((F82>=3)&&(F3<=F31))
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-14 with value :(F37>=3)
Read [reachable] property : CircularTrains-PT-096-ReachabilityCardinality-15 with value :(Section_89>=2)
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 96 rows 192 cols
invariant :Section_51 + -1'Section_49 + -1'F49 + F50 = 1
invariant :Section_18 + Section_17 + F17 = 2
invariant :F2 + -1'F1 + Section_3 + -1'Section_1 = 1
invariant :Section_54 + Section_53 + F53 = 2
invariant :Section_67 + F66 + -1'F65 + -1'Section_65 = -1
invariant :F59 + Section_60 + Section_59 = 2
invariant :Section_85 + F84 + Section_84 = 1
invariant :Section_81 + F80 + Section_80 = 2
invariant :F58 + Section_58 + Section_59 = 1
invariant :Section_28 + -1'Section_26 + F27 + -1'F26 = -1
invariant :Section_94 + F93 + -1'Section_92 + -1'F92 = -1
invariant :Section_89 + F88 + Section_88 = 1
invariant :F74 + -1'Section_76 + -1'F75 + Section_74 = 1
invariant :F46 + Section_47 + Section_46 = 1
invariant :F42 + -1'F43 + F40 + Section_40 + -1'Section_44 + -1'F41 = -1
invariant :F16 + -1'Section_15 + Section_17 + -1'F15 = 0
invariant :F37 + F39 + Section_40 + -1'F36 + Section_35 + -1'F38 + F35 = 1
invariant :Section_73 + Section_72 + F72 = 1
invariant :Section_82 + F81 + -1'F80 + -1'Section_80 = -1
invariant :F62 + Section_63 + Section_62 = 2
invariant :Section_14 + F13 + Section_13 = 1
invariant :Section_21 + Section_20 + F20 = 2
invariant :F33 + -1'F34 + Section_33 + -1'Section_35 = 0
invariant :Section_71 + Section_72 + F71 = 2
invariant :F23 + Section_24 + -1'F22 + -1'Section_22 = 1
invariant :F44 + Section_45 + Section_44 = 2
invariant :F89 + Section_90 + -1'F88 + -1'Section_88 = 1
invariant :F85 + -1'F84 + -1'Section_84 + Section_86 = 0
invariant :Section_37 + F36 + -1'Section_35 + -1'F35 = -1
invariant :F82 + -1'F81 + F80 + Section_83 + Section_80 = 2
invariant :Section_25 + Section_24 + F24 = 1
invariant :F14 + Section_15 + -1'F13 + -1'Section_13 = 1
invariant :F87 + Section_87 + Section_88 = 1
invariant :Section_69 + F68 + Section_68 = 2
invariant :F60 + Section_60 + Section_61 = 1
invariant :Section_4 + Section_5 + F4 = 1
invariant :F83 + Section_84 + Section_83 = 2
invariant :Section_95 + Section_60 + -1'F96 + -1'F43 + -1'F34 + Section_33 + Section_87 + -1'F91 + Section_90 + Section_79 + -1'F29 + -1'F1 + Section_45 + -1'F15 + -1'F68 + -1'F77 + -1'F54 + Section_3 + Section_26 + Section_10 + -1'F84 + -1'F47 + -1'F63 + -1'F8 + -1'F31 + -1'F75 + Section_49 + -1'F24 + -1'Section_72 + -1'F72 + -1'F27 + -1'F88 + -1'Section_5 + Section_70 + -1'F13 + Section_19 + -1'F66 + Section_40 + -1'F36 + Section_61 + -1'F93 + Section_74 + Section_58 + -1'F22 + -1'F81 + Section_7 + Section_83 + Section_53 + -1'F5 + Section_59 + -1'F11 + -1'F71 + -1'F4 + -1'Section_1 + -1'F41 + -1'F56 + Section_86 + Section_52 + Section_62 + -1'F20 + -1'F17 + Section_65 + -1'F38 + -1'F50 + Section_46 + Section_80 = -18
invariant :F32 + Section_33 + -1'F31 + -1'Section_31 = 1
invariant :F90 + -1'F91 + Section_90 + -1'Section_92 = 0
invariant :Section_91 + F91 + Section_92 = 1
invariant :F51 + Section_49 + F49 + Section_52 + -1'F50 = 0
invariant :F6 + -1'Section_5 + Section_7 + -1'F5 = -1
invariant :F28 + Section_26 + -1'F27 + F26 + Section_29 = 2
invariant :F94 + -1'Section_60 + F96 + F43 + F34 + -1'Section_33 + -1'Section_87 + F91 + -1'Section_90 + -1'Section_79 + F29 + F1 + -1'Section_45 + F15 + F68 + F77 + F54 + -1'Section_3 + -1'Section_26 + -1'Section_10 + F84 + F47 + F63 + F8 + F31 + F75 + -1'Section_49 + F24 + Section_72 + F72 + F27 + F88 + Section_5 + -1'Section_70 + F13 + -1'Section_19 + F66 + -1'Section_40 + F36 + -1'Section_61 + -1'Section_74 + -1'Section_58 + F22 + F81 + -1'Section_7 + -1'Section_83 + -1'Section_53 + F5 + -1'Section_59 + F11 + F71 + F4 + Section_92 + Section_1 + F41 + F56 + -1'Section_86 + -1'Section_52 + -1'Section_62 + F20 + F17 + -1'Section_65 + F92 + F38 + F50 + -1'Section_46 + -1'Section_80 = 20
invariant :Section_75 + Section_76 + F75 = 1
invariant :F19 + Section_19 + Section_20 = 1
invariant :F45 + Section_45 + Section_46 = 1
invariant :F25 + -1'Section_24 + Section_26 + -1'F24 = 0
invariant :Section_41 + F40 + Section_40 = 1
invariant :F73 + -1'Section_72 + -1'F72 + Section_74 = 0
invariant :F21 + -1'Section_20 + Section_22 + -1'F20 = -1
invariant :Section_55 + F54 + -1'Section_53 + -1'F53 = -1
invariant :F48 + -1'F47 + Section_49 + -1'Section_47 = -1
invariant :Section_36 + Section_35 + F35 = 2
invariant :Section_66 + F65 + Section_65 = 2
invariant :Section_2 + F1 + Section_1 = 1
invariant :Section_96 + F96 + Section_1 = 1
invariant :F18 + -1'Section_17 + Section_19 + -1'F17 = -1
invariant :F79 + Section_79 + Section_80 = 1
invariant :F76 + Section_76 + Section_77 = 1
invariant :Section_16 + Section_15 + F15 = 1
invariant :F30 + -1'F29 + Section_31 + -1'Section_29 = -1
invariant :Section_27 + Section_26 + F26 = 2
invariant :F70 + -1'Section_72 + Section_70 + -1'F71 = -1
invariant :F78 + Section_79 + -1'F77 + -1'Section_77 = -1
invariant :F7 + Section_8 + Section_7 = 1
invariant :F9 + Section_10 + -1'F8 + -1'Section_8 = -1
invariant :F57 + -1'Section_56 + Section_58 + -1'F56 = -1
invariant :Section_43 + F43 + Section_44 = 1
invariant :F67 + -1'F66 + F65 + Section_68 + Section_65 = 2
invariant :F86 + Section_87 + Section_86 = 2
invariant :Section_12 + -1'Section_10 + -1'F10 + F11 = 1
invariant :F95 + -1'Section_60 + F43 + F34 + -1'Section_33 + -1'Section_87 + F91 + -1'Section_90 + -1'Section_79 + F29 + F1 + -1'Section_45 + F15 + F68 + F77 + F54 + -1'Section_3 + -1'Section_26 + -1'Section_10 + F84 + F47 + F63 + F8 + F31 + F75 + -1'Section_49 + F24 + Section_72 + F72 + F27 + F88 + Section_5 + -1'Section_70 + F13 + -1'Section_19 + F66 + -1'Section_40 + F36 + -1'Section_61 + F93 + -1'Section_74 + -1'Section_58 + F22 + F81 + -1'Section_7 + -1'Section_83 + -1'Section_53 + F5 + -1'Section_59 + F11 + F71 + F4 + F41 + F56 + -1'Section_86 + -1'Section_52 + -1'Section_62 + F20 + F17 + -1'Section_65 + F38 + F50 + -1'Section_46 + -1'Section_80 = 19
invariant :Section_34 + F34 + Section_35 = 1
invariant :Section_93 + Section_92 + F92 = 2
invariant :F52 + Section_53 + Section_52 = 1
invariant :Section_48 + F47 + Section_47 = 2
invariant :Section_32 + F31 + Section_31 = 1
invariant :Section_6 + Section_5 + F5 = 2
invariant :Section_57 + Section_56 + F56 = 2
invariant :Section_78 + F77 + Section_77 = 2
invariant :Section_38 + -1'F39 + -1'Section_40 + F38 = 1
invariant :F64 + -1'Section_63 + -1'F63 + Section_65 = 0
invariant :Section_42 + -1'F40 + -1'Section_40 + F41 = 1
invariant :F3 + Section_3 + -1'Section_5 + -1'F4 = 0
invariant :F12 + Section_10 + F10 + -1'F11 + Section_13 = 0
invariant :Section_11 + Section_10 + F10 = 1
invariant :Section_9 + F8 + Section_8 = 2
invariant :Section_64 + Section_63 + F63 = 1
invariant :Section_50 + Section_49 + F49 = 1
invariant :Section_23 + F22 + Section_22 = 1
invariant :Section_30 + F29 + Section_29 = 2
invariant :Section_39 + F39 + Section_40 = 1
invariant :F55 + Section_56 + -1'F54 + Section_53 + F53 = 2
invariant :F61 + Section_61 + Section_62 = 1
invariant :F69 + -1'F68 + Section_70 + -1'Section_68 = -1
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 96 rows 192 cols
invariant :Section_51 + -1'Section_49 + -1'F49 + F50 = 1
invariant :Section_18 + Section_17 + F17 = 2
invariant :F2 + -1'F1 + Section_3 + -1'Section_1 = 1
invariant :Section_54 + Section_53 + F53 = 2
invariant :Section_67 + F66 + -1'F65 + -1'Section_65 = -1
invariant :F59 + Section_60 + Section_59 = 2
invariant :Section_85 + F84 + Section_84 = 1
invariant :Section_81 + F80 + Section_80 = 2
invariant :F58 + Section_58 + Section_59 = 1
invariant :Section_28 + -1'Section_26 + F27 + -1'F26 = -1
invariant :Section_94 + F93 + -1'Section_92 + -1'F92 = -1
invariant :Section_89 + F88 + Section_88 = 1
invariant :F74 + -1'Section_76 + -1'F75 + Section_74 = 1
invariant :F46 + Section_47 + Section_46 = 1
invariant :F42 + -1'F43 + F40 + Section_40 + -1'Section_44 + -1'F41 = -1
invariant :F16 + -1'Section_15 + Section_17 + -1'F15 = 0
invariant :F37 + F39 + Section_40 + -1'F36 + Section_35 + -1'F38 + F35 = 1
invariant :Section_73 + Section_72 + F72 = 1
invariant :Section_82 + F81 + -1'F80 + -1'Section_80 = -1
invariant :F62 + Section_63 + Section_62 = 2
invariant :Section_14 + F13 + Section_13 = 1
invariant :Section_21 + Section_20 + F20 = 2
invariant :F33 + -1'F34 + Section_33 + -1'Section_35 = 0
invariant :Section_71 + Section_72 + F71 = 2
invariant :F23 + Section_24 + -1'F22 + -1'Section_22 = 1
invariant :F44 + Section_45 + Section_44 = 2
invariant :F89 + Section_90 + -1'F88 + -1'Section_88 = 1
invariant :F85 + -1'F84 + -1'Section_84 + Section_86 = 0
invariant :Section_37 + F36 + -1'Section_35 + -1'F35 = -1
invariant :F82 + -1'F81 + F80 + Section_83 + Section_80 = 2
invariant :Section_25 + Section_24 + F24 = 1
invariant :F14 + Section_15 + -1'F13 + -1'Section_13 = 1
invariant :F87 + Section_87 + Section_88 = 1
invariant :Section_69 + F68 + Section_68 = 2
invariant :F60 + Section_60 + Section_61 = 1
invariant :Section_4 + Section_5 + F4 = 1
invariant :F83 + Section_84 + Section_83 = 2
invariant :Section_95 + Section_60 + -1'F96 + -1'F43 + -1'F34 + Section_33 + Section_87 + -1'F91 + Section_90 + Section_79 + -1'F29 + -1'F1 + Section_45 + -1'F15 + -1'F68 + -1'F77 + -1'F54 + Section_3 + Section_26 + Section_10 + -1'F84 + -1'F47 + -1'F63 + -1'F8 + -1'F31 + -1'F75 + Section_49 + -1'F24 + -1'Section_72 + -1'F72 + -1'F27 + -1'F88 + -1'Section_5 + Section_70 + -1'F13 + Section_19 + -1'F66 + Section_40 + -1'F36 + Section_61 + -1'F93 + Section_74 + Section_58 + -1'F22 + -1'F81 + Section_7 + Section_83 + Section_53 + -1'F5 + Section_59 + -1'F11 + -1'F71 + -1'F4 + -1'Section_1 + -1'F41 + -1'F56 + Section_86 + Section_52 + Section_62 + -1'F20 + -1'F17 + Section_65 + -1'F38 + -1'F50 + Section_46 + Section_80 = -18
invariant :F32 + Section_33 + -1'F31 + -1'Section_31 = 1
invariant :F90 + -1'F91 + Section_90 + -1'Section_92 = 0
invariant :Section_91 + F91 + Section_92 = 1
invariant :F51 + Section_49 + F49 + Section_52 + -1'F50 = 0
invariant :F6 + -1'Section_5 + Section_7 + -1'F5 = -1
invariant :F28 + Section_26 + -1'F27 + F26 + Section_29 = 2
invariant :F94 + -1'Section_60 + F96 + F43 + F34 + -1'Section_33 + -1'Section_87 + F91 + -1'Section_90 + -1'Section_79 + F29 + F1 + -1'Section_45 + F15 + F68 + F77 + F54 + -1'Section_3 + -1'Section_26 + -1'Section_10 + F84 + F47 + F63 + F8 + F31 + F75 + -1'Section_49 + F24 + Section_72 + F72 + F27 + F88 + Section_5 + -1'Section_70 + F13 + -1'Section_19 + F66 + -1'Section_40 + F36 + -1'Section_61 + -1'Section_74 + -1'Section_58 + F22 + F81 + -1'Section_7 + -1'Section_83 + -1'Section_53 + F5 + -1'Section_59 + F11 + F71 + F4 + Section_92 + Section_1 + F41 + F56 + -1'Section_86 + -1'Section_52 + -1'Section_62 + F20 + F17 + -1'Section_65 + F92 + F38 + F50 + -1'Section_46 + -1'Section_80 = 20
invariant :Section_75 + Section_76 + F75 = 1
invariant :F19 + Section_19 + Section_20 = 1
invariant :F45 + Section_45 + Section_46 = 1
invariant :F25 + -1'Section_24 + Section_26 + -1'F24 = 0
invariant :Section_41 + F40 + Section_40 = 1
invariant :F73 + -1'Section_72 + -1'F72 + Section_74 = 0
invariant :F21 + -1'Section_20 + Section_22 + -1'F20 = -1
invariant :Section_55 + F54 + -1'Section_53 + -1'F53 = -1
invariant :F48 + -1'F47 + Section_49 + -1'Section_47 = -1
invariant :Section_36 + Section_35 + F35 = 2
invariant :Section_66 + F65 + Section_65 = 2
invariant :Section_2 + F1 + Section_1 = 1
invariant :Section_96 + F96 + Section_1 = 1
invariant :F18 + -1'Section_17 + Section_19 + -1'F17 = -1
invariant :F79 + Section_79 + Section_80 = 1
invariant :F76 + Section_76 + Section_77 = 1
invariant :Section_16 + Section_15 + F15 = 1
invariant :F30 + -1'F29 + Section_31 + -1'Section_29 = -1
invariant :Section_27 + Section_26 + F26 = 2
invariant :F70 + -1'Section_72 + Section_70 + -1'F71 = -1
invariant :F78 + Section_79 + -1'F77 + -1'Section_77 = -1
invariant :F7 + Section_8 + Section_7 = 1
invariant :F9 + Section_10 + -1'F8 + -1'Section_8 = -1
invariant :F57 + -1'Section_56 + Section_58 + -1'F56 = -1
invariant :Section_43 + F43 + Section_44 = 1
invariant :F67 + -1'F66 + F65 + Section_68 + Section_65 = 2
invariant :F86 + Section_87 + Section_86 = 2
invariant :Section_12 + -1'Section_10 + -1'F10 + F11 = 1
invariant :F95 + -1'Section_60 + F43 + F34 + -1'Section_33 + -1'Section_87 + F91 + -1'Section_90 + -1'Section_79 + F29 + F1 + -1'Section_45 + F15 + F68 + F77 + F54 + -1'Section_3 + -1'Section_26 + -1'Section_10 + F84 + F47 + F63 + F8 + F31 + F75 + -1'Section_49 + F24 + Section_72 + F72 + F27 + F88 + Section_5 + -1'Section_70 + F13 + -1'Section_19 + F66 + -1'Section_40 + F36 + -1'Section_61 + F93 + -1'Section_74 + -1'Section_58 + F22 + F81 + -1'Section_7 + -1'Section_83 + -1'Section_53 + F5 + -1'Section_59 + F11 + F71 + F4 + F41 + F56 + -1'Section_86 + -1'Section_52 + -1'Section_62 + F20 + F17 + -1'Section_65 + F38 + F50 + -1'Section_46 + -1'Section_80 = 19
invariant :Section_34 + F34 + Section_35 = 1
invariant :Section_93 + Section_92 + F92 = 2
invariant :F52 + Section_53 + Section_52 = 1
invariant :Section_48 + F47 + Section_47 = 2
invariant :Section_32 + F31 + Section_31 = 1
invariant :Section_6 + Section_5 + F5 = 2
invariant :Section_57 + Section_56 + F56 = 2
invariant :Section_78 + F77 + Section_77 = 2
invariant :Section_38 + -1'F39 + -1'Section_40 + F38 = 1
invariant :F64 + -1'Section_63 + -1'F63 + Section_65 = 0
invariant :Section_42 + -1'F40 + -1'Section_40 + F41 = 1
invariant :F3 + Section_3 + -1'Section_5 + -1'F4 = 0
invariant :F12 + Section_10 + F10 + -1'F11 + Section_13 = 0
invariant :Section_11 + Section_10 + F10 = 1
invariant :Section_9 + F8 + Section_8 = 2
invariant :Section_64 + Section_63 + F63 = 1
invariant :Section_50 + Section_49 + F49 = 1
invariant :Section_23 + F22 + Section_22 = 1
invariant :Section_30 + F29 + Section_29 = 2
invariant :Section_39 + F39 + Section_40 = 1
invariant :F55 + Section_56 + -1'F54 + Section_53 + F53 = 2
invariant :F61 + Section_61 + Section_62 = 1
invariant :F69 + -1'F68 + Section_70 + -1'Section_68 = -1
FORMULA CircularTrains-PT-096-ReachabilityCardinality-00 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA CircularTrains-PT-096-ReachabilityCardinality-01 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA CircularTrains-PT-096-ReachabilityCardinality-02 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA CircularTrains-PT-096-ReachabilityCardinality-03 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA CircularTrains-PT-096-ReachabilityCardinality-04 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA CircularTrains-PT-096-ReachabilityCardinality-05 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains\_PT\_096\_flat\_flat,2.5913e+21,2.39943,55044,2,12302,5,284938,6,0,867,298118,0
Total reachable state count : 2591300278296609652224
Verifying 16 reachability properties.
Invariant property CircularTrains-PT-096-ReachabilityCardinality-00 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-00,0,2.40106,55296,1,0,5,284938,7,0,869,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-01 does not hold.
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-01
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-01,0,2.40189,55408,1,0,5,284938,8,0,870,298118,0
Invariant property CircularTrains-PT-096-ReachabilityCardinality-02 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-02,0,2.41812,55408,1,0,5,284938,9,0,881,298118,0
Invariant property CircularTrains-PT-096-ReachabilityCardinality-03 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-03,0,2.42733,55408,1,0,5,284938,10,0,888,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-04 does not hold.
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-04
FORMULA CircularTrains-PT-096-ReachabilityCardinality-06 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-04,0,2.42906,55408,1,0,5,284938,11,0,901,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-05 does not hold.
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-05
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-05,0,2.45556,55408,1,0,5,284938,12,0,918,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-06 does not hold.
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-06
FORMULA CircularTrains-PT-096-ReachabilityCardinality-07 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-06,0,2.49266,55408,1,0,5,284938,13,0,928,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-07 does not hold.
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-07
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-07,0,2.50695,55408,1,0,5,284938,14,0,938,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-08 is true.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-08,9.7155e+18,2.54589,55408,2,9905,6,284938,15,0,957,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-09 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-09
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-09,0,2.54688,55408,1,0,6,284938,16,0,958,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-10 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-10
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-10,0,2.55386,55408,1,0,6,284938,17,0,967,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-11 is true.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-11,2.84815e+07,2.56307,55408,2,1469,7,284938,18,0,989,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-12 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-12,0,2.5777,55408,1,0,7,284938,19,0,996,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-13 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-13
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-13,0,2.5805,55408,1,0,7,284938,20,0,1002,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-14 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-14
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-14,0,2.60399,55408,1,0,7,284938,21,0,1003,298118,0
Reachability property CircularTrains-PT-096-ReachabilityCardinality-15 does not hold.
FORMULA CircularTrains-PT-096-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : CircularTrains-PT-096-ReachabilityCardinality-15
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
CircularTrains-PT-096-ReachabilityCardinality-15,0,2.60438,55408,1,0,7,284938,22,0,1003,298118,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527198168300
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 9:42:43 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 24, 2018 9:42:43 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 9:42:43 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 78 ms
May 24, 2018 9:42:43 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 192 places.
May 24, 2018 9:42:43 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 96 transitions.
May 24, 2018 9:42:43 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 17 ms
May 24, 2018 9:42:43 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 96 ms
May 24, 2018 9:42:43 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 46 ms
May 24, 2018 9:42:43 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 5 ms
May 24, 2018 9:42:43 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 71 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 96 transitions.
May 24, 2018 9:42:44 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 96 transitions.
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 97 place invariants in 88 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 610 ms.
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-00(UNSAT) depth K=0 took 10 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-01(UNSAT) depth K=0 took 20 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-02(UNSAT) depth K=0 took 11 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-03(UNSAT) depth K=0 took 11 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-04(UNSAT) depth K=0 took 11 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 96 transitions.
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-05(UNSAT) depth K=0 took 18 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-06(UNSAT) depth K=0 took 11 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-07(UNSAT) depth K=0 took 14 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-08(UNSAT) depth K=0 took 12 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-09(UNSAT) depth K=0 took 9 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-10(UNSAT) depth K=0 took 10 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-11(UNSAT) depth K=0 took 11 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-12(UNSAT) depth K=0 took 7 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-13(UNSAT) depth K=0 took 9 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-14(UNSAT) depth K=0 took 23 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-15(UNSAT) depth K=0 took 13 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-00(UNSAT) depth K=1 took 28 ms
May 24, 2018 9:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-01(UNSAT) depth K=1 took 11 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-02(UNSAT) depth K=1 took 23 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-03(UNSAT) depth K=1 took 29 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 97 place invariants in 128 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-04(UNSAT) depth K=1 took 37 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-05(UNSAT) depth K=1 took 13 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-06(UNSAT) depth K=1 took 12 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-07(UNSAT) depth K=1 took 12 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-08(UNSAT) depth K=1 took 10 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-09(UNSAT) depth K=1 took 9 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-10(UNSAT) depth K=1 took 17 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-11(UNSAT) depth K=1 took 15 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-12(UNSAT) depth K=1 took 16 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-13(UNSAT) depth K=1 took 12 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-14(UNSAT) depth K=1 took 17 ms
May 24, 2018 9:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-15(UNSAT) depth K=1 took 22 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-00(UNSAT) depth K=2 took 1032 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 192 variables to be positive in 2040 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 96 transitions.
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/96 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 8 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 96 transitions.
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 6 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 192 variables to be positive in 1718 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant CircularTrains-PT-096-ReachabilityCardinality-00
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-00
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-00(TRUE) depth K=0 took 70 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate CircularTrains-PT-096-ReachabilityCardinality-01
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-01
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-01(FALSE) depth K=0 took 60 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant CircularTrains-PT-096-ReachabilityCardinality-02
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-02
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-02(TRUE) depth K=0 took 83 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property CircularTrains-PT-096-ReachabilityCardinality-01(UNSAT) depth K=2 took 603 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant CircularTrains-PT-096-ReachabilityCardinality-03
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-03
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-03(TRUE) depth K=0 took 60 ms
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate CircularTrains-PT-096-ReachabilityCardinality-04
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-04
May 24, 2018 9:42:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-04(FALSE) depth K=0 took 56 ms
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate CircularTrains-PT-096-ReachabilityCardinality-05
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-05
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-05(FALSE) depth K=0 took 74 ms
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate CircularTrains-PT-096-ReachabilityCardinality-06
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-06
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-06(FALSE) depth K=0 took 62 ms
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate CircularTrains-PT-096-ReachabilityCardinality-07
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for CircularTrains-PT-096-ReachabilityCardinality-07
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property CircularTrains-PT-096-ReachabilityCardinality-07(FALSE) depth K=0 took 55 ms
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying CircularTrains-PT-096-ReachabilityCardinality-08 K-induction depth 0
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeAblingForPredicate(NecessaryEnablingsolver.java:766)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:502)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying CircularTrains-PT-096-ReachabilityCardinality-02 SMT depth 2
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 2
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 2
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 24, 2018 9:42:47 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 8/ 16 properties. Interrupting other analysis methods.
May 24, 2018 9:42:47 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 3161ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircularTrains-PT-096"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/CircularTrains-PT-096.tgz
mv CircularTrains-PT-096 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is CircularTrains-PT-096, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r045-smll-152646361500026"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;