fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r032-ebro-152646309900061
Last Updated
June 26, 2018

About the Execution of ITS-Tools for BART-PT-002

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15753.120 22202.00 80121.00 201.10 TTTFTFTTFFTTFFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 82K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 201K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 55K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 148K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 29K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 21K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 44K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 102 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 340 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 64K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 169K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 14K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 27K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 506K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BART-PT-002, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r032-ebro-152646309900061
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-002-ReachabilityCardinality-00
FORMULA_NAME BART-PT-002-ReachabilityCardinality-01
FORMULA_NAME BART-PT-002-ReachabilityCardinality-02
FORMULA_NAME BART-PT-002-ReachabilityCardinality-03
FORMULA_NAME BART-PT-002-ReachabilityCardinality-04
FORMULA_NAME BART-PT-002-ReachabilityCardinality-05
FORMULA_NAME BART-PT-002-ReachabilityCardinality-06
FORMULA_NAME BART-PT-002-ReachabilityCardinality-07
FORMULA_NAME BART-PT-002-ReachabilityCardinality-08
FORMULA_NAME BART-PT-002-ReachabilityCardinality-09
FORMULA_NAME BART-PT-002-ReachabilityCardinality-10
FORMULA_NAME BART-PT-002-ReachabilityCardinality-11
FORMULA_NAME BART-PT-002-ReachabilityCardinality-12
FORMULA_NAME BART-PT-002-ReachabilityCardinality-13
FORMULA_NAME BART-PT-002-ReachabilityCardinality-14
FORMULA_NAME BART-PT-002-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1526856945926

FORMULA BART-PT-002-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA BART-PT-002-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : BART-PT-002-ReachabilityCardinality-00 with value :((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((TrainState_1_0_0+TrainState_2_0_0)+TrainState_1_1_1)+TrainState_2_1_1)+TrainState_1_1_2)+TrainState_2_1_2)+TrainState_1_1_3)+TrainState_2_1_3)+TrainState_1_1_4)+TrainState_2_1_4)+TrainState_1_2_4)+TrainState_2_2_4)+TrainState_1_1_5)+TrainState_2_1_5)+TrainState_1_2_5)+TrainState_2_2_5)+TrainState_1_1_6)+TrainState_2_1_6)+TrainState_1_2_6)+TrainState_2_2_6)+TrainState_1_1_7)+TrainState_2_1_7)+TrainState_1_2_7)+TrainState_2_2_7)+TrainState_1_3_7)+TrainState_2_3_7)+TrainState_1_1_8)+TrainState_2_1_8)+TrainState_1_2_8)+TrainState_2_2_8)+TrainState_1_3_8)+TrainState_2_3_8)+TrainState_1_1_9)+TrainState_2_1_9)+TrainState_1_2_9)+TrainState_2_2_9)+TrainState_1_3_9)+TrainState_2_3_9)+TrainState_1_1_10)+TrainState_2_1_10)+TrainState_1_2_10)+TrainState_2_2_10)+TrainState_1_3_10)+TrainState_2_3_10)+TrainState_1_1_11)+TrainState_2_1_11)+TrainState_1_2_11)+TrainState_2_2_11)+TrainState_1_3_11)+TrainState_2_3_11)+TrainState_1_4_11)+TrainState_2_4_11)+TrainState_1_1_12)+TrainState_2_1_12)+TrainState_1_2_12)+TrainState_2_2_12)+TrainState_1_3_12)+TrainState_2_3_12)+TrainState_1_4_12)+TrainState_2_4_12)+TrainState_1_1_13)+TrainState_2_1_13)+TrainState_1_2_13)+TrainState_2_2_13)+TrainState_1_3_13)+TrainState_2_3_13)+TrainState_1_4_13)+TrainState_2_4_13)+TrainState_1_1_14)+TrainState_2_1_14)+TrainState_1_2_14)+TrainState_2_2_14)+TrainState_1_3_14)+TrainState_2_3_14)+TrainState_1_4_14)+TrainState_2_4_14)+TrainState_1_1_15)+TrainState_2_1_15)+TrainState_1_2_15)+TrainState_2_2_15)+TrainState_1_3_15)+TrainState_2_3_15)+TrainState_1_4_15)+TrainState_2_4_15)+TrainState_1_1_16)+TrainState_2_1_16)+TrainState_1_2_16)+TrainState_2_2_16)+TrainState_1_3_16)+TrainState_2_3_16)+TrainState_1_4_16)+TrainState_2_4_16)+TrainState_1_1_17)+TrainState_2_1_17)+TrainState_1_2_17)+TrainState_2_2_17)+TrainState_1_3_17)+TrainState_2_3_17)+TrainState_1_4_17)+TrainState_2_4_17)+TrainState_1_1_18)+TrainState_2_1_18)+TrainState_1_2_18)+TrainState_2_2_18)+TrainState_1_3_18)+TrainState_2_3_18)+TrainState_1_4_18)+TrainState_2_4_18)+TrainState_1_1_19)+TrainState_2_1_19)+TrainState_1_2_19)+TrainState_2_2_19)+TrainState_1_3_19)+TrainState_2_3_19)+TrainState_1_4_19)+TrainState_2_4_19)+TrainState_1_1_20)+TrainState_2_1_20)+TrainState_1_2_20)+TrainState_2_2_20)+TrainState_1_3_20)+TrainState_2_3_20)+TrainState_1_4_20)+TrainState_2_4_20)+TrainState_1_1_21)+TrainState_2_1_21)+TrainState_1_2_21)+TrainState_2_2_21)+TrainState_1_3_21)+TrainState_2_3_21)+TrainState_1_4_21)+TrainState_2_4_21)+TrainState_1_1_22)+TrainState_2_1_22)+TrainState_1_2_22)+TrainState_2_2_22)+TrainState_1_3_22)+TrainState_2_3_22)+TrainState_1_4_22)+TrainState_2_4_22)+TrainState_1_1_23)+TrainState_2_1_23)+TrainState_1_2_23)+TrainState_2_2_23)+TrainState_1_3_23)+TrainState_2_3_23)+TrainState_1_4_23)+TrainState_2_4_23)+TrainState_1_1_24)+TrainState_2_1_24)+TrainState_1_2_24)+TrainState_2_2_24)+TrainState_1_3_24)+TrainState_2_3_24)+TrainState_1_4_24)+TrainState_2_4_24)+TrainState_1_1_25)+TrainState_2_1_25)+TrainState_1_2_25)+TrainState_2_2_25)+TrainState_1_3_25)+TrainState_2_3_25)+TrainState_1_4_25)+TrainState_2_4_25)+TrainState_1_1_26)+TrainState_2_1_26)+TrainState_1_2_26)+TrainState_2_2_26)+TrainState_1_3_26)+TrainState_2_3_26)+TrainState_1_4_26)+TrainState_2_4_26)+TrainState_1_1_27)+TrainState_2_1_27)+TrainState_1_2_27)+TrainState_2_2_27)+TrainState_1_3_27)+TrainState_2_3_27)+TrainState_1_4_27)+TrainState_2_4_27)+TrainState_1_1_28)+TrainState_2_1_28)+TrainState_1_2_28)+TrainState_2_2_28)+TrainState_1_3_28)+TrainState_2_3_28)+TrainState_1_4_28)+TrainState_2_4_28)+TrainState_1_1_29)+TrainState_2_1_29)+TrainState_1_2_29)+TrainState_2_2_29)+TrainState_1_3_29)+TrainState_2_3_29)+TrainState_1_4_29)+TrainState_2_4_29)+TrainState_1_1_30)+TrainState_2_1_30)+TrainState_1_2_30)+TrainState_2_2_30)+TrainState_1_3_30)+TrainState_2_3_30)+TrainState_1_4_30)+TrainState_2_4_30)+TrainState_1_1_31)+TrainState_2_1_31)+TrainState_1_2_31)+TrainState_2_2_31)+TrainState_1_3_31)+TrainState_2_3_31)+TrainState_1_4_31)+TrainState_2_4_31)+TrainState_1_1_32)+TrainState_2_1_32)+TrainState_1_2_32)+TrainState_2_2_32)+TrainState_1_3_32)+TrainState_2_3_32)+TrainState_1_4_32)+TrainState_2_4_32)+TrainState_1_1_33)+TrainState_2_1_33)+TrainState_1_2_33)+TrainState_2_2_33)+TrainState_1_3_33)+TrainState_2_3_33)+TrainState_1_4_33)+TrainState_2_4_33)+TrainState_1_1_34)+TrainState_2_1_34)+TrainState_1_2_34)+TrainState_2_2_34)+TrainState_1_3_34)+TrainState_2_3_34)+TrainState_1_4_34)+TrainState_2_4_34)+TrainState_1_1_35)+TrainState_2_1_35)+TrainState_1_2_35)+TrainState_2_2_35)+TrainState_1_3_35)+TrainState_2_3_35)+TrainState_1_1_36)+TrainState_2_1_36)+TrainState_1_2_36)+TrainState_2_2_36)+TrainState_1_3_36)+TrainState_2_3_36)+TrainState_1_1_37)+TrainState_2_1_37)+TrainState_1_2_37)+TrainState_2_2_37)+TrainState_1_3_37)+TrainState_2_3_37)+TrainState_1_1_38)+TrainState_2_1_38)+TrainState_1_2_38)+TrainState_2_2_38)+TrainState_1_1_39)+TrainState_2_1_39)+TrainState_1_2_39)+TrainState_2_2_39)+TrainState_1_1_40)+TrainState_2_1_40)>=1)
Read [reachable] property : BART-PT-002-ReachabilityCardinality-03 with value :(!((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((TrainState_1_0_0+TrainState_2_0_0)+TrainState_1_1_1)+TrainState_2_1_1)+TrainState_1_1_2)+TrainState_2_1_2)+TrainState_1_1_3)+TrainState_2_1_3)+TrainState_1_1_4)+TrainState_2_1_4)+TrainState_1_2_4)+TrainState_2_2_4)+TrainState_1_1_5)+TrainState_2_1_5)+TrainState_1_2_5)+TrainState_2_2_5)+TrainState_1_1_6)+TrainState_2_1_6)+TrainState_1_2_6)+TrainState_2_2_6)+TrainState_1_1_7)+TrainState_2_1_7)+TrainState_1_2_7)+TrainState_2_2_7)+TrainState_1_3_7)+TrainState_2_3_7)+TrainState_1_1_8)+TrainState_2_1_8)+TrainState_1_2_8)+TrainState_2_2_8)+TrainState_1_3_8)+TrainState_2_3_8)+TrainState_1_1_9)+TrainState_2_1_9)+TrainState_1_2_9)+TrainState_2_2_9)+TrainState_1_3_9)+TrainState_2_3_9)+TrainState_1_1_10)+TrainState_2_1_10)+TrainState_1_2_10)+TrainState_2_2_10)+TrainState_1_3_10)+TrainState_2_3_10)+TrainState_1_1_11)+TrainState_2_1_11)+TrainState_1_2_11)+TrainState_2_2_11)+TrainState_1_3_11)+TrainState_2_3_11)+TrainState_1_4_11)+TrainState_2_4_11)+TrainState_1_1_12)+TrainState_2_1_12)+TrainState_1_2_12)+TrainState_2_2_12)+TrainState_1_3_12)+TrainState_2_3_12)+TrainState_1_4_12)+TrainState_2_4_12)+TrainState_1_1_13)+TrainState_2_1_13)+TrainState_1_2_13)+TrainState_2_2_13)+TrainState_1_3_13)+TrainState_2_3_13)+TrainState_1_4_13)+TrainState_2_4_13)+TrainState_1_1_14)+TrainState_2_1_14)+TrainState_1_2_14)+TrainState_2_2_14)+TrainState_1_3_14)+TrainState_2_3_14)+TrainState_1_4_14)+TrainState_2_4_14)+TrainState_1_1_15)+TrainState_2_1_15)+TrainState_1_2_15)+TrainState_2_2_15)+TrainState_1_3_15)+TrainState_2_3_15)+TrainState_1_4_15)+TrainState_2_4_15)+TrainState_1_1_16)+TrainState_2_1_16)+TrainState_1_2_16)+TrainState_2_2_16)+TrainState_1_3_16)+TrainState_2_3_16)+TrainState_1_4_16)+TrainState_2_4_16)+TrainState_1_1_17)+TrainState_2_1_17)+TrainState_1_2_17)+TrainState_2_2_17)+TrainState_1_3_17)+TrainState_2_3_17)+TrainState_1_4_17)+TrainState_2_4_17)+TrainState_1_1_18)+TrainState_2_1_18)+TrainState_1_2_18)+TrainState_2_2_18)+TrainState_1_3_18)+TrainState_2_3_18)+TrainState_1_4_18)+TrainState_2_4_18)+TrainState_1_1_19)+TrainState_2_1_19)+TrainState_1_2_19)+TrainState_2_2_19)+TrainState_1_3_19)+TrainState_2_3_19)+TrainState_1_4_19)+TrainState_2_4_19)+TrainState_1_1_20)+TrainState_2_1_20)+TrainState_1_2_20)+TrainState_2_2_20)+TrainState_1_3_20)+TrainState_2_3_20)+TrainState_1_4_20)+TrainState_2_4_20)+TrainState_1_1_21)+TrainState_2_1_21)+TrainState_1_2_21)+TrainState_2_2_21)+TrainState_1_3_21)+TrainState_2_3_21)+TrainState_1_4_21)+TrainState_2_4_21)+TrainState_1_1_22)+TrainState_2_1_22)+TrainState_1_2_22)+TrainState_2_2_22)+TrainState_1_3_22)+TrainState_2_3_22)+TrainState_1_4_22)+TrainState_2_4_22)+TrainState_1_1_23)+TrainState_2_1_23)+TrainState_1_2_23)+TrainState_2_2_23)+TrainState_1_3_23)+TrainState_2_3_23)+TrainState_1_4_23)+TrainState_2_4_23)+TrainState_1_1_24)+TrainState_2_1_24)+TrainState_1_2_24)+TrainState_2_2_24)+TrainState_1_3_24)+TrainState_2_3_24)+TrainState_1_4_24)+TrainState_2_4_24)+TrainState_1_1_25)+TrainState_2_1_25)+TrainState_1_2_25)+TrainState_2_2_25)+TrainState_1_3_25)+TrainState_2_3_25)+TrainState_1_4_25)+TrainState_2_4_25)+TrainState_1_1_26)+TrainState_2_1_26)+TrainState_1_2_26)+TrainState_2_2_26)+TrainState_1_3_26)+TrainState_2_3_26)+TrainState_1_4_26)+TrainState_2_4_26)+TrainState_1_1_27)+TrainState_2_1_27)+TrainState_1_2_27)+TrainState_2_2_27)+TrainState_1_3_27)+TrainState_2_3_27)+TrainState_1_4_27)+TrainState_2_4_27)+TrainState_1_1_28)+TrainState_2_1_28)+TrainState_1_2_28)+TrainState_2_2_28)+TrainState_1_3_28)+TrainState_2_3_28)+TrainState_1_4_28)+TrainState_2_4_28)+TrainState_1_1_29)+TrainState_2_1_29)+TrainState_1_2_29)+TrainState_2_2_29)+TrainState_1_3_29)+TrainState_2_3_29)+TrainState_1_4_29)+TrainState_2_4_29)+TrainState_1_1_30)+TrainState_2_1_30)+TrainState_1_2_30)+TrainState_2_2_30)+TrainState_1_3_30)+TrainState_2_3_30)+TrainState_1_4_30)+TrainState_2_4_30)+TrainState_1_1_31)+TrainState_2_1_31)+TrainState_1_2_31)+TrainState_2_2_31)+TrainState_1_3_31)+TrainState_2_3_31)+TrainState_1_4_31)+TrainState_2_4_31)+TrainState_1_1_32)+TrainState_2_1_32)+TrainState_1_2_32)+TrainState_2_2_32)+TrainState_1_3_32)+TrainState_2_3_32)+TrainState_1_4_32)+TrainState_2_4_32)+TrainState_1_1_33)+TrainState_2_1_33)+TrainState_1_2_33)+TrainState_2_2_33)+TrainState_1_3_33)+TrainState_2_3_33)+TrainState_1_4_33)+TrainState_2_4_33)+TrainState_1_1_34)+TrainState_2_1_34)+TrainState_1_2_34)+TrainState_2_2_34)+TrainState_1_3_34)+TrainState_2_3_34)+TrainState_1_4_34)+TrainState_2_4_34)+TrainState_1_1_35)+TrainState_2_1_35)+TrainState_1_2_35)+TrainState_2_2_35)+TrainState_1_3_35)+TrainState_2_3_35)+TrainState_1_1_36)+TrainState_2_1_36)+TrainState_1_2_36)+TrainState_2_2_36)+TrainState_1_3_36)+TrainState_2_3_36)+TrainState_1_1_37)+TrainState_2_1_37)+TrainState_1_2_37)+TrainState_2_2_37)+TrainState_1_3_37)+TrainState_2_3_37)+TrainState_1_1_38)+TrainState_2_1_38)+TrainState_1_2_38)+TrainState_2_2_38)+TrainState_1_1_39)+TrainState_2_1_39)+TrainState_1_2_39)+TrainState_2_2_39)+TrainState_1_1_40)+TrainState_2_1_40)>=2))
Read [reachable] property : BART-PT-002-ReachabilityCardinality-08 with value :(TrainState_2_1_29>=3)
Read [reachable] property : BART-PT-002-ReachabilityCardinality-09 with value :(TrainState_2_4_13>=2)
Read [reachable] property : BART-PT-002-ReachabilityCardinality-12 with value :(TrainState_1_4_18>=2)
Read [reachable] property : BART-PT-002-ReachabilityCardinality-13 with value :(!(TrainState_2_1_22<=1))
Read [invariant] property : BART-PT-002-ReachabilityCardinality-15 with value :((!((TrainState_1_2_31>=1)&&(TrainState_1_3_37>=1)))&&(!(TrainState_1_4_25>=3)))
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART\_PT\_002\_flat\_flat,17424,0.318759,8564,2,1046,5,21923,6,0,1463,18180,0
Total reachable state count : 17424

Verifying 7 reachability properties.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 404 rows 264 cols
invariant :TrainState_2_0_0 + TrainState_2_1_1 + TrainState_2_1_2 + TrainState_2_1_3 + TrainState_2_1_4 + TrainState_2_2_4 + TrainState_2_1_5 + TrainState_2_2_5 + TrainState_2_1_6 + TrainState_2_2_6 + TrainState_2_1_7 + TrainState_2_2_7 + TrainState_2_3_7 + TrainState_2_1_8 + TrainState_2_2_8 + TrainState_2_3_8 + TrainState_2_1_9 + TrainState_2_2_9 + TrainState_2_3_9 + TrainState_2_1_10 + TrainState_2_2_10 + TrainState_2_3_10 + TrainState_2_1_11 + TrainState_2_2_11 + TrainState_2_3_11 + TrainState_2_4_11 + TrainState_2_1_12 + TrainState_2_2_12 + TrainState_2_3_12 + TrainState_2_4_12 + TrainState_2_1_13 + TrainState_2_2_13 + TrainState_2_3_13 + TrainState_2_4_13 + TrainState_2_1_14 + TrainState_2_2_14 + TrainState_2_3_14 + TrainState_2_4_14 + TrainState_2_1_15 + TrainState_2_2_15 + TrainState_2_3_15 + TrainState_2_4_15 + TrainState_2_1_16 + TrainState_2_2_16 + TrainState_2_3_16 + TrainState_2_4_16 + TrainState_2_1_17 + TrainState_2_2_17 + TrainState_2_3_17 + TrainState_2_4_17 + TrainState_2_1_18 + TrainState_2_2_18 + TrainState_2_3_18 + TrainState_2_4_18 + TrainState_2_1_19 + TrainState_2_2_19 + TrainState_2_3_19 + TrainState_2_4_19 + TrainState_2_1_20 + TrainState_2_2_20 + TrainState_2_3_20 + TrainState_2_4_20 + TrainState_2_1_21 + TrainState_2_2_21 + TrainState_2_3_21 + TrainState_2_4_21 + TrainState_2_1_22 + TrainState_2_2_22 + TrainState_2_3_22 + TrainState_2_4_22 + TrainState_2_1_23 + TrainState_2_2_23 + TrainState_2_3_23 + TrainState_2_4_23 + TrainState_2_1_24 + TrainState_2_2_24 + TrainState_2_3_24 + TrainState_2_4_24 + TrainState_2_1_25 + TrainState_2_2_25 + TrainState_2_3_25 + TrainState_2_4_25 + TrainState_2_1_26 + TrainState_2_2_26 + TrainState_2_3_26 + TrainState_2_4_26 + TrainState_2_1_27 + TrainState_2_2_27 + TrainState_2_3_27 + TrainState_2_4_27 + TrainState_2_1_28 + TrainState_2_2_28 + TrainState_2_3_28 + TrainState_2_4_28 + TrainState_2_1_29 + TrainState_2_2_29 + TrainState_2_3_29 + TrainState_2_4_29 + TrainState_2_1_30 + TrainState_2_2_30 + TrainState_2_3_30 + TrainState_2_4_30 + TrainState_2_1_31 + TrainState_2_2_31 + TrainState_2_3_31 + TrainState_2_4_31 + TrainState_2_1_32 + TrainState_2_2_32 + TrainState_2_3_32 + TrainState_2_4_32 + TrainState_2_1_33 + TrainState_2_2_33 + TrainState_2_3_33 + TrainState_2_4_33 + TrainState_2_1_34 + TrainState_2_2_34 + TrainState_2_3_34 + TrainState_2_4_34 + TrainState_2_1_35 + TrainState_2_2_35 + TrainState_2_3_35 + TrainState_2_1_36 + TrainState_2_2_36 + TrainState_2_3_36 + TrainState_2_1_37 + TrainState_2_2_37 + TrainState_2_3_37 + TrainState_2_1_38 + TrainState_2_2_38 + TrainState_2_1_39 + TrainState_2_2_39 + TrainState_2_1_40 = 1
invariant :TrainState_1_0_0 + TrainState_1_1_1 + TrainState_1_1_2 + TrainState_1_1_3 + TrainState_1_1_4 + TrainState_1_2_4 + TrainState_1_1_5 + TrainState_1_2_5 + TrainState_1_1_6 + TrainState_1_2_6 + TrainState_1_1_7 + TrainState_1_2_7 + TrainState_1_3_7 + TrainState_1_1_8 + TrainState_1_2_8 + TrainState_1_3_8 + TrainState_1_1_9 + TrainState_1_2_9 + TrainState_1_3_9 + TrainState_1_1_10 + TrainState_1_2_10 + TrainState_1_3_10 + TrainState_1_1_11 + TrainState_1_2_11 + TrainState_1_3_11 + TrainState_1_4_11 + TrainState_1_1_12 + TrainState_1_2_12 + TrainState_1_3_12 + TrainState_1_4_12 + TrainState_1_1_13 + TrainState_1_2_13 + TrainState_1_3_13 + TrainState_1_4_13 + TrainState_1_1_14 + TrainState_1_2_14 + TrainState_1_3_14 + TrainState_1_4_14 + TrainState_1_1_15 + TrainState_1_2_15 + TrainState_1_3_15 + TrainState_1_4_15 + TrainState_1_1_16 + TrainState_1_2_16 + TrainState_1_3_16 + TrainState_1_4_16 + TrainState_1_1_17 + TrainState_1_2_17 + TrainState_1_3_17 + TrainState_1_4_17 + TrainState_1_1_18 + TrainState_1_2_18 + TrainState_1_3_18 + TrainState_1_4_18 + TrainState_1_1_19 + TrainState_1_2_19 + TrainState_1_3_19 + TrainState_1_4_19 + TrainState_1_1_20 + TrainState_1_2_20 + TrainState_1_3_20 + TrainState_1_4_20 + TrainState_1_1_21 + TrainState_1_2_21 + TrainState_1_3_21 + TrainState_1_4_21 + TrainState_1_1_22 + TrainState_1_2_22 + TrainState_1_3_22 + TrainState_1_4_22 + TrainState_1_1_23 + TrainState_1_2_23 + TrainState_1_3_23 + TrainState_1_4_23 + TrainState_1_1_24 + TrainState_1_2_24 + TrainState_1_3_24 + TrainState_1_4_24 + TrainState_1_1_25 + TrainState_1_2_25 + TrainState_1_3_25 + TrainState_1_4_25 + TrainState_1_1_26 + TrainState_1_2_26 + TrainState_1_3_26 + TrainState_1_4_26 + TrainState_1_1_27 + TrainState_1_2_27 + TrainState_1_3_27 + TrainState_1_4_27 + TrainState_1_1_28 + TrainState_1_2_28 + TrainState_1_3_28 + TrainState_1_4_28 + TrainState_1_1_29 + TrainState_1_2_29 + TrainState_1_3_29 + TrainState_1_4_29 + TrainState_1_1_30 + TrainState_1_2_30 + TrainState_1_3_30 + TrainState_1_4_30 + TrainState_1_1_31 + TrainState_1_2_31 + TrainState_1_3_31 + TrainState_1_4_31 + TrainState_1_1_32 + TrainState_1_2_32 + TrainState_1_3_32 + TrainState_1_4_32 + TrainState_1_1_33 + TrainState_1_2_33 + TrainState_1_3_33 + TrainState_1_4_33 + TrainState_1_1_34 + TrainState_1_2_34 + TrainState_1_3_34 + TrainState_1_4_34 + TrainState_1_1_35 + TrainState_1_2_35 + TrainState_1_3_35 + TrainState_1_1_36 + TrainState_1_2_36 + TrainState_1_3_36 + TrainState_1_1_37 + TrainState_1_2_37 + TrainState_1_3_37 + TrainState_1_1_38 + TrainState_1_2_38 + TrainState_1_1_39 + TrainState_1_2_39 + TrainState_1_1_40 = 1
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 404 rows 264 cols
invariant :TrainState_2_0_0 + TrainState_2_1_1 + TrainState_2_1_2 + TrainState_2_1_3 + TrainState_2_1_4 + TrainState_2_2_4 + TrainState_2_1_5 + TrainState_2_2_5 + TrainState_2_1_6 + TrainState_2_2_6 + TrainState_2_1_7 + TrainState_2_2_7 + TrainState_2_3_7 + TrainState_2_1_8 + TrainState_2_2_8 + TrainState_2_3_8 + TrainState_2_1_9 + TrainState_2_2_9 + TrainState_2_3_9 + TrainState_2_1_10 + TrainState_2_2_10 + TrainState_2_3_10 + TrainState_2_1_11 + TrainState_2_2_11 + TrainState_2_3_11 + TrainState_2_4_11 + TrainState_2_1_12 + TrainState_2_2_12 + TrainState_2_3_12 + TrainState_2_4_12 + TrainState_2_1_13 + TrainState_2_2_13 + TrainState_2_3_13 + TrainState_2_4_13 + TrainState_2_1_14 + TrainState_2_2_14 + TrainState_2_3_14 + TrainState_2_4_14 + TrainState_2_1_15 + TrainState_2_2_15 + TrainState_2_3_15 + TrainState_2_4_15 + TrainState_2_1_16 + TrainState_2_2_16 + TrainState_2_3_16 + TrainState_2_4_16 + TrainState_2_1_17 + TrainState_2_2_17 + TrainState_2_3_17 + TrainState_2_4_17 + TrainState_2_1_18 + TrainState_2_2_18 + TrainState_2_3_18 + TrainState_2_4_18 + TrainState_2_1_19 + TrainState_2_2_19 + TrainState_2_3_19 + TrainState_2_4_19 + TrainState_2_1_20 + TrainState_2_2_20 + TrainState_2_3_20 + TrainState_2_4_20 + TrainState_2_1_21 + TrainState_2_2_21 + TrainState_2_3_21 + TrainState_2_4_21 + TrainState_2_1_22 + TrainState_2_2_22 + TrainState_2_3_22 + TrainState_2_4_22 + TrainState_2_1_23 + TrainState_2_2_23 + TrainState_2_3_23 + TrainState_2_4_23 + TrainState_2_1_24 + TrainState_2_2_24 + TrainState_2_3_24 + TrainState_2_4_24 + TrainState_2_1_25 + TrainState_2_2_25 + TrainState_2_3_25 + TrainState_2_4_25 + TrainState_2_1_26 + TrainState_2_2_26 + TrainState_2_3_26 + TrainState_2_4_26 + TrainState_2_1_27 + TrainState_2_2_27 + TrainState_2_3_27 + TrainState_2_4_27 + TrainState_2_1_28 + TrainState_2_2_28 + TrainState_2_3_28 + TrainState_2_4_28 + TrainState_2_1_29 + TrainState_2_2_29 + TrainState_2_3_29 + TrainState_2_4_29 + TrainState_2_1_30 + TrainState_2_2_30 + TrainState_2_3_30 + TrainState_2_4_30 + TrainState_2_1_31 + TrainState_2_2_31 + TrainState_2_3_31 + TrainState_2_4_31 + TrainState_2_1_32 + TrainState_2_2_32 + TrainState_2_3_32 + TrainState_2_4_32 + TrainState_2_1_33 + TrainState_2_2_33 + TrainState_2_3_33 + TrainState_2_4_33 + TrainState_2_1_34 + TrainState_2_2_34 + TrainState_2_3_34 + TrainState_2_4_34 + TrainState_2_1_35 + TrainState_2_2_35 + TrainState_2_3_35 + TrainState_2_1_36 + TrainState_2_2_36 + TrainState_2_3_36 + TrainState_2_1_37 + TrainState_2_2_37 + TrainState_2_3_37 + TrainState_2_1_38 + TrainState_2_2_38 + TrainState_2_1_39 + TrainState_2_2_39 + TrainState_2_1_40 = 1
invariant :TrainState_1_0_0 + TrainState_1_1_1 + TrainState_1_1_2 + TrainState_1_1_3 + TrainState_1_1_4 + TrainState_1_2_4 + TrainState_1_1_5 + TrainState_1_2_5 + TrainState_1_1_6 + TrainState_1_2_6 + TrainState_1_1_7 + TrainState_1_2_7 + TrainState_1_3_7 + TrainState_1_1_8 + TrainState_1_2_8 + TrainState_1_3_8 + TrainState_1_1_9 + TrainState_1_2_9 + TrainState_1_3_9 + TrainState_1_1_10 + TrainState_1_2_10 + TrainState_1_3_10 + TrainState_1_1_11 + TrainState_1_2_11 + TrainState_1_3_11 + TrainState_1_4_11 + TrainState_1_1_12 + TrainState_1_2_12 + TrainState_1_3_12 + TrainState_1_4_12 + TrainState_1_1_13 + TrainState_1_2_13 + TrainState_1_3_13 + TrainState_1_4_13 + TrainState_1_1_14 + TrainState_1_2_14 + TrainState_1_3_14 + TrainState_1_4_14 + TrainState_1_1_15 + TrainState_1_2_15 + TrainState_1_3_15 + TrainState_1_4_15 + TrainState_1_1_16 + TrainState_1_2_16 + TrainState_1_3_16 + TrainState_1_4_16 + TrainState_1_1_17 + TrainState_1_2_17 + TrainState_1_3_17 + TrainState_1_4_17 + TrainState_1_1_18 + TrainState_1_2_18 + TrainState_1_3_18 + TrainState_1_4_18 + TrainState_1_1_19 + TrainState_1_2_19 + TrainState_1_3_19 + TrainState_1_4_19 + TrainState_1_1_20 + TrainState_1_2_20 + TrainState_1_3_20 + TrainState_1_4_20 + TrainState_1_1_21 + TrainState_1_2_21 + TrainState_1_3_21 + TrainState_1_4_21 + TrainState_1_1_22 + TrainState_1_2_22 + TrainState_1_3_22 + TrainState_1_4_22 + TrainState_1_1_23 + TrainState_1_2_23 + TrainState_1_3_23 + TrainState_1_4_23 + TrainState_1_1_24 + TrainState_1_2_24 + TrainState_1_3_24 + TrainState_1_4_24 + TrainState_1_1_25 + TrainState_1_2_25 + TrainState_1_3_25 + TrainState_1_4_25 + TrainState_1_1_26 + TrainState_1_2_26 + TrainState_1_3_26 + TrainState_1_4_26 + TrainState_1_1_27 + TrainState_1_2_27 + TrainState_1_3_27 + TrainState_1_4_27 + TrainState_1_1_28 + TrainState_1_2_28 + TrainState_1_3_28 + TrainState_1_4_28 + TrainState_1_1_29 + TrainState_1_2_29 + TrainState_1_3_29 + TrainState_1_4_29 + TrainState_1_1_30 + TrainState_1_2_30 + TrainState_1_3_30 + TrainState_1_4_30 + TrainState_1_1_31 + TrainState_1_2_31 + TrainState_1_3_31 + TrainState_1_4_31 + TrainState_1_1_32 + TrainState_1_2_32 + TrainState_1_3_32 + TrainState_1_4_32 + TrainState_1_1_33 + TrainState_1_2_33 + TrainState_1_3_33 + TrainState_1_4_33 + TrainState_1_1_34 + TrainState_1_2_34 + TrainState_1_3_34 + TrainState_1_4_34 + TrainState_1_1_35 + TrainState_1_2_35 + TrainState_1_3_35 + TrainState_1_1_36 + TrainState_1_2_36 + TrainState_1_3_36 + TrainState_1_1_37 + TrainState_1_2_37 + TrainState_1_3_37 + TrainState_1_1_38 + TrainState_1_2_38 + TrainState_1_1_39 + TrainState_1_2_39 + TrainState_1_1_40 = 1
Invariant property BART-PT-002-ReachabilityCardinality-00 is true.
FORMULA BART-PT-002-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-00,0,9.27802,44436,1,0,5,21923,7,0,14225,18180,0
Reachability property BART-PT-002-ReachabilityCardinality-03 does not hold.
FORMULA BART-PT-002-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : BART-PT-002-ReachabilityCardinality-03

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-03,0,16.6026,56284,1,0,5,21923,8,0,26986,18180,0
Reachability property BART-PT-002-ReachabilityCardinality-08 does not hold.
FORMULA BART-PT-002-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : BART-PT-002-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-08,0,16.6034,56308,1,0,5,21923,9,0,26987,18180,0
Reachability property BART-PT-002-ReachabilityCardinality-09 does not hold.
FORMULA BART-PT-002-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : BART-PT-002-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-09,0,16.6043,56444,1,0,5,21923,10,0,26988,18180,0
Reachability property BART-PT-002-ReachabilityCardinality-12 does not hold.
FORMULA BART-PT-002-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : BART-PT-002-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-12,0,16.6049,56572,1,0,5,21923,11,0,26989,18180,0
Reachability property BART-PT-002-ReachabilityCardinality-13 does not hold.
FORMULA BART-PT-002-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : BART-PT-002-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-13,0,16.6056,56620,1,0,5,21923,12,0,26990,18180,0
Invariant property BART-PT-002-ReachabilityCardinality-15 is true.
FORMULA BART-PT-002-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
BART-PT-002-ReachabilityCardinality-15,0,16.6068,56652,1,0,5,21923,13,0,26995,18180,0
ITS tools runner thread asked to quit. Dying gracefully.
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526856968128

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 20, 2018 10:55:48 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 20, 2018 10:55:48 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 20, 2018 10:55:49 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 179 ms
May 20, 2018 10:55:49 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 474 places.
May 20, 2018 10:55:49 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 404 transitions.
May 20, 2018 10:55:49 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 83 ms
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 210 fixed domain variables (out of 474 variables) in GAL type BART_PT_002
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 210 constant array cells/variables (out of 474 variables) in type BART_PT_002
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: NewDistTable_19_5_14,NewDistTable_16_2_14,NewDistTable_34_3_31,NewDistTable_22_1_21,DistStation_24,NewDistTable_34_1_33,DistStation_14,NewDistTable_16_5_11,NewDistTable_38_3_35,StopTable_3_6,NewDistTable_28_4_24,NewDistTable_25_4_21,NewDistTable_39_1_38,NewDistTable_37_2_35,DistStation_7,NewDistTable_19_4_15,DistStation_25,NewDistTable_5_2_3,DistStation_32,DistStation_6,NewDistTable_39_3_36,NewDistTable_4_1_3,NewDistTable_18_4_14,NewDistTable_34_5_29,DistStation_8,NewDistTable_10_1_9,NewDistTable_37_3_34,NewDistTable_39_2_37,DistStation_36,DistStation_39,NewDistTable_22_4_18,NewDistTable_35_4_31,NewDistTable_29_1_28,NewDistTable_35_3_32,DistStation_15,NewDistTable_33_5_28,NewDistTable_15_4_11,NewDistTable_19_1_18,NewDistTable_20_5_15,NewDistTable_33_4_29,DistStation_19,DistStation_12,NewDistTable_14_2_12,NewDistTable_24_2_22,NewDistTable_31_4_27,NewDistTable_40_1_39,NewDistTable_10_3_7,NewDistTable_12_1_11,NewDistTable_21_1_20,NewDistTable_17_4_13,NewDistTable_9_1_8,NewDistTable_36_3_33,NewDistTable_11_5_6,NewDistTable_5_3_2,NewDistTable_15_3_12,DistStation_17,DistStation_33,NewDistTable_32_5_27,DistStation_9,DistStation_29,NewDistTable_27_5_22,NewDistTable_17_3_14,NewDistTable_24_4_20,NewDistTable_40_2_38,NewDistTable_28_5_23,NewDistTable_2_1_1,NewDistTable_13_4_9,DistStation_16,NewDistTable_16_4_12,NewDistTable_25_5_20,NewDistTable_11_4_7,DistStation_10,NewDistTable_32_1_31,NewDistTable_23_2_21,NewDistTable_34_4_30,NewDistTable_13_5_8,NewDistTable_30_4_26,NewDistTable_20_4_16,StopTable_2_3,NewDistTable_9_3_6,NewDistTable_30_1_29,NewDistTable_18_5_13,NewDistTable_30_2_28,NewDistTable_13_3_10,NewDistTable_4_3_1,NewDistTable_23_3_20,NewDistTable_17_5_12,StopTable_5_15,DistStation_30,NewDistTable_18_3_15,NewDistTable_2_2_0,NewDistTable_28_1_27,NewDistTable_30_3_27,NewDistTable_12_5_7,NewDistTable_6_2_4,NewDistTable_17_1_16,NewDistTable_3_1_2,NewDistTable_20_1_19,DistStation_18,DistStation_37,NewDistTable_21_2_19,NewDistTable_23_1_22,NewDistTable_29_3_26,DistStation_28,NewDistTable_31_3_28,NewDistTable_23_4_19,NewDistTable_10_4_6,NewDistTable_38_2_36,NewDistTable_12_2_10,NewDistTable_26_2_24,NewDistTable_22_3_19,NewDistTable_24_5_19,DistStation_40,NewDistTable_31_1_30,NewDistTable_26_4_22,NewDistTable_31_5_26,DistStation_35,NewDistTable_8_1_7,NewDistTable_32_4_28,NewDistTable_16_1_15,DistStation_20,NewDistTable_14_3_11,NewDistTable_35_1_34,NewDistTable_23_5_18,NewDistTable_6_3_3,NewDistTable_11_1_10,NewDistTable_27_2_25,NewDistTable_3_2_1,NewDistTable_27_3_24,NewDistTable_15_2_13,NewDistTable_38_1_37,NewDistTable_30_5_25,DistStation_5,NewDistTable_4_2_2,NewDistTable_28_3_25,NewDistTable_5_1_4,NewDistTable_29_4_25,NewDistTable_25_3_22,NewDistTable_25_2_23,DistStation_13,NewDistTable_19_2_17,DistStation_34,DistStation_27,NewDistTable_18_1_17,NewDistTable_31_2_29,DistStation_22,NewDistTable_21_3_18,DistStation_21,NewDistTable_12_4_8,NewDistTable_7_2_5,StopTable_4_10,NewDistTable_24_3_21,NewDistTable_11_3_8,NewDistTable_8_4_4,NewDistTable_36_4_32,DistStation_23,NewDistTable_8_2_6,NewDistTable_7_4_3,NewDistTable_32_3_29,NewDistTable_32_2_30,NewDistTable_33_1_32,NewDistTable_7_1_6,NewDistTable_9_4_5,NewDistTable_26_1_25,NewDistTable_27_1_26,NewDistTable_8_3_5,NewDistTable_33_3_30,NewDistTable_16_3_13,NewDistTable_21_4_17,NewDistTable_10_2_8,NewDistTable_37_4_33,NewDistTable_34_2_32,NewDistTable_28_2_26,NewDistTable_37_1_36,NewDistTable_13_1_12,NewDistTable_18_2_16,NewDistTable_14_4_10,NewDistTable_36_1_35,NewDistTable_7_3_4,StopTable_1_1,NewDistTable_17_2_15,NewDistTable_20_2_18,NewDistTable_22_2_20,DistStation_11,NewDistTable_20_3_17,NewDistTable_26_5_21,NewDistTable_15_5_10,NewDistTable_9_2_7,NewDistTable_15_1_14,NewDistTable_11_2_9,NewDistTable_26_3_23,NewDistTable_25_1_24,NewDistTable_14_1_13,NewDistTable_6_1_5,DistStation_38,DistStation_31,DistStation_26,NewDistTable_19_3_16,NewDistTable_24_1_23,NewDistTable_33_2_31,NewDistTable_14_5_9,NewDistTable_13_2_11,NewDistTable_29_2_27,NewDistTable_12_3_9,NewDistTable_22_5_17,NewDistTable_29_5_24,NewDistTable_21_5_16,NewDistTable_27_4_23,NewDistTable_36_2_34,NewDistTable_35_2_33,
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed 210 constant variables :NewDistTable_19_5_14=1, NewDistTable_16_2_14=1, NewDistTable_34_3_31=1, NewDistTable_22_1_21=1, DistStation_24=1, NewDistTable_34_1_33=1, DistStation_14=1, NewDistTable_16_5_11=1, NewDistTable_38_3_35=1, StopTable_3_6=1, NewDistTable_28_4_24=1, NewDistTable_25_4_21=1, NewDistTable_39_1_38=1, NewDistTable_37_2_35=1, DistStation_7=1, NewDistTable_19_4_15=1, DistStation_25=1, NewDistTable_5_2_3=1, DistStation_32=1, DistStation_6=1, NewDistTable_39_3_36=1, NewDistTable_4_1_3=1, NewDistTable_18_4_14=1, NewDistTable_34_5_29=1, DistStation_8=1, NewDistTable_10_1_9=1, NewDistTable_37_3_34=1, NewDistTable_39_2_37=1, DistStation_36=1, DistStation_39=1, NewDistTable_22_4_18=1, NewDistTable_35_4_31=1, NewDistTable_29_1_28=1, NewDistTable_35_3_32=1, DistStation_15=1, NewDistTable_33_5_28=1, NewDistTable_15_4_11=1, NewDistTable_19_1_18=1, NewDistTable_20_5_15=1, NewDistTable_33_4_29=1, DistStation_19=1, DistStation_12=1, NewDistTable_14_2_12=1, NewDistTable_24_2_22=1, NewDistTable_31_4_27=1, NewDistTable_40_1_39=1, NewDistTable_10_3_7=1, NewDistTable_12_1_11=1, NewDistTable_21_1_20=1, NewDistTable_17_4_13=1, NewDistTable_9_1_8=1, NewDistTable_36_3_33=1, NewDistTable_11_5_6=1, NewDistTable_5_3_2=1, NewDistTable_15_3_12=1, DistStation_17=1, DistStation_33=1, NewDistTable_32_5_27=1, DistStation_9=1, DistStation_29=1, NewDistTable_27_5_22=1, NewDistTable_17_3_14=1, NewDistTable_24_4_20=1, NewDistTable_40_2_38=1, NewDistTable_28_5_23=1, NewDistTable_2_1_1=1, NewDistTable_13_4_9=1, DistStation_16=1, NewDistTable_16_4_12=1, NewDistTable_25_5_20=1, NewDistTable_11_4_7=1, DistStation_10=1, NewDistTable_32_1_31=1, NewDistTable_23_2_21=1, NewDistTable_34_4_30=1, NewDistTable_13_5_8=1, NewDistTable_30_4_26=1, NewDistTable_20_4_16=1, StopTable_2_3=1, NewDistTable_9_3_6=1, NewDistTable_30_1_29=1, NewDistTable_18_5_13=1, NewDistTable_30_2_28=1, NewDistTable_13_3_10=1, NewDistTable_4_3_1=1, NewDistTable_23_3_20=1, NewDistTable_17_5_12=1, StopTable_5_15=1, DistStation_30=1, NewDistTable_18_3_15=1, NewDistTable_2_2_0=1, NewDistTable_28_1_27=1, NewDistTable_30_3_27=1, NewDistTable_12_5_7=1, NewDistTable_6_2_4=1, NewDistTable_17_1_16=1, NewDistTable_3_1_2=1, NewDistTable_20_1_19=1, DistStation_18=1, DistStation_37=1, NewDistTable_21_2_19=1, NewDistTable_23_1_22=1, NewDistTable_29_3_26=1, DistStation_28=1, NewDistTable_31_3_28=1, NewDistTable_23_4_19=1, NewDistTable_10_4_6=1, NewDistTable_38_2_36=1, NewDistTable_12_2_10=1, NewDistTable_26_2_24=1, NewDistTable_22_3_19=1, NewDistTable_24_5_19=1, DistStation_40=1, NewDistTable_31_1_30=1, NewDistTable_26_4_22=1, NewDistTable_31_5_26=1, DistStation_35=1, NewDistTable_8_1_7=1, NewDistTable_32_4_28=1, NewDistTable_16_1_15=1, DistStation_20=1, NewDistTable_14_3_11=1, NewDistTable_35_1_34=1, NewDistTable_23_5_18=1, NewDistTable_6_3_3=1, NewDistTable_11_1_10=1, NewDistTable_27_2_25=1, NewDistTable_3_2_1=1, NewDistTable_27_3_24=1, NewDistTable_15_2_13=1, NewDistTable_38_1_37=1, NewDistTable_30_5_25=1, DistStation_5=1, NewDistTable_4_2_2=1, NewDistTable_28_3_25=1, NewDistTable_5_1_4=1, NewDistTable_29_4_25=1, NewDistTable_25_3_22=1, NewDistTable_25_2_23=1, DistStation_13=1, NewDistTable_19_2_17=1, DistStation_34=1, DistStation_27=1, NewDistTable_18_1_17=1, NewDistTable_31_2_29=1, DistStation_22=1, NewDistTable_21_3_18=1, DistStation_21=1, NewDistTable_12_4_8=1, NewDistTable_7_2_5=1, StopTable_4_10=1, NewDistTable_24_3_21=1, NewDistTable_11_3_8=1, NewDistTable_8_4_4=1, NewDistTable_36_4_32=1, DistStation_23=1, NewDistTable_8_2_6=1, NewDistTable_7_4_3=1, NewDistTable_32_3_29=1, NewDistTable_32_2_30=1, NewDistTable_33_1_32=1, NewDistTable_7_1_6=1, NewDistTable_9_4_5=1, NewDistTable_26_1_25=1, NewDistTable_27_1_26=1, NewDistTable_8_3_5=1, NewDistTable_33_3_30=1, NewDistTable_16_3_13=1, NewDistTable_21_4_17=1, NewDistTable_10_2_8=1, NewDistTable_37_4_33=1, NewDistTable_34_2_32=1, NewDistTable_28_2_26=1, NewDistTable_37_1_36=1, NewDistTable_13_1_12=1, NewDistTable_18_2_16=1, NewDistTable_14_4_10=1, NewDistTable_36_1_35=1, NewDistTable_7_3_4=1, StopTable_1_1=1, NewDistTable_17_2_15=1, NewDistTable_20_2_18=1, NewDistTable_22_2_20=1, DistStation_11=1, NewDistTable_20_3_17=1, NewDistTable_26_5_21=1, NewDistTable_15_5_10=1, NewDistTable_9_2_7=1, NewDistTable_15_1_14=1, NewDistTable_11_2_9=1, NewDistTable_26_3_23=1, NewDistTable_25_1_24=1, NewDistTable_14_1_13=1, NewDistTable_6_1_5=1, DistStation_38=1, DistStation_31=1, DistStation_26=1, NewDistTable_19_3_16=1, NewDistTable_24_1_23=1, NewDistTable_33_2_31=1, NewDistTable_14_5_9=1, NewDistTable_13_2_11=1, NewDistTable_29_2_27=1, NewDistTable_12_3_9=1, NewDistTable_22_5_17=1, NewDistTable_29_5_24=1, NewDistTable_21_5_16=1, NewDistTable_27_4_23=1, NewDistTable_36_2_34=1, NewDistTable_35_2_33=1
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 1793 expressions due to constant valuations.
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 400 ms
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 164 ms
May 20, 2018 10:55:50 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 256 ms
May 20, 2018 10:55:50 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 23 ms
May 20, 2018 10:55:50 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 3 ms
May 20, 2018 10:55:50 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 404 transitions.
May 20, 2018 10:55:50 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 404 transitions.
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 7 in 753 ms.
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-00(UNSAT) depth K=0 took 43 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-03(UNSAT) depth K=0 took 51 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 404 transitions.
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-08(UNSAT) depth K=0 took 19 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-09(UNSAT) depth K=0 took 11 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-12(UNSAT) depth K=0 took 8 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-13(UNSAT) depth K=0 took 19 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-15(UNSAT) depth K=0 took 11 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 2 place invariants in 284 ms
May 20, 2018 10:55:51 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 2 place invariants in 169 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-00(UNSAT) depth K=1 took 606 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-03(UNSAT) depth K=1 took 540 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-08(UNSAT) depth K=1 took 29 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-09(UNSAT) depth K=1 took 29 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-12(UNSAT) depth K=1 took 27 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-13(UNSAT) depth K=1 took 28 ms
May 20, 2018 10:55:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property BART-PT-002-ReachabilityCardinality-15(UNSAT) depth K=1 took 56 ms
May 20, 2018 10:55:53 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 264 variables to be positive in 2316 ms
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 264 variables to be positive in 3080 ms
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 404 transitions.
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/404 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 93 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 404 transitions.
May 20, 2018 10:55:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 14 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeAblingForPredicate(NecessaryEnablingsolver.java:766)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:502)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying BART-PT-002-ReachabilityCardinality-00 SMT depth 2
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying BART-PT-002-ReachabilityCardinality-00 K-induction depth 0
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 2
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 2
May 20, 2018 10:56:07 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 7 properties. Interrupting other analysis methods.
May 20, 2018 10:56:07 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 17404ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-002"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-002.tgz
mv BART-PT-002 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BART-PT-002, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r032-ebro-152646309900061"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;