fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r021-qhx1-152646246300125
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for AutoFlight-PT-06a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15756.160 16867.00 14875.00 2123.20 T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................................................
/home/mcc/execution
total 204K
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 346 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 43K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is AutoFlight-PT-06a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r021-qhx1-152646246300125
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-06a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527228911045

Flatten gal took : 142 ms
Constant places removed 1 places and 1 transitions.
Reduce isomorphic transitions removed 30 transitions.
Performed 30 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 156 transition count 94
Constant places removed 42 places and 0 transitions.
Performed 30 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 72 rules applied. Total rules applied 133 place count 114 transition count 64
Constant places removed 30 places and 0 transitions.
Iterating post reduction 2 with 30 rules applied. Total rules applied 163 place count 84 transition count 64
Performed 6 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 163 place count 84 transition count 58
Constant places removed 12 places and 0 transitions.
Performed 6 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 18 rules applied. Total rules applied 181 place count 72 transition count 52
Constant places removed 6 places and 0 transitions.
Iterating post reduction 4 with 6 rules applied. Total rules applied 187 place count 66 transition count 52
Applied a total of 187 rules in 56 ms. Remains 66 /157 variables (removed 91) and now considering 52/155 (removed 103) transitions.
// Phase 1: matrix 52 rows 66 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 32 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,135168,0.05846,4928,48,21,406,182,148,397,44,332,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,12,0.063859,4928,46,15,489,198,386,457,153,392,944

System contains 12 deadlocks (shown below if less than --print-limit option) !
FORMULA AutoFlight-PT-06a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 12 states ] showing 10 first states
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
[ u38={[ p150=1 ]
[ p151=1 ]
} u37={[ p148=1 ]
} u17={[ p39=1 ]
} u14={[ p32=1 ]
} u16={[ p36=1 ]
} u36={[ p142=1 ]
} u13={[ p29=1 ]
} u11={[ p25=1 ]
} u39={[ p156=1 ]
} u10={[ p22=1 ]
} u32={[ p118=1 ]
} u35={[ p136=1 ]
} u8={[ p18=1 ]
} u31={[ p92=1 ]
} u7={[ p15=1 ]
} u5={[ p11=1 ]
} u34={[ p130=1 ]
} u4={[ p8=1 ]
} u2={[ p4=1 ]
} u33={[ p124=1 ]
} u1={[ p1=1 ]
} ]
[ u38={[ p154=1 ]
} u37={[ p144=1 ]
[ p145=1 ]
} u17={[ p39=1 ]
} u14={[ p32=1 ]
} u16={[ p36=1 ]
} u36={[ p142=1 ]
} u13={[ p29=1 ]
} u11={[ p25=1 ]
} u39={[ p156=1 ]
} u10={[ p22=1 ]
} u32={[ p118=1 ]
} u35={[ p136=1 ]
} u8={[ p18=1 ]
} u31={[ p92=1 ]
} u7={[ p15=1 ]
} u5={[ p11=1 ]
} u34={[ p130=1 ]
} u4={[ p8=1 ]
} u2={[ p4=1 ]
} u33={[ p124=1 ]
} u1={[ p1=1 ]
} ]
[ u38={[ p154=1 ]
} u37={[ p148=1 ]
} u17={[ p39=1 ]
} u14={[ p32=1 ]
} u16={[ p36=1 ]
} u36={[ p138=1 ]
[ p139=1 ]
} u13={[ p29=1 ]
} u11={[ p25=1 ]
} u39={[ p156=1 ]
} u10={[ p22=1 ]
} u32={[ p118=1 ]
} u35={[ p136=1 ]
} u8={[ p18=1 ]
} u31={[ p92=1 ]
} u7={[ p15=1 ]
} u5={[ p11=1 ]
} u34={[ p130=1 ]
} u4={[ p8=1 ]
} u2={[ p4=1 ]
} u33={[ p124=1 ]
} u1={[ p1=1 ]
} ]
[ u38={[ p154=1 ]
} u37={[ p148=1 ]
} u17={[ p39=1 ]
} u14={[ p32=1 ]
} u16={[ p36=1 ]
} u36={[ p142=1 ]
} u13={[ p29=1 ]
} u11={[ p25=1 ]
} u39={[ p156=1 ]
} u10={[ p22=1 ]
} u32={[ p118=1 ]
} u35={[ p132=1 ]
[ p133=1 ]
} u8={[ p18=1 ]
} u31={[ p92=1 ]
} u7={[ p15=1 ]
} u5={[ p11=1 ]
} u34={[ p130=1 ]
} u4={[ p8=1 ]
} u2={[ p4=1 ]
} u33={[ p124=1 ]
} u1={[ p1=1 ]
} ]
[ u38={[ p154=1 ]
} u37={[ p148=1 ]
} u17={[ p39=1 ]
} u14={[ p32=1 ]
} u16={[ p36=1 ]
} u36={[ p142=1 ]
} u13={[ p29=1 ]
} u11={[ p25=1 ]
} u39={[ p156=1 ]
} u10={[ p22=1 ]
} u32={[ p118=1 ]
} u35={[ p136=1 ]
} u8={[ p18=1 ]
} u31={[ p92=1 ]
} u7={[ p15=1 ]
} u5={[ p11=1 ]
} u34={[ p126=1 ]
[ p127=1 ]
} u4={[ p8=1 ]
} u2={[ p4=1 ]
} u33={[ p124=1 ]
} u1={[ p1=1 ]
} ]
// Phase 1: matrix 52 rows 66 cols
invariant :p25 + p27 = 1
invariant :p149 + p150 + p151 + p154 = 1
invariant :p39 + p41 = 1
invariant :p1 + p3 = 1
invariant :p4 + p6 = 1
invariant :p8 + p10 = 1
invariant :p29 + p31 = 1
invariant :p143 + p144 + p145 + p148 = 1
invariant :p11 + p13 = 1
invariant :p155 + p156 = 1
invariant :p15 + p17 = 1
invariant :p32 + p34 = 1
invariant :p92 + p118 + p124 + p130 + p136 + p142 + p148 + p154 + p156 = 8
invariant :p131 + p132 + p133 + p136 = 1
invariant :p18 + p20 = 1
invariant :p125 + p126 + p127 + p130 = 1
invariant :p93 + p112 + p113 + p114 + p115 + p116 + p117 + p118 = 1
invariant :p61 + p86 + p87 + p88 + p89 + p90 + p91 + -1'p118 + -1'p124 + -1'p130 + -1'p136 + -1'p142 + -1'p148 + -1'p154 + -1'p156 = -7
invariant :p22 + p24 = 1
invariant :p36 + p38 = 1
invariant :p137 + p138 + p139 + p142 = 1
invariant :p119 + p120 + p121 + p124 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527228927912

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 6:15:24 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 6:15:24 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 6:15:25 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 166 ms
May 25, 2018 6:15:25 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 157 places.
May 25, 2018 6:15:25 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 155 transitions.
May 25, 2018 6:15:25 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 25, 2018 6:15:25 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 23 ms
May 25, 2018 6:15:25 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 135 ms
May 25, 2018 6:15:25 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 6 ms
May 25, 2018 6:15:25 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 155 transitions.
May 25, 2018 6:15:26 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 25 ms
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 26 ms
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 36 ms
May 25, 2018 6:15:26 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 52 transitions.
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 25, 2018 6:15:26 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 14 redundant transitions.
May 25, 2018 6:15:26 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 3 ms
May 25, 2018 6:15:26 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 22 place invariants in 24 ms
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 6:15:26 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 318ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-06a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-06a.tgz
mv AutoFlight-PT-06a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is AutoFlight-PT-06a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r021-qhx1-152646246300125"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;