fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r020-qhx1-152646244500167
Last Updated
June 26, 2018

About the Execution of ITS-Tools for AutoFlight-PT-48a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15757.650 88699.00 183612.00 2019.30 T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......................
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.1K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 346 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 309K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is AutoFlight-PT-48a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r020-qhx1-152646244500167
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-48a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1526868787048

Flatten gal took : 622 ms
Constant places removed 1 places and 1 transitions.
Reduce isomorphic transitions removed 192 transitions.
Performed 312 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 505 rules applied. Total rules applied 505 place count 1126 transition count 608
Constant places removed 396 places and 0 transitions.
Performed 192 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 588 rules applied. Total rules applied 1093 place count 730 transition count 416
Constant places removed 192 places and 0 transitions.
Iterating post reduction 2 with 192 rules applied. Total rules applied 1285 place count 538 transition count 416
Performed 48 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 3 with 48 Pre rules applied. Total rules applied 1285 place count 538 transition count 368
Constant places removed 96 places and 0 transitions.
Performed 48 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 144 rules applied. Total rules applied 1429 place count 442 transition count 320
Constant places removed 48 places and 0 transitions.
Iterating post reduction 4 with 48 rules applied. Total rules applied 1477 place count 394 transition count 320
Applied a total of 1477 rules in 412 ms. Remains 394 /1127 variables (removed 733) and now considering 320/1113 (removed 793) transitions.
// Phase 1: matrix 320 rows 394 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 320 rows 394 cols
invariant :p74 + p76 = 1
invariant :p228 + p230 = 1
invariant :p867 + p868 + p869 + p872 = 1
invariant :p60 + p62 = 1
invariant :p909 + p910 + p911 + p914 = 1
invariant :p1101 + p1102 + p1103 + p1106 = 1
invariant :p106 + p108 = 1
invariant :p1035 + p1040 = 1
invariant :p939 + p940 + p941 + p944 = 1
invariant :p945 + p946 + p947 + p950 = 1
invariant :p15 + p17 = 1
invariant :p88 + p90 = 1
invariant :p951 + p952 + p953 + p956 = 1
invariant :p933 + p934 + p935 + p938 = 1
invariant :p1047 + p1052 = 1
invariant :p1119 + p1120 + p1121 + p1124 = 1
invariant :p134 + p136 = 1
invariant :p137 + p139 = 1
invariant :p987 + p992 = 1
invariant :p957 + p958 + p959 + p962 = 1
invariant :p981 + p986 = 1
invariant :p232 + p234 = 1
invariant :p36 + p38 = 1
invariant :p109 + p111 = 1
invariant :p1029 + p1034 = 1
invariant :p927 + p928 + p929 + p932 = 1
invariant :p50 + p52 = 1
invariant :p873 + p874 + p875 + p878 = 1
invariant :p144 + p146 = 1
invariant :p249 + p251 = 1
invariant :p92 + p94 = 1
invariant :p225 + p227 = 1
invariant :p39 + p41 = 1
invariant :p221 + p223 = 1
invariant :p1041 + p1046 = 1
invariant :p1107 + p1108 + p1109 + p1112 = 1
invariant :p18 + p20 = 1
invariant :p8 + p10 = 1
invariant :p891 + p892 + p893 + p896 = 1
invariant :p64 + p66 = 1
invariant :p1 + p3 = 1
invariant :p78 + p80 = 1
invariant :p214 + p216 = 1
invariant :p963 + p964 + p965 + p968 = 1
invariant :p29 + p31 = 1
invariant :p903 + p904 + p905 + p908 = 1
invariant :p999 + p1004 = 1
invariant :p116 + p118 = 1
invariant :p993 + p998 = 1
invariant :p1071 + p1072 + p1073 + p1076 = 1
invariant :p1077 + p1078 + p1079 + p1082 = 1
invariant :p921 + p922 + p923 + p926 = 1
invariant :p95 + p97 = 1
invariant :p519 + p628 + p629 + p630 + p631 + p632 + p633 + p634 + p635 + p636 + p637 + p638 + p639 + p640 = 1
invariant :p113 + p115 = 1
invariant :p141 + p143 = 1
invariant :p1083 + p1084 + p1085 + p1088 = 1
invariant :p1065 + p1066 + p1067 + p1070 = 1
invariant :p67 + p69 = 1
invariant :p207 + p209 = 1
invariant :p81 + p83 = 1
invariant :p148 + p150 = 1
invariant :p879 + p880 + p881 + p884 = 1
invariant :p11 + p13 = 1
invariant :p53 + p55 = 1
invariant :p218 + p220 = 1
invariant :p1089 + p1090 + p1091 + p1094 = 1
invariant :p151 + p153 = 1
invariant :p518 + p640 + p738 + p836 + p842 + p848 + p854 + p860 + p866 + p872 + p878 + p884 + p890 + p896 + p902 + p908 + p914 + p920 + p926 + p932 + p938 + p944 + p950 + p956 + p962 + p968 + p974 + p980 + p986 + p992 + p998 + p1004 + p1010 + p1016 + p1022 + p1028 + p1034 + p1040 + p1046 + p1052 + p1058 + p1064 + p1070 + p1076 + p1082 + p1088 + p1094 + p1100 + p1106 + p1112 + p1118 + p1124 + p1126 = 52
invariant :p1059 + p1060 + p1061 + p1064 = 1
invariant :p99 + p101 = 1
invariant :p969 + p970 + p971 + p974 = 1
invariant :p165 + p167 = 1
invariant :p123 + p125 = 1
invariant :p120 + p122 = 1
invariant :p843 + p844 + p845 + p848 = 1
invariant :p849 + p850 + p851 + p854 = 1
invariant :p155 + p157 = 1
invariant :p200 + p202 = 1
invariant :p1005 + p1010 = 1
invariant :p1011 + p1016 = 1
invariant :p32 + p34 = 1
invariant :p1113 + p1114 + p1115 + p1118 = 1
invariant :p211 + p213 = 1
invariant :p915 + p916 + p917 + p920 = 1
invariant :p855 + p856 + p857 + p860 = 1
invariant :p242 + p244 = 1
invariant :p837 + p838 + p839 + p842 = 1
invariant :p1125 + p1126 = 1
invariant :p158 + p160 = 1
invariant :p246 + p248 = 1
invariant :p197 + p199 = 1
invariant :p641 + p714 + p715 + p716 + p717 + p718 + p719 + p720 + p721 + p722 + p723 + p724 + p725 + p726 + p727 + p728 + p729 + p730 + p731 + p732 + p733 + p734 + p735 + p736 + p737 + p738 = 1
invariant :p397 + p494 + p495 + p496 + p497 + p498 + p499 + p500 + p501 + p502 + p503 + p504 + p505 + p506 + p507 + p508 + p509 + p510 + p511 + p512 + p513 + p514 + p515 + p516 + p517 + -1'p640 + -1'p738 + -1'p836 + -1'p842 + -1'p848 + -1'p854 + -1'p860 + -1'p866 + -1'p872 + -1'p878 + -1'p884 + -1'p890 + -1'p896 + -1'p902 + -1'p908 + -1'p914 + -1'p920 + -1'p926 + -1'p932 + -1'p938 + -1'p944 + -1'p950 + -1'p956 + -1'p962 + -1'p968 + -1'p974 + -1'p980 + -1'p986 + -1'p992 + -1'p998 + -1'p1004 + -1'p1010 + -1'p1016 + -1'p1022 + -1'p1028 + -1'p1034 + -1'p1040 + -1'p1046 + -1'p1052 + -1'p1058 + -1'p1064 + -1'p1070 + -1'p1076 + -1'p1082 + -1'p1088 + -1'p1094 + -1'p1100 + -1'p1106 + -1'p1112 + -1'p1118 + -1'p1124 + -1'p1126 = -51
invariant :p1095 + p1096 + p1097 + p1100 = 1
invariant :p162 + p164 = 1
invariant :p179 + p181 = 1
invariant :p186 + p188 = 1
invariant :p739 + p824 + p825 + p826 + p827 + p828 + p829 + p830 + p831 + p832 + p833 + p834 + p835 + p836 = 1
invariant :p102 + p104 = 1
invariant :p1053 + p1054 + p1055 + p1058 = 1
invariant :p861 + p862 + p863 + p866 = 1
invariant :p172 + p174 = 1
invariant :p204 + p206 = 1
invariant :p43 + p45 = 1
invariant :p193 + p195 = 1
invariant :p897 + p898 + p899 + p902 = 1
invariant :p22 + p24 = 1
invariant :p4 + p6 = 1
invariant :p71 + p73 = 1
invariant :p25 + p27 = 1
invariant :p127 + p129 = 1
invariant :p130 + p132 = 1
invariant :p46 + p48 = 1
invariant :p57 + p59 = 1
invariant :p885 + p886 + p887 + p890 = 1
invariant :p183 + p185 = 1
invariant :p1017 + p1022 = 1
invariant :p176 + p178 = 1
invariant :p85 + p87 = 1
invariant :p975 + p976 + p977 + p980 = 1
invariant :p1023 + p1028 = 1
invariant :p190 + p192 = 1
invariant :p235 + p237 = 1
invariant :p239 + p241 = 1
invariant :p169 + p171 = 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,9.30306e+23,14.3611,135580,2,76038,5,478757,6,0,1899,474481,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,72,76.4203,629612,2,3232,7,3.50108e+06,9,1,8322,474481,2

System contains 72 deadlocks (shown below if less than --print-limit option) !
FORMULA AutoFlight-PT-48a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 72 states ] showing 10 first states
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p968=1 p962=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p838=1 p151=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p968=1 p962=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p839=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p962=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p964=1 p151=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p962=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p965=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p4=1 p148=1 p1=1 p958=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p848=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p959=1 p151=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p962=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p4=1 p148=1 p1=1 p844=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p962=1 p956=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p845=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p962=1 p848=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p4=1 p148=1 p1=1 p952=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
[ p235=1 p232=1 p228=1 p225=1 p221=1 p242=1 p239=1 p218=1 p214=1 p211=1 p207=1 p179=1 p186=1 p249=1 p246=1 p176=1 p204=1 p200=1 p193=1 p183=1 p172=1 p169=1 p190=1 p197=1 p165=1 p162=1 p1112=1 p1106=1 p1118=1 p158=1 p836=1 p1100=1 p640=1 p1094=1 p1124=1 p1064=1 p1088=1 p1070=1 p1058=1 p1082=1 p980=1 p1076=1 p1052=1 p1046=1 p1040=1 p1034=1 p1028=1 p1022=1 p1016=1 p1010=1 p1004=1 p738=1 p998=1 p992=1 p518=1 p986=1 p1126=1 p974=1 p155=1 p842=1 p968=1 p962=1 p848=1 p950=1 p944=1 p938=1 p932=1 p854=1 p926=1 p920=1 p914=1 p908=1 p902=1 p860=1 p896=1 p890=1 p884=1 p866=1 p878=1 p872=1 p151=1 p953=1 p4=1 p148=1 p1=1 p144=1 p141=1 p11=1 p8=1 p137=1 p134=1 p130=1 p127=1 p123=1 p120=1 p116=1 p109=1 p113=1 p18=1 p102=1 p15=1 p106=1 p95=1 p99=1 p88=1 p92=1 p81=1 p85=1 p25=1 p74=1 p78=1 p22=1 p67=1 p71=1 p60=1 p64=1 p57=1 p53=1 p32=1 p46=1 p29=1 p50=1 p39=1 p43=1 p36=1 ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526868875747

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 21, 2018 2:13:13 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 21, 2018 2:13:13 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 21, 2018 2:13:14 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 191 ms
May 21, 2018 2:13:14 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1127 places.
May 21, 2018 2:13:14 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1113 transitions.
May 21, 2018 2:13:14 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 21, 2018 2:13:14 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 62 ms
May 21, 2018 2:13:15 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 612 ms
May 21, 2018 2:13:15 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 20 ms
May 21, 2018 2:13:15 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1113 transitions.
May 21, 2018 2:13:16 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 6 ms
May 21, 2018 2:13:17 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 320 transitions.
May 21, 2018 2:13:17 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 126 place invariants in 126 ms
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 394 variables to be positive in 1080 ms
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 320 transitions.
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/320 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 42 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 320 transitions.
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 10 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 2:13:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 320 transitions.
May 21, 2018 2:13:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(85/320) took 2995 ms. Total solver calls (SAT/UNSAT): 417(72/345)
May 21, 2018 2:13:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(103/320) took 6044 ms. Total solver calls (SAT/UNSAT): 1596(1170/426)
May 21, 2018 2:13:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(113/320) took 9115 ms. Total solver calls (SAT/UNSAT): 2731(2295/436)
May 21, 2018 2:13:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(117/320) took 12560 ms. Total solver calls (SAT/UNSAT): 3157(2717/440)
May 21, 2018 2:13:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(142/320) took 16630 ms. Total solver calls (SAT/UNSAT): 3670(2870/800)
May 21, 2018 2:13:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(145/320) took 19655 ms. Total solver calls (SAT/UNSAT): 3976(3014/962)
May 21, 2018 2:13:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/320) took 25335 ms. Total solver calls (SAT/UNSAT): 4171(3105/1066)
May 21, 2018 2:13:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(149/320) took 29493 ms. Total solver calls (SAT/UNSAT): 4362(3192/1170)
May 21, 2018 2:13:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(151/320) took 34812 ms. Total solver calls (SAT/UNSAT): 4549(3275/1274)
May 21, 2018 2:13:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(155/320) took 38002 ms. Total solver calls (SAT/UNSAT): 4919(3429/1490)
May 21, 2018 2:13:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(160/320) took 41141 ms. Total solver calls (SAT/UNSAT): 5359(3599/1760)
May 21, 2018 2:14:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(164/320) took 45138 ms. Total solver calls (SAT/UNSAT): 5692(3717/1975)
May 21, 2018 2:14:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(166/320) took 48309 ms. Total solver calls (SAT/UNSAT): 5850(3769/2081)
May 21, 2018 2:14:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(169/320) took 51537 ms. Total solver calls (SAT/UNSAT): 6083(3841/2242)
May 21, 2018 2:14:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(173/320) took 54546 ms. Total solver calls (SAT/UNSAT): 6381(3923/2458)
May 21, 2018 2:14:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(182/320) took 58081 ms. Total solver calls (SAT/UNSAT): 6987(4049/2938)
May 21, 2018 2:14:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(192/320) took 61878 ms. Total solver calls (SAT/UNSAT): 7565(4146/3419)
May 21, 2018 2:14:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(195/320) took 66089 ms. Total solver calls (SAT/UNSAT): 7716(4295/3421)
May 21, 2018 2:14:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(273/320) took 70025 ms. Total solver calls (SAT/UNSAT): 7969(4436/3533)
May 21, 2018 2:14:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(276/320) took 73657 ms. Total solver calls (SAT/UNSAT): 8101(4568/3533)
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:480)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 21, 2018 2:14:34 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 77437ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-48a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-48a.tgz
mv AutoFlight-PT-48a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is AutoFlight-PT-48a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r020-qhx1-152646244500167"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;