fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r009-qhx2-152646139300002
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for ARMCacheCoherence-PT-none

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15749.890 98785.00 163554.00 643.20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..........................
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 5 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 14M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ARMCacheCoherence-PT-none, examination is UpperBounds
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r009-qhx2-152646139300002
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of positive values
NUM_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-00
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-01
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-02
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-03
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-04
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-05
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-06
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-07
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-08
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-09
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-10
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-11
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-12
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-13
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-14
FORMULA_NAME ARMCacheCoherence-PT-none-UpperBounds-15

=== Now, execution of the tool begins

BK_START 1527749722719

Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/UpperBounds.pnml.gal, -t, CGAL, -reachable-file, UpperBounds.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/UpperBounds.pnml.gal -t CGAL -reachable-file UpperBounds.prop --nowitness
Loading property file UpperBounds.prop.
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-00 with value :u6.p50
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-01 with value :u6.p52
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-02 with value :u10.p78
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-03 with value :u4.p13
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-04 with value :u7.p68
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-05 with value :u12.p83
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-06 with value :u5.p27
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-07 with value :u10.p75
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-08 with value :u6.p52
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-09 with value :u11.p80
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-10 with value :u9.p74
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-11 with value :u11.p82
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-12 with value :u1.p3
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-13 with value :u5.p34
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-14 with value :u11.p79
Read [bounds] property : ARMCacheCoherence-PT-none-UpperBounds-15 with value :u1.p2
built 50 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence\_PT\_none\_flat\_flat\_flat\_mod,3.20568e+08,44.024,100128,65,60,2811,1610,1379,5134,100,10368,0
Total reachable state count : 320567601

Verifying 16 reachability properties.
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-00 :0 <= u6.p50 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-00 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-00,0,44.0282,100160,1,0,2811,1610,1467,5134,126,10368,188
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-01 :0 <= u6.p52 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-01 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-01,0,44.0286,100224,1,0,2811,1610,1490,5134,139,10368,203
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-02 :0 <= u10.p78 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-02 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-02,0,44.029,100224,1,0,2811,1610,1518,5134,146,10368,227
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-03 :0 <= u4.p13 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-03 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-03,0,44.0296,100224,1,0,2811,1610,1539,5134,178,10368,254
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-04 :0 <= u7.p68 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-04 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-04,0,44.03,100224,1,0,2811,1610,1566,5134,183,10368,275
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-05 :0 <= u12.p83 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-05 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-05,0,44.0303,100224,1,0,2811,1610,1593,5134,183,10368,290
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-06 :0 <= u5.p27 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-06 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-06,0,44.0318,100224,1,0,2811,1610,1613,5134,200,10368,311
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-07 :0 <= u10.p75 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-07 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-07,0,44.0328,100224,1,0,2811,1610,1631,5134,200,10368,333
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-08 :0 <= u6.p52 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-08 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-08,0,44.0332,100224,1,0,2811,1610,1631,5134,200,10368,333
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-09 :0 <= u11.p80 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-09 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-09,0,44.0338,100224,1,0,2811,1610,1652,5134,209,10368,352
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-10 :0 <= u9.p74 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-10 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-10,0,44.0342,100224,1,0,2811,1610,1680,5134,209,10368,368
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-11 :0 <= u11.p82 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-11 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-11,0,44.0345,100224,1,0,2811,1610,1700,5134,209,10368,385
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-12 :0 <= u1.p3 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-12 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-12,0,44.035,100224,1,0,2811,1610,1718,5134,211,10368,410
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-13 :0 <= u5.p34 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-13 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-13,0,44.0356,100224,1,0,2811,1610,1738,5134,233,10368,431
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-14 :0 <= u11.p79 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-14 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-14,0,44.036,100224,1,0,2811,1610,1758,5134,233,10368,448
Min sum of variable value : 0
Maximum sum along a path : 1
Bounds property ARMCacheCoherence-PT-none-UpperBounds-15 :0 <= u1.p2 <= 1
FORMULA ARMCacheCoherence-PT-none-UpperBounds-15 1 TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-UpperBounds-15,0,44.0364,100224,1,0,2811,1610,1776,5134,233,10368,473

BK_STOP 1527749821504

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution UpperBounds -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination UpperBounds -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 6:55:26 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, UpperBounds, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 6:55:26 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 6:55:28 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 1901 ms
May 31, 2018 6:55:28 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 87 places.
May 31, 2018 6:55:30 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33676 transitions.
May 31, 2018 6:55:30 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 6:55:30 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 6:55:40 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 10462 ms
May 31, 2018 6:55:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 11015 ms
May 31, 2018 6:55:53 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 6:56:01 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 8300 ms
May 31, 2018 6:56:02 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 6:56:15 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 123217 redundant transitions.
May 31, 2018 6:56:15 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/UpperBounds.pnml.gal : 268 ms
May 31, 2018 6:56:16 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/UpperBounds.prop : 1 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="UpperBounds"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ARMCacheCoherence-PT-none, examination is UpperBounds"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r009-qhx2-152646139300002"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "UpperBounds" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "UpperBounds" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "UpperBounds.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property UpperBounds.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "UpperBounds.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' UpperBounds.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;