Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.............................................................................................................
/home/mcc/execution
total 268K
-rw-r--r-- 1 mcc users 3.1K May 30 21:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 30 21:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 29 15:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 13K May 29 15:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.1K May 28 09:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.1K May 28 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.7K May 28 06:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 28 06:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 348 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 27 03:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 27 03:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 104K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DiscoveryGPU-PT-14b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r285-csrt-152749175900159
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-00
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-01
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-02
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-03
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-04
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-05
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-06
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-07
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-08
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-09
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-10
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-11
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-12
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-13
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-14
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527986444071

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(F(F(X("((i0.i0.i0.i0.u24.p299>=1)&&(i1.u29.p399>=1))"))))))
Formula 0 simplified : !XFX"((i0.i0.i0.i0.u24.p299>=1)&&(i1.u29.p399>=1))"
built 4 ordering constraints for composite.
built 140 ordering constraints for composite.
built 130 ordering constraints for composite.
built 120 ordering constraints for composite.
built 110 ordering constraints for composite.
built 100 ordering constraints for composite.
built 90 ordering constraints for composite.
built 80 ordering constraints for composite.
built 70 ordering constraints for composite.
built 60 ordering constraints for composite.
built 50 ordering constraints for composite.
built 40 ordering constraints for composite.
built 30 ordering constraints for composite.
built 20 ordering constraints for composite.
built 128 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 434 rows 408 cols
invariant :u35:p0 + i1:u30:p402 + i1:u30:p403 + i1:u30:p404 + i1:u30:p405 + i1:u30:p406 + i1:u30:p407 + i1:u45:p392 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u21:p203 + i0:i0:i0:i0:i0:i0:i0:u21:p204 + i0:i0:i0:i0:i0:i0:i0:u21:p205 + i0:i0:i0:i0:i0:i0:i0:u21:p206 + i0:i0:i0:i0:i0:i0:i0:u21:p207 + i0:i0:i0:i0:i0:i0:i0:u21:p208 + i0:i0:i0:i0:i0:i0:i0:u21:p209 + i0:i0:i0:i0:i0:i0:i0:u21:p210 + i0:i0:i0:i0:i0:i0:i0:u21:p211 + i0:i0:i0:i0:i0:i0:i0:u21:p212 + i0:i0:i0:i0:i0:i0:i0:u21:p213 + i0:i0:i0:i0:i0:i0:i0:u21:p214 + i0:i0:i0:i0:i0:i0:i0:u21:p215 + i0:i0:i0:i0:i0:i0:i0:u21:p216 + i0:i0:i0:i0:i0:i0:i0:u21:p217 + i0:i0:i0:i0:i0:i0:i0:u21:p218 + i0:i0:i0:i0:i0:i0:i0:u21:p219 + i0:i0:i0:i0:i0:i0:i0:u21:p220 + i0:i0:i0:i0:i0:i0:i0:u21:p221 + i0:i0:i0:i0:i0:i0:i0:u21:p222 + i0:i0:i0:i0:i0:i0:i0:u21:p223 + i0:i0:i0:i0:i0:i0:i0:u21:p224 + i0:i0:i0:i0:i0:i0:i0:u21:p225 + i0:i0:i0:i0:i0:i0:i0:u21:p226 + i0:i0:i0:i0:i0:i0:i0:u21:p227 + i0:i0:i0:i0:i0:i0:i0:u21:p228 + i0:i0:i0:i0:i0:i0:i0:u21:p229 + i0:i0:i0:i0:i0:i0:i0:u42:p7 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u25:p311 + i0:i0:i0:u25:p312 + i0:i0:i0:u25:p313 + i0:i0:i0:u25:p314 + i0:i0:i0:u25:p315 + i0:i0:i0:u25:p316 + i0:i0:i0:u25:p317 + i0:i0:i0:u25:p318 + i0:i0:i0:u25:p319 + i0:i0:i0:u25:p320 + i0:i0:i0:u25:p321 + i0:i0:i0:u25:p322 + i0:i0:i0:u25:p323 + i0:i0:i0:u25:p324 + i0:i0:i0:u25:p325 + i0:i0:i0:u25:p326 + i0:i0:i0:u25:p327 + i0:i0:i0:u25:p328 + i0:i0:i0:u25:p329 + i0:i0:i0:u25:p330 + i0:i0:i0:u25:p331 + i0:i0:i0:u25:p332 + i0:i0:i0:u25:p333 + i0:i0:i0:u25:p334 + i0:i0:i0:u25:p335 + i0:i0:i0:u25:p336 + i0:i0:i0:u25:p337 + i0:i0:i0:u38:p3 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u32:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u31:p11 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u34:p12 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p14 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p15 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p16 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p17 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p18 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p19 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p20 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p21 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p22 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p23 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p24 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p25 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p26 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p27 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p28 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p29 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p30 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p31 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p32 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p33 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p34 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p35 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p36 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p37 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p38 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p39 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u14:p40 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u33:p13 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u22:p230 + i0:i0:i0:i0:i0:i0:u22:p231 + i0:i0:i0:i0:i0:i0:u22:p232 + i0:i0:i0:i0:i0:i0:u22:p233 + i0:i0:i0:i0:i0:i0:u22:p234 + i0:i0:i0:i0:i0:i0:u22:p235 + i0:i0:i0:i0:i0:i0:u22:p236 + i0:i0:i0:i0:i0:i0:u22:p237 + i0:i0:i0:i0:i0:i0:u22:p238 + i0:i0:i0:i0:i0:i0:u22:p239 + i0:i0:i0:i0:i0:i0:u22:p240 + i0:i0:i0:i0:i0:i0:u22:p241 + i0:i0:i0:i0:i0:i0:u22:p242 + i0:i0:i0:i0:i0:i0:u22:p243 + i0:i0:i0:i0:i0:i0:u22:p244 + i0:i0:i0:i0:i0:i0:u22:p245 + i0:i0:i0:i0:i0:i0:u22:p246 + i0:i0:i0:i0:i0:i0:u22:p247 + i0:i0:i0:i0:i0:i0:u22:p248 + i0:i0:i0:i0:i0:i0:u22:p249 + i0:i0:i0:i0:i0:i0:u22:p250 + i0:i0:i0:i0:i0:i0:u22:p251 + i0:i0:i0:i0:i0:i0:u22:p252 + i0:i0:i0:i0:i0:i0:u22:p253 + i0:i0:i0:i0:i0:i0:u22:p254 + i0:i0:i0:i0:i0:i0:u22:p255 + i0:i0:i0:i0:i0:i0:u22:p256 + i0:i0:i0:i0:i0:i0:u41:p6 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u23:p257 + i0:i0:i0:i0:i0:u23:p258 + i0:i0:i0:i0:i0:u23:p259 + i0:i0:i0:i0:i0:u23:p260 + i0:i0:i0:i0:i0:u23:p261 + i0:i0:i0:i0:i0:u23:p262 + i0:i0:i0:i0:i0:u23:p263 + i0:i0:i0:i0:i0:u23:p264 + i0:i0:i0:i0:i0:u23:p265 + i0:i0:i0:i0:i0:u23:p266 + i0:i0:i0:i0:i0:u23:p267 + i0:i0:i0:i0:i0:u23:p268 + i0:i0:i0:i0:i0:u23:p269 + i0:i0:i0:i0:i0:u23:p270 + i0:i0:i0:i0:i0:u23:p271 + i0:i0:i0:i0:i0:u23:p272 + i0:i0:i0:i0:i0:u23:p273 + i0:i0:i0:i0:i0:u23:p274 + i0:i0:i0:i0:i0:u23:p275 + i0:i0:i0:i0:i0:u23:p276 + i0:i0:i0:i0:i0:u23:p277 + i0:i0:i0:i0:i0:u23:p278 + i0:i0:i0:i0:i0:u23:p279 + i0:i0:i0:i0:i0:u23:p280 + i0:i0:i0:i0:i0:u23:p281 + i0:i0:i0:i0:i0:u23:p282 + i0:i0:i0:i0:i0:u23:p283 + i0:i0:i0:i0:i0:u40:p5 = 1
invariant :u35:p0 + i1:u29:p393 + i1:u29:p394 + i1:u29:p395 + i1:u29:p396 + i1:u29:p397 + i1:u29:p398 + i1:u29:p399 + i1:u29:p400 + i1:u29:p401 + i1:u45:p392 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p176 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p177 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p178 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p179 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p180 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p181 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p182 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p183 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p184 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p185 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p186 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p187 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p188 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p189 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p190 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p191 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p192 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p193 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p194 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p195 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p196 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p197 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p198 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p199 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p200 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p201 + i0:i0:i0:i0:i0:i0:i0:i0:u20:p202 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u32:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u31:p11 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p68 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p69 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p70 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p71 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p72 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p73 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p74 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p75 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p76 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p77 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p78 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p79 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p80 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p81 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p82 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p83 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p84 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p85 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p86 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p87 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p88 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p89 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p90 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p91 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p92 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p93 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u16:p94 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u34:p12 = 1
invariant :u35:p0 + i0:u27:p365 + i0:u27:p366 + i0:u27:p367 + i0:u27:p368 + i0:u27:p369 + i0:u27:p370 + i0:u27:p371 + i0:u27:p372 + i0:u27:p373 + i0:u27:p374 + i0:u27:p375 + i0:u27:p376 + i0:u27:p377 + i0:u27:p378 + i0:u27:p379 + i0:u27:p380 + i0:u27:p381 + i0:u27:p382 + i0:u27:p383 + i0:u27:p384 + i0:u27:p385 + i0:u27:p386 + i0:u27:p387 + i0:u27:p388 + i0:u27:p389 + i0:u27:p390 + i0:u27:p391 + i0:u36:p1 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p149 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p150 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p151 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p152 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p153 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p154 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p155 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p156 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p157 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p158 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p159 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p160 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p161 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p162 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p163 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p164 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p165 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p166 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p167 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p168 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p169 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p170 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p171 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p172 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p173 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p174 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u19:p175 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u26:p338 + i0:i0:u26:p339 + i0:i0:u26:p340 + i0:i0:u26:p341 + i0:i0:u26:p342 + i0:i0:u26:p343 + i0:i0:u26:p344 + i0:i0:u26:p345 + i0:i0:u26:p346 + i0:i0:u26:p347 + i0:i0:u26:p348 + i0:i0:u26:p349 + i0:i0:u26:p350 + i0:i0:u26:p351 + i0:i0:u26:p352 + i0:i0:u26:p353 + i0:i0:u26:p354 + i0:i0:u26:p355 + i0:i0:u26:p356 + i0:i0:u26:p357 + i0:i0:u26:p358 + i0:i0:u26:p359 + i0:i0:u26:p360 + i0:i0:u26:p361 + i0:i0:u26:p362 + i0:i0:u26:p363 + i0:i0:u26:p364 + i0:i0:u37:p2 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u32:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p95 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p96 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p97 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p98 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p99 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p100 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p101 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p102 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p103 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p104 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p105 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p106 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p107 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p108 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p109 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p110 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p111 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p112 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p113 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p114 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p115 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p116 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p117 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p118 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p119 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p120 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u17:p121 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u31:p11 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u32:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u31:p11 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u34:p12 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p41 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p42 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p43 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p44 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p45 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p46 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p47 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p48 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p49 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p50 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p51 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p52 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p53 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p54 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p55 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p56 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p57 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p58 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p59 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p60 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p61 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p62 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p63 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p64 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p65 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p66 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u15:p67 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u33:p13 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u24:p284 + i0:i0:i0:i0:u24:p285 + i0:i0:i0:i0:u24:p286 + i0:i0:i0:i0:u24:p287 + i0:i0:i0:i0:u24:p288 + i0:i0:i0:i0:u24:p289 + i0:i0:i0:i0:u24:p290 + i0:i0:i0:i0:u24:p291 + i0:i0:i0:i0:u24:p292 + i0:i0:i0:i0:u24:p293 + i0:i0:i0:i0:u24:p294 + i0:i0:i0:i0:u24:p295 + i0:i0:i0:i0:u24:p296 + i0:i0:i0:i0:u24:p297 + i0:i0:i0:i0:u24:p298 + i0:i0:i0:i0:u24:p299 + i0:i0:i0:i0:u24:p300 + i0:i0:i0:i0:u24:p301 + i0:i0:i0:i0:u24:p302 + i0:i0:i0:i0:u24:p303 + i0:i0:i0:i0:u24:p304 + i0:i0:i0:i0:u24:p305 + i0:i0:i0:i0:u24:p306 + i0:i0:i0:i0:u24:p307 + i0:i0:i0:i0:u24:p308 + i0:i0:i0:i0:u24:p309 + i0:i0:i0:i0:u24:p310 + i0:i0:i0:i0:u39:p4 = 1
invariant :u35:p0 + i0:u36:p1 + i0:i0:u37:p2 + i0:i0:i0:u38:p3 + i0:i0:i0:i0:u39:p4 + i0:i0:i0:i0:i0:u40:p5 + i0:i0:i0:i0:i0:i0:u41:p6 + i0:i0:i0:i0:i0:i0:i0:u42:p7 + i0:i0:i0:i0:i0:i0:i0:i0:u43:p8 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u44:p9 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p122 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p123 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p124 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p125 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p126 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p127 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p128 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p129 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p130 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p131 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p132 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p133 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p134 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p135 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p136 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p137 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p138 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p139 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p140 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p141 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p142 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p143 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p144 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p145 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p146 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p147 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u18:p148 + i0:i0:i0:i0:i0:i0:i0:i0:i0:i0:u32:p10 = 1
Reverse transition relation is NOT exact ! Due to transitions i0.u27.t17, i0.u27.t23, i0.u27.t27, i0.u27.t29, i0.u27.t31, i0.u27.t33, i0.i0.u26.t36, i0.i0.u26.t42, i0.i0.u26.t46, i0.i0.u26.t48, i0.i0.u26.t50, i0.i0.u26.t52, i0.i0.i0.u25.t55, i0.i0.i0.u25.t61, i0.i0.i0.u25.t65, i0.i0.i0.u25.t67, i0.i0.i0.u25.t69, i0.i0.i0.u25.t71, i0.i0.i0.i0.u24.t74, i0.i0.i0.i0.u24.t80, i0.i0.i0.i0.u24.t84, i0.i0.i0.i0.u24.t86, i0.i0.i0.i0.u24.t88, i0.i0.i0.i0.u24.t90, i0.i0.i0.i0.i0.u23.t93, i0.i0.i0.i0.i0.u23.t99, i0.i0.i0.i0.i0.u23.t103, i0.i0.i0.i0.i0.u23.t105, i0.i0.i0.i0.i0.u23.t107, i0.i0.i0.i0.i0.u23.t109, i0.i0.i0.i0.i0.i0.u22.t112, i0.i0.i0.i0.i0.i0.u22.t118, i0.i0.i0.i0.i0.i0.u22.t122, i0.i0.i0.i0.i0.i0.u22.t124, i0.i0.i0.i0.i0.i0.u22.t126, i0.i0.i0.i0.i0.i0.u22.t128, i0.i0.i0.i0.i0.i0.i0.u21.t131, i0.i0.i0.i0.i0.i0.i0.u21.t137, i0.i0.i0.i0.i0.i0.i0.u21.t141, i0.i0.i0.i0.i0.i0.i0.u21.t143, i0.i0.i0.i0.i0.i0.i0.u21.t145, i0.i0.i0.i0.i0.i0.i0.u21.t147, i0.i0.i0.i0.i0.i0.i0.i0.u20.t150, i0.i0.i0.i0.i0.i0.i0.i0.u20.t156, i0.i0.i0.i0.i0.i0.i0.i0.u20.t160, i0.i0.i0.i0.i0.i0.i0.i0.u20.t162, i0.i0.i0.i0.i0.i0.i0.i0.u20.t164, i0.i0.i0.i0.i0.i0.i0.i0.u20.t166, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t169, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t175, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t179, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t181, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t183, i0.i0.i0.i0.i0.i0.i0.i0.i0.u19.t185, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t188, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t194, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t198, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t200, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t202, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u18.t204, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t207, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t213, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t217, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t219, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t221, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u17.t223, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t226, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t232, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t236, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t238, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t240, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u16.t242, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t263, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t269, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t273, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t275, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t277, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u14.t279, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t245, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t251, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t255, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t257, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t259, i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.i0.u15.t261, i1.u29.t9, i1.u29.t11, i1.u29.t12, i1.u29.t14, i1.u30.t3, i1.u30.t4, i1.u30.t6, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/343/91/434
Computing Next relation with stutter on 16384 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6361 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 77 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(<>(X((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 37 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 456 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>(X((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 38 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (((LTLAP4==true))U(X((LTLAP5==true))))U([](X([]((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 34 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]([]((LTLAP7==true))))U((X((LTLAP8==true)))U((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 45 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP10==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 475 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>([]([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 490 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 35 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(([](X((LTLAP13==true))))U(<>([]((LTLAP14==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 31 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP15==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 48 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 447 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP17==true)))U(<>((LTLAP18==true))))U(<>([](<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 455 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](((LTLAP19==true))U((LTLAP20==true))))U(<>(((LTLAP21==true))U((LTLAP22==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 451 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP23==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 447 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X([]((LTLAP16==true)))))U(X((LTLAP24==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 63 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527986618606

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 82 ms
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 408 places.
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 434 transitions.
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 03, 2018 12:40:46 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 34 ms
Jun 03, 2018 12:40:46 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 135 ms
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 100 ms
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 50 ms
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 03, 2018 12:40:47 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 121 redundant transitions.
Jun 03, 2018 12:40:47 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 12 ms
Jun 03, 2018 12:40:47 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Jun 03, 2018 12:40:48 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 434 transitions.
Jun 03, 2018 12:40:48 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 16 place invariants in 236 ms
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 408 variables to be positive in 6010 ms
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 434 transitions.
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/434 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 65 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 434 transitions.
Jun 03, 2018 12:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 35 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:41:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 434 transitions.
Jun 03, 2018 12:41:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/434) took 812 ms. Total solver calls (SAT/UNSAT): 433(0/433)
Jun 03, 2018 12:41:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/434) took 4634 ms. Total solver calls (SAT/UNSAT): 2868(0/2868)
Jun 03, 2018 12:41:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/434) took 7906 ms. Total solver calls (SAT/UNSAT): 3608(0/3608)
Jun 03, 2018 12:41:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/434) took 11154 ms. Total solver calls (SAT/UNSAT): 4083(222/3861)
Jun 03, 2018 12:41:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(31/434) took 14281 ms. Total solver calls (SAT/UNSAT): 4754(535/4219)
Jun 03, 2018 12:41:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(54/434) took 17294 ms. Total solver calls (SAT/UNSAT): 5766(818/4948)
Jun 03, 2018 12:41:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/434) took 22609 ms. Total solver calls (SAT/UNSAT): 6159(1051/5108)
Jun 03, 2018 12:41:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/434) took 27446 ms. Total solver calls (SAT/UNSAT): 6374(1201/5173)
Jun 03, 2018 12:41:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/434) took 32337 ms. Total solver calls (SAT/UNSAT): 6792(1489/5303)
Jun 03, 2018 12:41:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/434) took 35363 ms. Total solver calls (SAT/UNSAT): 6995(1627/5368)
Jun 03, 2018 12:41:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/434) took 38620 ms. Total solver calls (SAT/UNSAT): 7292(1827/5465)
Jun 03, 2018 12:41:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(72/434) took 43473 ms. Total solver calls (SAT/UNSAT): 7485(1955/5530)
Jun 03, 2018 12:41:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/434) took 47704 ms. Total solver calls (SAT/UNSAT): 7767(2139/5628)
Jun 03, 2018 12:41:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(78/434) took 51908 ms. Total solver calls (SAT/UNSAT): 8040(2315/5725)
Jun 03, 2018 12:42:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/434) took 56725 ms. Total solver calls (SAT/UNSAT): 8304(2481/5823)
Jun 03, 2018 12:42:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/434) took 62557 ms. Total solver calls (SAT/UNSAT): 8475(2587/5888)
Jun 03, 2018 12:42:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(85/434) took 66981 ms. Total solver calls (SAT/UNSAT): 8642(2691/5951)
Jun 03, 2018 12:42:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(87/434) took 71498 ms. Total solver calls (SAT/UNSAT): 8805(2793/6012)
Jun 03, 2018 12:42:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/434) took 75706 ms. Total solver calls (SAT/UNSAT): 8964(2891/6073)
Jun 03, 2018 12:42:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(97/434) took 79744 ms. Total solver calls (SAT/UNSAT): 9560(3243/6317)
Jun 03, 2018 12:42:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(102/434) took 83760 ms. Total solver calls (SAT/UNSAT): 9900(3431/6469)
Jun 03, 2018 12:42:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/434) took 87269 ms. Total solver calls (SAT/UNSAT): 10029(3499/6530)
Jun 03, 2018 12:42:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(106/434) took 91243 ms. Total solver calls (SAT/UNSAT): 10154(3563/6591)
Jun 03, 2018 12:42:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(108/434) took 94429 ms. Total solver calls (SAT/UNSAT): 10275(3623/6652)
Jun 03, 2018 12:42:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/434) took 97455 ms. Total solver calls (SAT/UNSAT): 10964(3933/7031)
Jun 03, 2018 12:42:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(134/434) took 100969 ms. Total solver calls (SAT/UNSAT): 11484(4083/7401)
Jun 03, 2018 12:42:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(164/434) took 103984 ms. Total solver calls (SAT/UNSAT): 11927(4100/7827)
Jun 03, 2018 12:42:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(191/434) took 107046 ms. Total solver calls (SAT/UNSAT): 12201(4107/8094)
Jun 03, 2018 12:42:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(226/434) took 110268 ms. Total solver calls (SAT/UNSAT): 12526(4113/8413)
Jun 03, 2018 12:43:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(242/434) took 113312 ms. Total solver calls (SAT/UNSAT): 12654(4115/8539)
Jun 03, 2018 12:43:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(254/434) took 116369 ms. Total solver calls (SAT/UNSAT): 12792(4119/8673)
Jun 03, 2018 12:43:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(284/434) took 119499 ms. Total solver calls (SAT/UNSAT): 13067(4124/8943)
Jun 03, 2018 12:43:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(305/434) took 122569 ms. Total solver calls (SAT/UNSAT): 13272(4129/9143)
Jun 03, 2018 12:43:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(341/434) took 125660 ms. Total solver calls (SAT/UNSAT): 13586(4135/9451)
Jun 03, 2018 12:43:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(380/434) took 128672 ms. Total solver calls (SAT/UNSAT): 13947(4143/9804)
Jun 03, 2018 12:43:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(388/434) took 131881 ms. Total solver calls (SAT/UNSAT): 14071(4145/9926)
Jun 03, 2018 12:43:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(403/434) took 135202 ms. Total solver calls (SAT/UNSAT): 14191(4148/10043)
Jun 03, 2018 12:43:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(410/434) took 138373 ms. Total solver calls (SAT/UNSAT): 14282(4150/10132)
Jun 03, 2018 12:43:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 140744 ms. Total solver calls (SAT/UNSAT): 14365(4151/10214)
Jun 03, 2018 12:43:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 434 transitions.
Jun 03, 2018 12:43:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 42 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:43:27 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 159935ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DiscoveryGPU-PT-14b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DiscoveryGPU-PT-14b.tgz
mv DiscoveryGPU-PT-14b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DiscoveryGPU-PT-14b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r285-csrt-152749175900159"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;