Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
........................
/home/mcc/execution
total 232K
-rw-r--r-- 1 mcc users 5.2K May 30 20:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 33K May 30 20:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 29 13:51 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 29 13:51 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 28 09:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.5K May 28 07:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.3K May 28 06:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 28 06:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 348 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 27 03:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 27 03:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 46K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DiscoveryGPU-PT-06b, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r285-csrt-152749175700014
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-00
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-01
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-02
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-03
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-04
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-05
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-06
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-07
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-08
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-09
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-10
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-11
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-12
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-13
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-14
FORMULA_NAME DiscoveryGPU-PT-06b-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1527985991508

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((("((i1.u16.p168==0)||(i0.i0.u10.p132==1))")U(F(F("(i0.u11.p160>=2)")))))
Formula 0 simplified : !("((i1.u16.p168==0)||(i0.i0.u10.p132==1))" U F"(i0.u11.p160>=2)")
built 4 ordering constraints for composite.
built 60 ordering constraints for composite.
built 50 ordering constraints for composite.
built 40 ordering constraints for composite.
built 30 ordering constraints for composite.
built 20 ordering constraints for composite.
built 56 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 194 rows 184 cols
invariant :u17:p0 + i0:u18:p1 + i0:i0:u19:p2 + i0:i0:i0:u20:p3 + i0:i0:i0:i0:u21:p4 + i0:i0:i0:i0:i0:u6:p6 + i0:i0:i0:i0:i0:u6:p7 + i0:i0:i0:i0:i0:u6:p8 + i0:i0:i0:i0:i0:u6:p9 + i0:i0:i0:i0:i0:u6:p10 + i0:i0:i0:i0:i0:u6:p11 + i0:i0:i0:i0:i0:u6:p12 + i0:i0:i0:i0:i0:u6:p13 + i0:i0:i0:i0:i0:u6:p14 + i0:i0:i0:i0:i0:u6:p15 + i0:i0:i0:i0:i0:u6:p16 + i0:i0:i0:i0:i0:u6:p17 + i0:i0:i0:i0:i0:u6:p18 + i0:i0:i0:i0:i0:u6:p19 + i0:i0:i0:i0:i0:u6:p20 + i0:i0:i0:i0:i0:u6:p21 + i0:i0:i0:i0:i0:u6:p22 + i0:i0:i0:i0:i0:u6:p23 + i0:i0:i0:i0:i0:u6:p24 + i0:i0:i0:i0:i0:u6:p25 + i0:i0:i0:i0:i0:u6:p26 + i0:i0:i0:i0:i0:u6:p27 + i0:i0:i0:i0:i0:u6:p28 + i0:i0:i0:i0:i0:u6:p29 + i0:i0:i0:i0:i0:u6:p30 + i0:i0:i0:i0:i0:u6:p31 + i0:i0:i0:i0:i0:u6:p32 + i0:i0:i0:i0:i0:u15:p5 = 1
invariant :u17:p0 + i1:u14:p178 + i1:u14:p179 + i1:u14:p180 + i1:u14:p181 + i1:u14:p182 + i1:u14:p183 + i1:u16:p168 = 1
invariant :u17:p0 + i0:u18:p1 + i0:i0:u19:p2 + i0:i0:i0:u20:p3 + i0:i0:i0:i0:u21:p4 + i0:i0:i0:i0:i0:u7:p33 + i0:i0:i0:i0:i0:u7:p34 + i0:i0:i0:i0:i0:u7:p35 + i0:i0:i0:i0:i0:u7:p36 + i0:i0:i0:i0:i0:u7:p37 + i0:i0:i0:i0:i0:u7:p38 + i0:i0:i0:i0:i0:u7:p39 + i0:i0:i0:i0:i0:u7:p40 + i0:i0:i0:i0:i0:u7:p41 + i0:i0:i0:i0:i0:u7:p42 + i0:i0:i0:i0:i0:u7:p43 + i0:i0:i0:i0:i0:u7:p44 + i0:i0:i0:i0:i0:u7:p45 + i0:i0:i0:i0:i0:u7:p46 + i0:i0:i0:i0:i0:u7:p47 + i0:i0:i0:i0:i0:u7:p48 + i0:i0:i0:i0:i0:u7:p49 + i0:i0:i0:i0:i0:u7:p50 + i0:i0:i0:i0:i0:u7:p51 + i0:i0:i0:i0:i0:u7:p52 + i0:i0:i0:i0:i0:u7:p53 + i0:i0:i0:i0:i0:u7:p54 + i0:i0:i0:i0:i0:u7:p55 + i0:i0:i0:i0:i0:u7:p56 + i0:i0:i0:i0:i0:u7:p57 + i0:i0:i0:i0:i0:u7:p58 + i0:i0:i0:i0:i0:u7:p59 + i0:i0:i0:i0:i0:u15:p5 = 1
invariant :u17:p0 + i0:u11:p141 + i0:u11:p142 + i0:u11:p143 + i0:u11:p144 + i0:u11:p145 + i0:u11:p146 + i0:u11:p147 + i0:u11:p148 + i0:u11:p149 + i0:u11:p150 + i0:u11:p151 + i0:u11:p152 + i0:u11:p153 + i0:u11:p154 + i0:u11:p155 + i0:u11:p156 + i0:u11:p157 + i0:u11:p158 + i0:u11:p159 + i0:u11:p160 + i0:u11:p161 + i0:u11:p162 + i0:u11:p163 + i0:u11:p164 + i0:u11:p165 + i0:u11:p166 + i0:u11:p167 + i0:u18:p1 = 1
invariant :u17:p0 + i0:u18:p1 + i0:i0:u19:p2 + i0:i0:i0:u9:p87 + i0:i0:i0:u9:p88 + i0:i0:i0:u9:p89 + i0:i0:i0:u9:p90 + i0:i0:i0:u9:p91 + i0:i0:i0:u9:p92 + i0:i0:i0:u9:p93 + i0:i0:i0:u9:p94 + i0:i0:i0:u9:p95 + i0:i0:i0:u9:p96 + i0:i0:i0:u9:p97 + i0:i0:i0:u9:p98 + i0:i0:i0:u9:p99 + i0:i0:i0:u9:p100 + i0:i0:i0:u9:p101 + i0:i0:i0:u9:p102 + i0:i0:i0:u9:p103 + i0:i0:i0:u9:p104 + i0:i0:i0:u9:p105 + i0:i0:i0:u9:p106 + i0:i0:i0:u9:p107 + i0:i0:i0:u9:p108 + i0:i0:i0:u9:p109 + i0:i0:i0:u9:p110 + i0:i0:i0:u9:p111 + i0:i0:i0:u9:p112 + i0:i0:i0:u9:p113 + i0:i0:i0:u20:p3 = 1
invariant :u17:p0 + i0:u18:p1 + i0:i0:u19:p2 + i0:i0:i0:u20:p3 + i0:i0:i0:i0:u8:p60 + i0:i0:i0:i0:u8:p61 + i0:i0:i0:i0:u8:p62 + i0:i0:i0:i0:u8:p63 + i0:i0:i0:i0:u8:p64 + i0:i0:i0:i0:u8:p65 + i0:i0:i0:i0:u8:p66 + i0:i0:i0:i0:u8:p67 + i0:i0:i0:i0:u8:p68 + i0:i0:i0:i0:u8:p69 + i0:i0:i0:i0:u8:p70 + i0:i0:i0:i0:u8:p71 + i0:i0:i0:i0:u8:p72 + i0:i0:i0:i0:u8:p73 + i0:i0:i0:i0:u8:p74 + i0:i0:i0:i0:u8:p75 + i0:i0:i0:i0:u8:p76 + i0:i0:i0:i0:u8:p77 + i0:i0:i0:i0:u8:p78 + i0:i0:i0:i0:u8:p79 + i0:i0:i0:i0:u8:p80 + i0:i0:i0:i0:u8:p81 + i0:i0:i0:i0:u8:p82 + i0:i0:i0:i0:u8:p83 + i0:i0:i0:i0:u8:p84 + i0:i0:i0:i0:u8:p85 + i0:i0:i0:i0:u8:p86 + i0:i0:i0:i0:u21:p4 = 1
invariant :u17:p0 + i0:u18:p1 + i0:i0:u10:p114 + i0:i0:u10:p115 + i0:i0:u10:p116 + i0:i0:u10:p117 + i0:i0:u10:p118 + i0:i0:u10:p119 + i0:i0:u10:p120 + i0:i0:u10:p121 + i0:i0:u10:p122 + i0:i0:u10:p123 + i0:i0:u10:p124 + i0:i0:u10:p125 + i0:i0:u10:p126 + i0:i0:u10:p127 + i0:i0:u10:p128 + i0:i0:u10:p129 + i0:i0:u10:p130 + i0:i0:u10:p131 + i0:i0:u10:p132 + i0:i0:u10:p133 + i0:i0:u10:p134 + i0:i0:u10:p135 + i0:i0:u10:p136 + i0:i0:u10:p137 + i0:i0:u10:p138 + i0:i0:u10:p139 + i0:i0:u10:p140 + i0:i0:u19:p2 = 1
invariant :u17:p0 + i1:u13:p169 + i1:u13:p170 + i1:u13:p171 + i1:u13:p172 + i1:u13:p173 + i1:u13:p174 + i1:u13:p175 + i1:u13:p176 + i1:u13:p177 + i1:u16:p168 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions i0.u11.t17, i0.u11.t23, i0.u11.t27, i0.u11.t29, i0.u11.t31, i0.u11.t33, i0.i0.u10.t36, i0.i0.u10.t42, i0.i0.u10.t46, i0.i0.u10.t48, i0.i0.u10.t50, i0.i0.u10.t52, i0.i0.i0.u9.t55, i0.i0.i0.u9.t61, i0.i0.i0.u9.t65, i0.i0.i0.u9.t67, i0.i0.i0.u9.t69, i0.i0.i0.u9.t71, i0.i0.i0.i0.u8.t74, i0.i0.i0.i0.u8.t80, i0.i0.i0.i0.u8.t84, i0.i0.i0.i0.u8.t86, i0.i0.i0.i0.u8.t88, i0.i0.i0.i0.u8.t90, i0.i0.i0.i0.i0.u6.t111, i0.i0.i0.i0.i0.u6.t117, i0.i0.i0.i0.i0.u6.t121, i0.i0.i0.i0.i0.u6.t123, i0.i0.i0.i0.i0.u6.t125, i0.i0.i0.i0.i0.u6.t127, i0.i0.i0.i0.i0.u7.t93, i0.i0.i0.i0.i0.u7.t99, i0.i0.i0.i0.i0.u7.t103, i0.i0.i0.i0.i0.u7.t105, i0.i0.i0.i0.i0.u7.t107, i0.i0.i0.i0.i0.u7.t109, i1.u13.t9, i1.u13.t11, i1.u13.t12, i1.u13.t14, i1.u14.t3, i1.u14.t4, i1.u14.t6, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/151/43/194
Computing Next relation with stutter on 64 deadlock states
Compilation finished in 2919 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 68 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP0==true))U(<>(<>((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 108 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((LTLAP2==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 143 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([]([]((LTLAP3==true))))U(((LTLAP4==true))U((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 85 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-02 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 97 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(X((LTLAP7==true))))U(<>(X((LTLAP8==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 15 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-04 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]([]((LTLAP9==true))))U(X([]((LTLAP10==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
1958 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,19.6179,304040,1,0,395570,109035,2701,1.39922e+06,864,898614,165090
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((F(G("((i0.i0.i0.i0.i0.u7.p52==0)||(i0.i0.i0.i0.i0.u6.p7==1))"))))
Formula 1 simplified : !FG"((i0.i0.i0.i0.i0.u7.p52==0)||(i0.i0.i0.i0.i0.u6.p7==1))"
Computing Next relation with stutter on 64 deadlock states
LTSmin run took 13594 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP11==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 39 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP13==true))U((LTLAP14==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 98 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 98 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((X((LTLAP16==true)))U(X((LTLAP17==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 30 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](((LTLAP18==true))U(<>((LTLAP19==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 86 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 65 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>([]((LTLAP21==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP22==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 88 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](<>((LTLAP23==true))))U(<>([]((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 98 ms.
FORMULA DiscoveryGPU-PT-06b-LTLCardinality-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527986019791

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 62 ms
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 184 places.
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 194 transitions.
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 03, 2018 12:33:13 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 30 ms
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 106 ms
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 32 ms
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 27 ms
Jun 03, 2018 12:33:13 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 49 redundant transitions.
Jun 03, 2018 12:33:14 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 5 ms
Jun 03, 2018 12:33:14 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 1 ms
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 194 transitions.
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 8 place invariants in 47 ms
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 184 variables to be positive in 276 ms
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 194 transitions.
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/194 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 194 transitions.
Jun 03, 2018 12:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:33:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 194 transitions.
Jun 03, 2018 12:33:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/194) took 2598 ms. Total solver calls (SAT/UNSAT): 2037(351/1686)
Jun 03, 2018 12:33:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(165/194) took 5609 ms. Total solver calls (SAT/UNSAT): 4234(697/3537)
Jun 03, 2018 12:33:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 5926 ms. Total solver calls (SAT/UNSAT): 4377(699/3678)
Jun 03, 2018 12:33:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 194 transitions.
Jun 03, 2018 12:33:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 9 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 03, 2018 12:33:21 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 7416ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DiscoveryGPU-PT-06b"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DiscoveryGPU-PT-06b.tgz
mv DiscoveryGPU-PT-06b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DiscoveryGPU-PT-06b, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r285-csrt-152749175700014"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;