fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r284-csrt-152749175400643
Last Updated
June 26, 2018

About the Execution of ITS-Tools for RefineWMG-PT-005005

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15756.110 2672.00 5388.00 67.30 FTFFFFTFTTFTFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................................................
/home/mcc/execution
total 192K
-rw-r--r-- 1 mcc users 3.6K May 30 22:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 30 22:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 29 16:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 29 16:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.2K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 28 10:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 28 10:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 08:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7K May 28 08:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.4K May 28 07:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 28 07:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 111 May 26 06:33 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 349 May 26 06:33 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.0K May 27 05:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 27 05:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:35 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:35 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 7 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 14K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is RefineWMG-PT-005005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r284-csrt-152749175400643

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-00
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-01
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-02
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-03
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-04
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-05
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-06
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-07
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-08
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-09
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-10
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-11
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-12
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-13
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-14
FORMULA_NAME RefineWMG-PT-005-005-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1527971206095

Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,6.2256e+11,0.094261,6568,2,519,5,12156,6,0,142,13851,0


Converting to forward existential form...Done !
original formula: ((p9>=1) * EF(AG((p14>=1))))
=> equivalent forward existential formula: [(FwdU((Init * (p9>=1)),TRUE) * !(E(TRUE U !((p14>=1)))))] != FALSE
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
(forward)formula 0,0,0.123716,7008,1,0,6,12156,15,0,776,13851,5
FORMULA RefineWMG-PT-005-005-CTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: AG(AF(EF((p22>=1))))
=> equivalent forward existential formula: [FwdG(FwdU(Init,TRUE),!(E(TRUE U (p22>=1))))] = FALSE
(forward)formula 1,1,0.131029,7008,1,0,7,12156,22,0,815,13851,10
FORMULA RefineWMG-PT-005-005-CTLFireability-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: (!(EF((p22>=1))) + E((((p12>=1)||(p9>=1))||((p12>=1)||(p14>=1))) U AG((p5>=1))))
=> equivalent forward existential formula: [(FwdU((Init * !(E((((p12>=1)||(p9>=1))||((p12>=1)||(p14>=1))) U !(E(TRUE U !((p5>=1))))))),TRUE) * (p22>=1))] = FALSE
(forward)formula 2,0,0.183395,8328,1,0,10,22094,31,2,853,16121,16
FORMULA RefineWMG-PT-005-005-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: E(AX(!((p22>=1))) U (((p13>=1)&&(p14>=1))&&(p16>=1)))
=> equivalent forward existential formula: [(FwdU(Init,!(EX(!(!((p22>=1)))))) * (((p13>=1)&&(p14>=1))&&(p16>=1)))] != FALSE
(forward)formula 3,0,0.214342,9120,1,0,76,26490,36,67,855,24030,114
FORMULA RefineWMG-PT-005-005-CTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF(AG((p14>=1)))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U !((p14>=1)))))] != FALSE
(forward)formula 4,0,0.21483,9384,1,0,76,26490,36,67,855,24030,114
FORMULA RefineWMG-PT-005-005-CTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF((AG((((psecond>=2)&&(pprime>=2))||(((p13>=1)&&(p14>=1))&&(p16>=1)))) + AX(!((p10>=1)))))
=> equivalent forward existential formula: ([(FwdU(Init,TRUE) * !(E(TRUE U !((((psecond>=2)&&(pprime>=2))||(((p13>=1)&&(p14>=1))&&(p16>=1)))))))] != FALSE + [(FwdU(Init,TRUE) * !(EX(!(!((p10>=1))))))] != FALSE)
(forward)formula 5,0,0.243136,9912,1,0,78,30115,39,67,865,27780,119
FORMULA RefineWMG-PT-005-005-CTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (AF(A((pterce>=3) U (p12>=1))) + (AF((p5>=1)) + AG(EF((p7>=1)))))
=> equivalent forward existential formula: [(FwdU(((Init * !(!(EG(!(!((E(!((p12>=1)) U (!((pterce>=3)) * !((p12>=1)))) + EG(!((p12>=1)))))))))) * !(!(EG(!((p5>=1)))))),TRUE) * !(E(TRUE U (p7>=1))))] = FALSE
(forward)formula 6,1,0.255802,10440,1,0,79,32512,40,67,865,29844,122
FORMULA RefineWMG-PT-005-005-CTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: EF((!((p25>=1)) * (AG((((p18>=1)&&(p19>=1))&&(p21>=1))) * ((!(p4>=1))&&((p20>=1)&&(p1>=5))))))
=> equivalent forward existential formula: [(((FwdU(Init,TRUE) * !((p25>=1))) * ((!(p4>=1))&&((p20>=1)&&(p1>=5)))) * !(E(TRUE U !((((p18>=1)&&(p19>=1))&&(p21>=1))))))] != FALSE
(forward)formula 7,0,0.259316,10968,1,0,80,32978,42,67,871,30114,125
FORMULA RefineWMG-PT-005-005-CTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (!((p22>=1)) * EF((p1>=5)))
=> equivalent forward existential formula: [(FwdU((Init * !((p22>=1))),TRUE) * (p1>=5))] != FALSE
(forward)formula 8,1,0.260026,11232,1,0,82,32999,44,68,872,30285,127
FORMULA RefineWMG-PT-005-005-CTLFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AG(EX(!((pterce>=3))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(EX(!((pterce>=3)))))] = FALSE
(forward)formula 9,1,0.260349,11232,1,0,83,33000,46,68,873,30286,129
FORMULA RefineWMG-PT-005-005-CTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: E(E((((p18>=1)&&(p19>=1))&&(p21>=1)) U ((psecond>=2)&&(pprime>=2))) U (AG((p22>=1)) * (((((p13>=1)&&(p14>=1))&&(p16>=1))&&(((p3>=1)&&(p4>=1))&&(p6>=1)))||((p4>=1)||(p10>=1)))))
=> equivalent forward existential formula: [((FwdU(Init,E((((p18>=1)&&(p19>=1))&&(p21>=1)) U ((psecond>=2)&&(pprime>=2)))) * (((((p13>=1)&&(p14>=1))&&(p16>=1))&&(((p3>=1)&&(p4>=1))&&(p6>=1)))||((p4>=1)||(p10>=1)))) * !(E(TRUE U !((p22>=1)))))] != FALSE
(forward)formula 10,0,0.261375,11232,1,0,84,33130,46,68,873,30343,132
FORMULA RefineWMG-PT-005-005-CTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: AG(EF((((p3>=1)&&(p4>=1))&&(p6>=1))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U (((p3>=1)&&(p4>=1))&&(p6>=1)))))] = FALSE
(forward)formula 11,1,0.272842,11232,1,0,85,35284,47,68,875,32011,135
FORMULA RefineWMG-PT-005-005-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: E((EF((p24>=1)) * EF((p12>=1))) U !(EX((p25>=1))))
=> equivalent forward existential formula: [(FwdU(Init,(E(TRUE U (p24>=1)) * E(TRUE U (p12>=1)))) * !(EX((p25>=1))))] != FALSE
(forward)formula 12,0,0.273832,11232,1,0,86,35350,48,68,875,32088,137
FORMULA RefineWMG-PT-005-005-CTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF(!(EF(((p10>=1)&&(p19>=1)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U ((p10>=1)&&(p19>=1)))))] != FALSE
(forward)formula 13,0,0.275445,11232,1,0,87,35495,49,68,876,32094,140
FORMULA RefineWMG-PT-005-005-CTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (!(E((pterce>=3) U ((p9>=1)&&(p10>=1)))) + AX(EX(((p17>=1)&&(p15>=1)))))
=> equivalent forward existential formula: [(EY((Init * !(!(E((pterce>=3) U ((p9>=1)&&(p10>=1))))))) * !(EX(((p17>=1)&&(p15>=1)))))] = FALSE
Hit Full ! (commute/partial/dont) 21/0/2
(forward)formula 14,1,0.288725,11496,1,0,93,38064,57,70,888,34882,146
FORMULA RefineWMG-PT-005-005-CTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: EF(AG((p9>=1)))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U !((p9>=1)))))] != FALSE
(forward)formula 15,0,0.291228,11760,1,0,94,38560,59,70,889,34938,149
FORMULA RefineWMG-PT-005-005-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************


BK_STOP 1527971208767

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 8:26:47 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 8:26:47 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 8:26:47 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 37 ms
Jun 02, 2018 8:26:47 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 29 places.
Jun 02, 2018 8:26:48 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 23 transitions.
Jun 02, 2018 8:26:48 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 9 ms
Jun 02, 2018 8:26:48 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 24 ms
Jun 02, 2018 8:26:48 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 1 ms
Jun 02, 2018 8:26:48 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 2 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-005005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-005005.tgz
mv RefineWMG-PT-005005 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is RefineWMG-PT-005005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r284-csrt-152749175400643"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;