Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................
/home/mcc/execution
total 276K
-rw-r--r-- 1 mcc users 3.2K May 30 21:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 30 21:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 29 15:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 29 15:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.6K May 28 09:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 08:00 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7K May 28 08:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.4K May 28 06:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 28 06:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 348 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.4K May 27 03:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 27 03:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 111K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DiscoveryGPU-PT-15b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r284-csrt-152749174700177
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-00
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-01
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-02
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-03
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-04
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-05
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-06
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-07
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-08
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-09
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-10
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-11
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-12
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-13
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-14
FORMULA_NAME DiscoveryGPU-PT-15b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527921501859

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("((u27.p345>=1)&&(u31.p427>=1))"))
Formula 0 simplified : !"((u27.p345>=1)&&(u31.p427>=1))"
built 46 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 464 rows 436 cols
invariant :u22:p204 + u22:p205 + u22:p206 + u22:p207 + u22:p208 + u22:p209 + u22:p210 + u22:p211 + u22:p212 + u22:p213 + u22:p214 + u22:p215 + u22:p216 + u22:p217 + u22:p218 + u22:p219 + u22:p220 + u22:p221 + u22:p222 + u22:p223 + u22:p224 + u22:p225 + u22:p226 + u22:p227 + u22:p228 + u22:p229 + u22:p230 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u28:p366 + u28:p367 + u28:p368 + u28:p369 + u28:p370 + u28:p371 + u28:p372 + u28:p373 + u28:p374 + u28:p375 + u28:p376 + u28:p377 + u28:p378 + u28:p379 + u28:p380 + u28:p381 + u28:p382 + u28:p383 + u28:p384 + u28:p385 + u28:p386 + u28:p387 + u28:p388 + u28:p389 + u28:p390 + u28:p391 + u28:p392 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u25:p285 + u25:p286 + u25:p287 + u25:p288 + u25:p289 + u25:p290 + u25:p291 + u25:p292 + u25:p293 + u25:p294 + u25:p295 + u25:p296 + u25:p297 + u25:p298 + u25:p299 + u25:p300 + u25:p301 + u25:p302 + u25:p303 + u25:p304 + u25:p305 + u25:p306 + u25:p307 + u25:p308 + u25:p309 + u25:p310 + u25:p311 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u19:p123 + u19:p124 + u19:p125 + u19:p126 + u19:p127 + u19:p128 + u19:p129 + u19:p130 + u19:p131 + u19:p132 + u19:p133 + u19:p134 + u19:p135 + u19:p136 + u19:p137 + u19:p138 + u19:p139 + u19:p140 + u19:p141 + u19:p142 + u19:p143 + u19:p144 + u19:p145 + u19:p146 + u19:p147 + u19:p148 + u19:p149 + u34:p11 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u24:p258 + u24:p259 + u24:p260 + u24:p261 + u24:p262 + u24:p263 + u24:p264 + u24:p265 + u24:p266 + u24:p267 + u24:p268 + u24:p269 + u24:p270 + u24:p271 + u24:p272 + u24:p273 + u24:p274 + u24:p275 + u24:p276 + u24:p277 + u24:p278 + u24:p279 + u24:p280 + u24:p281 + u24:p282 + u24:p283 + u24:p284 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u23:p231 + u23:p232 + u23:p233 + u23:p234 + u23:p235 + u23:p236 + u23:p237 + u23:p238 + u23:p239 + u23:p240 + u23:p241 + u23:p242 + u23:p243 + u23:p244 + u23:p245 + u23:p246 + u23:p247 + u23:p248 + u23:p249 + u23:p250 + u23:p251 + u23:p252 + u23:p253 + u23:p254 + u23:p255 + u23:p256 + u23:p257 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u18:p96 + u18:p97 + u18:p98 + u18:p99 + u18:p100 + u18:p101 + u18:p102 + u18:p103 + u18:p104 + u18:p105 + u18:p106 + u18:p107 + u18:p108 + u18:p109 + u18:p110 + u18:p111 + u18:p112 + u18:p113 + u18:p114 + u18:p115 + u18:p116 + u18:p117 + u18:p118 + u18:p119 + u18:p120 + u18:p121 + u18:p122 + u37:p12 + u34:p11 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u29:p393 + u29:p394 + u29:p395 + u29:p396 + u29:p397 + u29:p398 + u29:p399 + u29:p400 + u29:p401 + u29:p402 + u29:p403 + u29:p404 + u29:p405 + u29:p406 + u29:p407 + u29:p408 + u29:p409 + u29:p410 + u29:p411 + u29:p412 + u29:p413 + u29:p414 + u29:p415 + u29:p416 + u29:p417 + u29:p418 + u29:p419 + u40:p1 + u39:p0 = 1
invariant :u21:p177 + u21:p178 + u21:p179 + u21:p180 + u21:p181 + u21:p182 + u21:p183 + u21:p184 + u21:p185 + u21:p186 + u21:p187 + u21:p188 + u21:p189 + u21:p190 + u21:p191 + u21:p192 + u21:p193 + u21:p194 + u21:p195 + u21:p196 + u21:p197 + u21:p198 + u21:p199 + u21:p200 + u21:p201 + u21:p202 + u21:p203 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u20:p150 + u20:p151 + u20:p152 + u20:p153 + u20:p154 + u20:p155 + u20:p156 + u20:p157 + u20:p158 + u20:p159 + u20:p160 + u20:p161 + u20:p162 + u20:p163 + u20:p164 + u20:p165 + u20:p166 + u20:p167 + u20:p168 + u20:p169 + u20:p170 + u20:p171 + u20:p172 + u20:p173 + u20:p174 + u20:p175 + u20:p176 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u27:p339 + u27:p340 + u27:p341 + u27:p342 + u27:p343 + u27:p344 + u27:p345 + u27:p346 + u27:p347 + u27:p348 + u27:p349 + u27:p350 + u27:p351 + u27:p352 + u27:p353 + u27:p354 + u27:p355 + u27:p356 + u27:p357 + u27:p358 + u27:p359 + u27:p360 + u27:p361 + u27:p362 + u27:p363 + u27:p364 + u27:p365 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u31:p421 + u31:p422 + u31:p423 + u31:p424 + u31:p425 + u31:p426 + u31:p427 + u31:p428 + u31:p429 + u33:p420 + u39:p0 = 1
invariant :u26:p312 + u26:p313 + u26:p314 + u26:p315 + u26:p316 + u26:p317 + u26:p318 + u26:p319 + u26:p320 + u26:p321 + u26:p322 + u26:p323 + u26:p324 + u26:p325 + u26:p326 + u26:p327 + u26:p328 + u26:p329 + u26:p330 + u26:p331 + u26:p332 + u26:p333 + u26:p334 + u26:p335 + u26:p336 + u26:p337 + u26:p338 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u15:p15 + u15:p16 + u15:p17 + u15:p18 + u15:p19 + u15:p20 + u15:p21 + u15:p22 + u15:p23 + u15:p24 + u15:p25 + u15:p26 + u15:p27 + u15:p28 + u15:p29 + u15:p30 + u15:p31 + u15:p32 + u15:p33 + u15:p34 + u15:p35 + u15:p36 + u15:p37 + u15:p38 + u15:p39 + u15:p40 + u15:p41 + u38:p14 + u36:p13 + u37:p12 + u34:p11 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u17:p69 + u17:p70 + u17:p71 + u17:p72 + u17:p73 + u17:p74 + u17:p75 + u17:p76 + u17:p77 + u17:p78 + u17:p79 + u17:p80 + u17:p81 + u17:p82 + u17:p83 + u17:p84 + u17:p85 + u17:p86 + u17:p87 + u17:p88 + u17:p89 + u17:p90 + u17:p91 + u17:p92 + u17:p93 + u17:p94 + u17:p95 + u36:p13 + u37:p12 + u34:p11 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
invariant :u32:p430 + u32:p431 + u32:p432 + u32:p433 + u32:p434 + u32:p435 + u33:p420 + u39:p0 = 1
invariant :u16:p42 + u16:p43 + u16:p44 + u16:p45 + u16:p46 + u16:p47 + u16:p48 + u16:p49 + u16:p50 + u16:p51 + u16:p52 + u16:p53 + u16:p54 + u16:p55 + u16:p56 + u16:p57 + u16:p58 + u16:p59 + u16:p60 + u16:p61 + u16:p62 + u16:p63 + u16:p64 + u16:p65 + u16:p66 + u16:p67 + u16:p68 + u38:p14 + u36:p13 + u37:p12 + u34:p11 + u35:p10 + u48:p9 + u47:p8 + u46:p7 + u45:p6 + u44:p5 + u43:p4 + u42:p3 + u41:p2 + u40:p1 + u39:p0 = 1
Reverse transition relation is NOT exact ! Due to transitions u15.t282, u15.t288, u15.t292, u15.t294, u15.t296, u15.t298, u16.t264, u16.t270, u16.t274, u16.t276, u16.t278, u16.t280, u17.t245, u17.t251, u17.t255, u17.t257, u17.t259, u17.t261, u18.t226, u18.t232, u18.t236, u18.t238, u18.t240, u18.t242, u19.t207, u19.t213, u19.t217, u19.t219, u19.t221, u19.t223, u20.t188, u20.t194, u20.t198, u20.t200, u20.t202, u20.t204, u21.t169, u21.t175, u21.t179, u21.t181, u21.t183, u21.t185, u22.t150, u22.t156, u22.t160, u22.t162, u22.t164, u22.t166, u23.t131, u23.t137, u23.t141, u23.t143, u23.t145, u23.t147, u24.t112, u24.t118, u24.t122, u24.t124, u24.t126, u24.t128, u25.t93, u25.t99, u25.t103, u25.t105, u25.t107, u25.t109, u26.t74, u26.t80, u26.t84, u26.t86, u26.t88, u26.t90, u27.t55, u27.t61, u27.t65, u27.t67, u27.t69, u27.t71, u28.t36, u28.t42, u28.t46, u28.t48, u28.t50, u28.t52, u29.t17, u29.t23, u29.t27, u29.t29, u29.t31, u29.t33, u31.t9, u31.t11, u31.t12, u31.t14, u32.t3, u32.t4, u32.t6, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/367/97/464
Computing Next relation with stutter on 32768 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1577 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,15.812,269308,1,0,378122,44266,2924,570288,923,419971,1564250
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !(("(u20.p168>=1)"))
Formula 1 simplified : !"(u20.p168>=1)"
Computing Next relation with stutter on 32768 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,15.8133,269308,1,0,378122,44266,2929,570288,924,419971,1564276
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((G(X(F(F(F("(u27.p348>=1)")))))))
Formula 2 simplified : !GXF"(u27.p348>=1)"
Computing Next relation with stutter on 32768 deadlock states
85 unique states visited
85 strongly connected components in search stack
86 transitions explored
85 items max in DFS search stack
994 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,25.7547,499180,1,0,742655,54937,2966,1.13407e+06,925,554345,2170522
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !((("(u31.p429>=1)")U(X(F(G("((u19.p147>=1)&&(u31.p427>=1))"))))))
Formula 3 simplified : !("(u31.p429>=1)" U XFG"((u19.p147>=1)&&(u31.p427>=1))")
Computing Next relation with stutter on 32768 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 7681 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 120 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP3==true))U(X(<>([]((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 135 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>((LTLAP5==true)))U(([]((LTLAP6==true)))U(<>((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 546 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](X([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 66 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP9==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 607 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(X(<>((LTLAP10==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 54 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](<>(<>((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>((LTLAP12==true)))U(<>((LTLAP13==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 579 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (([]((LTLAP14==true)))U(X((LTLAP15==true))))U(X(((LTLAP16==true))U((LTLAP17==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((<>(X((LTLAP18==true))))U(X(<>((LTLAP19==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 67 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 548 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X([]((LTLAP21==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 42 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP22==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 508 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(((LTLAP23==true))U([](<>((LTLAP24==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 502 ms.
FORMULA DiscoveryGPU-PT-15b-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527921693285

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 75 ms
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 436 places.
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 464 transitions.
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 02, 2018 6:38:24 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 21 ms
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 90 ms
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 130 redundant transitions.
Jun 02, 2018 6:38:24 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 8 ms
Jun 02, 2018 6:38:24 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Jun 02, 2018 6:38:24 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 464 transitions.
Jun 02, 2018 6:38:25 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 17 place invariants in 183 ms
Jun 02, 2018 6:38:25 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 436 variables to be positive in 838 ms
Jun 02, 2018 6:38:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 464 transitions.
Jun 02, 2018 6:38:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/464 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:38:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 49 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:38:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 464 transitions.
Jun 02, 2018 6:38:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 14 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:38:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 464 transitions.
Jun 02, 2018 6:38:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/464) took 1340 ms. Total solver calls (SAT/UNSAT): 3563(0/3563)
Jun 02, 2018 6:38:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/464) took 5463 ms. Total solver calls (SAT/UNSAT): 4375(124/4251)
Jun 02, 2018 6:38:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/464) took 8920 ms. Total solver calls (SAT/UNSAT): 4858(380/4478)
Jun 02, 2018 6:38:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/464) took 12305 ms. Total solver calls (SAT/UNSAT): 5292(586/4706)
Jun 02, 2018 6:38:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(38/464) took 15849 ms. Total solver calls (SAT/UNSAT): 5625(724/4901)
Jun 02, 2018 6:38:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(54/464) took 20368 ms. Total solver calls (SAT/UNSAT): 6337(930/5407)
Jun 02, 2018 6:38:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/464) took 25858 ms. Total solver calls (SAT/UNSAT): 6655(1029/5626)
Jun 02, 2018 6:38:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(63/464) took 29686 ms. Total solver calls (SAT/UNSAT): 6886(1195/5691)
Jun 02, 2018 6:39:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/464) took 33872 ms. Total solver calls (SAT/UNSAT): 7000(1277/5723)
Jun 02, 2018 6:39:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/464) took 38172 ms. Total solver calls (SAT/UNSAT): 7113(1357/5756)
Jun 02, 2018 6:39:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/464) took 41934 ms. Total solver calls (SAT/UNSAT): 7336(1515/5821)
Jun 02, 2018 6:39:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/464) took 45305 ms. Total solver calls (SAT/UNSAT): 7663(1745/5918)
Jun 02, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(71/464) took 49484 ms. Total solver calls (SAT/UNSAT): 7770(1819/5951)
Jun 02, 2018 6:39:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(72/464) took 52954 ms. Total solver calls (SAT/UNSAT): 7876(1893/5983)
Jun 02, 2018 6:39:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/464) took 56510 ms. Total solver calls (SAT/UNSAT): 7981(1965/6016)
Jun 02, 2018 6:39:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(77/464) took 60335 ms. Total solver calls (SAT/UNSAT): 8391(2245/6146)
Jun 02, 2018 6:39:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(80/464) took 63459 ms. Total solver calls (SAT/UNSAT): 8688(2445/6243)
Jun 02, 2018 6:39:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/464) took 66999 ms. Total solver calls (SAT/UNSAT): 8976(2635/6341)
Jun 02, 2018 6:39:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(88/464) took 70224 ms. Total solver calls (SAT/UNSAT): 9436(2933/6503)
Jun 02, 2018 6:39:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(94/464) took 73304 ms. Total solver calls (SAT/UNSAT): 9955(3265/6690)
Jun 02, 2018 6:39:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(97/464) took 76583 ms. Total solver calls (SAT/UNSAT): 10201(3419/6782)
Jun 02, 2018 6:39:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(99/464) took 82076 ms. Total solver calls (SAT/UNSAT): 10360(3517/6843)
Jun 02, 2018 6:39:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/464) took 88386 ms. Total solver calls (SAT/UNSAT): 10515(3611/6904)
Jun 02, 2018 6:40:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(103/464) took 94066 ms. Total solver calls (SAT/UNSAT): 10666(3701/6965)
Jun 02, 2018 6:40:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(105/464) took 98732 ms. Total solver calls (SAT/UNSAT): 10813(3787/7026)
Jun 02, 2018 6:40:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(107/464) took 104081 ms. Total solver calls (SAT/UNSAT): 10956(3869/7087)
Jun 02, 2018 6:40:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(108/464) took 107428 ms. Total solver calls (SAT/UNSAT): 11026(3909/7117)
Jun 02, 2018 6:40:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/464) took 111081 ms. Total solver calls (SAT/UNSAT): 11163(3985/7178)
Jun 02, 2018 6:40:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/464) took 114095 ms. Total solver calls (SAT/UNSAT): 11550(4189/7361)
Jun 02, 2018 6:40:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(125/464) took 117935 ms. Total solver calls (SAT/UNSAT): 12063(4437/7626)
Jun 02, 2018 6:40:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/464) took 120970 ms. Total solver calls (SAT/UNSAT): 12166(4483/7683)
Jun 02, 2018 6:40:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(130/464) took 125132 ms. Total solver calls (SAT/UNSAT): 12313(4545/7768)
Jun 02, 2018 6:40:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(132/464) took 129158 ms. Total solver calls (SAT/UNSAT): 12406(4581/7825)
Jun 02, 2018 6:40:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/464) took 133351 ms. Total solver calls (SAT/UNSAT): 12621(4653/7968)
Jun 02, 2018 6:40:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(171/464) took 136400 ms. Total solver calls (SAT/UNSAT): 13272(4729/8543)
Jun 02, 2018 6:40:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(180/464) took 139522 ms. Total solver calls (SAT/UNSAT): 13398(4732/8666)
Jun 02, 2018 6:40:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(211/464) took 142541 ms. Total solver calls (SAT/UNSAT): 13652(4737/8915)
Jun 02, 2018 6:40:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(221/464) took 145546 ms. Total solver calls (SAT/UNSAT): 13787(4741/9046)
Jun 02, 2018 6:40:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(240/464) took 148852 ms. Total solver calls (SAT/UNSAT): 13968(4744/9224)
Jun 02, 2018 6:40:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(265/464) took 151972 ms. Total solver calls (SAT/UNSAT): 14193(4749/9444)
Jun 02, 2018 6:41:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(278/464) took 155140 ms. Total solver calls (SAT/UNSAT): 14327(4751/9576)
Jun 02, 2018 6:41:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(294/464) took 158512 ms. Total solver calls (SAT/UNSAT): 14463(4754/9709)
Jun 02, 2018 6:41:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(308/464) took 161517 ms. Total solver calls (SAT/UNSAT): 14582(4757/9825)
Jun 02, 2018 6:41:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(322/464) took 164611 ms. Total solver calls (SAT/UNSAT): 14745(4761/9984)
Jun 02, 2018 6:41:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(335/464) took 167990 ms. Total solver calls (SAT/UNSAT): 14858(4763/10095)
Jun 02, 2018 6:41:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(348/464) took 171028 ms. Total solver calls (SAT/UNSAT): 14962(4765/10197)
Jun 02, 2018 6:41:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 173238 ms. Total solver calls (SAT/UNSAT): 15951(4785/11166)
Jun 02, 2018 6:41:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 464 transitions.
Jun 02, 2018 6:41:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 61 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:41:21 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 176428ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DiscoveryGPU-PT-15b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DiscoveryGPU-PT-15b.tgz
mv DiscoveryGPU-PT-15b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DiscoveryGPU-PT-15b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r284-csrt-152749174700177"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;