Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.................
/home/mcc/execution
total 268K
-rw-r--r-- 1 mcc users 3.1K May 30 21:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 30 21:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 29 15:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 13K May 29 15:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.1K May 28 09:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.1K May 28 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.7K May 28 06:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 28 06:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 348 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 27 03:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 27 03:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 104K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DiscoveryGPU-PT-14b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r284-csrt-152749174700159
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-00
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-01
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-02
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-03
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-04
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-05
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-06
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-07
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-08
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-09
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-10
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-11
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-12
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-13
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-14
FORMULA_NAME DiscoveryGPU-PT-14b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527921455507

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(F(F(X("((u24.p299>=1)&&(u29.p399>=1))"))))))
Formula 0 simplified : !XFX"((u24.p299>=1)&&(u29.p399>=1))"
built 43 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 434 rows 408 cols
invariant :u24:p284 + u24:p285 + u24:p286 + u24:p287 + u24:p288 + u24:p289 + u24:p290 + u24:p291 + u24:p292 + u24:p293 + u24:p294 + u24:p295 + u24:p296 + u24:p297 + u24:p298 + u24:p299 + u24:p300 + u24:p301 + u24:p302 + u24:p303 + u24:p304 + u24:p305 + u24:p306 + u24:p307 + u24:p308 + u24:p309 + u24:p310 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u15:p41 + u15:p42 + u15:p43 + u15:p44 + u15:p45 + u15:p46 + u15:p47 + u15:p48 + u15:p49 + u15:p50 + u15:p51 + u15:p52 + u15:p53 + u15:p54 + u15:p55 + u15:p56 + u15:p57 + u15:p58 + u15:p59 + u15:p60 + u15:p61 + u15:p62 + u15:p63 + u15:p64 + u15:p65 + u15:p66 + u15:p67 + u33:p13 + u34:p12 + u31:p11 + u32:p10 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u22:p230 + u22:p231 + u22:p232 + u22:p233 + u22:p234 + u22:p235 + u22:p236 + u22:p237 + u22:p238 + u22:p239 + u22:p240 + u22:p241 + u22:p242 + u22:p243 + u22:p244 + u22:p245 + u22:p246 + u22:p247 + u22:p248 + u22:p249 + u22:p250 + u22:p251 + u22:p252 + u22:p253 + u22:p254 + u22:p255 + u22:p256 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u30:p402 + u30:p403 + u30:p404 + u30:p405 + u30:p406 + u30:p407 + u45:p392 + u35:p0 = 1
invariant :u27:p365 + u27:p366 + u27:p367 + u27:p368 + u27:p369 + u27:p370 + u27:p371 + u27:p372 + u27:p373 + u27:p374 + u27:p375 + u27:p376 + u27:p377 + u27:p378 + u27:p379 + u27:p380 + u27:p381 + u27:p382 + u27:p383 + u27:p384 + u27:p385 + u27:p386 + u27:p387 + u27:p388 + u27:p389 + u27:p390 + u27:p391 + u36:p1 + u35:p0 = 1
invariant :u21:p203 + u21:p204 + u21:p205 + u21:p206 + u21:p207 + u21:p208 + u21:p209 + u21:p210 + u21:p211 + u21:p212 + u21:p213 + u21:p214 + u21:p215 + u21:p216 + u21:p217 + u21:p218 + u21:p219 + u21:p220 + u21:p221 + u21:p222 + u21:p223 + u21:p224 + u21:p225 + u21:p226 + u21:p227 + u21:p228 + u21:p229 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u16:p68 + u16:p69 + u16:p70 + u16:p71 + u16:p72 + u16:p73 + u16:p74 + u16:p75 + u16:p76 + u16:p77 + u16:p78 + u16:p79 + u16:p80 + u16:p81 + u16:p82 + u16:p83 + u16:p84 + u16:p85 + u16:p86 + u16:p87 + u16:p88 + u16:p89 + u16:p90 + u16:p91 + u16:p92 + u16:p93 + u16:p94 + u34:p12 + u31:p11 + u32:p10 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u14:p14 + u14:p15 + u14:p16 + u14:p17 + u14:p18 + u14:p19 + u14:p20 + u14:p21 + u14:p22 + u14:p23 + u14:p24 + u14:p25 + u14:p26 + u14:p27 + u14:p28 + u14:p29 + u14:p30 + u14:p31 + u14:p32 + u14:p33 + u14:p34 + u14:p35 + u14:p36 + u14:p37 + u14:p38 + u14:p39 + u14:p40 + u33:p13 + u34:p12 + u31:p11 + u32:p10 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u20:p176 + u20:p177 + u20:p178 + u20:p179 + u20:p180 + u20:p181 + u20:p182 + u20:p183 + u20:p184 + u20:p185 + u20:p186 + u20:p187 + u20:p188 + u20:p189 + u20:p190 + u20:p191 + u20:p192 + u20:p193 + u20:p194 + u20:p195 + u20:p196 + u20:p197 + u20:p198 + u20:p199 + u20:p200 + u20:p201 + u20:p202 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u19:p149 + u19:p150 + u19:p151 + u19:p152 + u19:p153 + u19:p154 + u19:p155 + u19:p156 + u19:p157 + u19:p158 + u19:p159 + u19:p160 + u19:p161 + u19:p162 + u19:p163 + u19:p164 + u19:p165 + u19:p166 + u19:p167 + u19:p168 + u19:p169 + u19:p170 + u19:p171 + u19:p172 + u19:p173 + u19:p174 + u19:p175 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u25:p311 + u25:p312 + u25:p313 + u25:p314 + u25:p315 + u25:p316 + u25:p317 + u25:p318 + u25:p319 + u25:p320 + u25:p321 + u25:p322 + u25:p323 + u25:p324 + u25:p325 + u25:p326 + u25:p327 + u25:p328 + u25:p329 + u25:p330 + u25:p331 + u25:p332 + u25:p333 + u25:p334 + u25:p335 + u25:p336 + u25:p337 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u26:p338 + u26:p339 + u26:p340 + u26:p341 + u26:p342 + u26:p343 + u26:p344 + u26:p345 + u26:p346 + u26:p347 + u26:p348 + u26:p349 + u26:p350 + u26:p351 + u26:p352 + u26:p353 + u26:p354 + u26:p355 + u26:p356 + u26:p357 + u26:p358 + u26:p359 + u26:p360 + u26:p361 + u26:p362 + u26:p363 + u26:p364 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u18:p122 + u18:p123 + u18:p124 + u18:p125 + u18:p126 + u18:p127 + u18:p128 + u18:p129 + u18:p130 + u18:p131 + u18:p132 + u18:p133 + u18:p134 + u18:p135 + u18:p136 + u18:p137 + u18:p138 + u18:p139 + u18:p140 + u18:p141 + u18:p142 + u18:p143 + u18:p144 + u18:p145 + u18:p146 + u18:p147 + u18:p148 + u32:p10 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u17:p95 + u17:p96 + u17:p97 + u17:p98 + u17:p99 + u17:p100 + u17:p101 + u17:p102 + u17:p103 + u17:p104 + u17:p105 + u17:p106 + u17:p107 + u17:p108 + u17:p109 + u17:p110 + u17:p111 + u17:p112 + u17:p113 + u17:p114 + u17:p115 + u17:p116 + u17:p117 + u17:p118 + u17:p119 + u17:p120 + u17:p121 + u31:p11 + u32:p10 + u44:p9 + u43:p8 + u42:p7 + u41:p6 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u23:p257 + u23:p258 + u23:p259 + u23:p260 + u23:p261 + u23:p262 + u23:p263 + u23:p264 + u23:p265 + u23:p266 + u23:p267 + u23:p268 + u23:p269 + u23:p270 + u23:p271 + u23:p272 + u23:p273 + u23:p274 + u23:p275 + u23:p276 + u23:p277 + u23:p278 + u23:p279 + u23:p280 + u23:p281 + u23:p282 + u23:p283 + u40:p5 + u39:p4 + u38:p3 + u37:p2 + u36:p1 + u35:p0 = 1
invariant :u29:p393 + u29:p394 + u29:p395 + u29:p396 + u29:p397 + u29:p398 + u29:p399 + u29:p400 + u29:p401 + u45:p392 + u35:p0 = 1
Reverse transition relation is NOT exact ! Due to transitions u14.t263, u14.t269, u14.t273, u14.t275, u14.t277, u14.t279, u15.t245, u15.t251, u15.t255, u15.t257, u15.t259, u15.t261, u16.t226, u16.t232, u16.t236, u16.t238, u16.t240, u16.t242, u17.t207, u17.t213, u17.t217, u17.t219, u17.t221, u17.t223, u18.t188, u18.t194, u18.t198, u18.t200, u18.t202, u18.t204, u19.t169, u19.t175, u19.t179, u19.t181, u19.t183, u19.t185, u20.t150, u20.t156, u20.t160, u20.t162, u20.t164, u20.t166, u21.t131, u21.t137, u21.t141, u21.t143, u21.t145, u21.t147, u22.t112, u22.t118, u22.t122, u22.t124, u22.t126, u22.t128, u23.t93, u23.t99, u23.t103, u23.t105, u23.t107, u23.t109, u24.t74, u24.t80, u24.t84, u24.t86, u24.t88, u24.t90, u25.t55, u25.t61, u25.t65, u25.t67, u25.t69, u25.t71, u26.t36, u26.t42, u26.t46, u26.t48, u26.t50, u26.t52, u27.t17, u27.t23, u27.t27, u27.t29, u27.t31, u27.t33, u29.t9, u29.t11, u29.t12, u29.t14, u30.t3, u30.t4, u30.t6, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/343/91/434
Computing Next relation with stutter on 16384 deadlock states
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
3144 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,31.4956,760880,1,0,1.31097e+06,51321,2668,1.87668e+06,887,538504,3397344
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((F(X("(u20.p185>=1)"))))
Formula 1 simplified : !FX"(u20.p185>=1)"
Computing Next relation with stutter on 16384 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
568 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,37.1733,898468,1,0,1.551e+06,56689,2824,2.22953e+06,899,646069,3942144
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((G("(u20.p190>=1)")))
Formula 2 simplified : !G"(u20.p190>=1)"
Computing Next relation with stutter on 16384 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
319 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,40.3641,957844,1,0,1.64364e+06,56762,2884,2.37489e+06,900,648798,4209445
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !((F(X(F(X("(u26.p343>=1)"))))))
Formula 3 simplified : !FXFX"(u26.p343>=1)"
Computing Next relation with stutter on 16384 deadlock states
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
204 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,42.4181,988192,1,0,1.69688e+06,57001,2923,2.4431e+06,901,656142,4341819
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 4 : !(((("((u14.p27>=1)&&(u29.p399>=1))")U(X("(u15.p57>=1)")))U(G(X(G("(u19.p174>=1)"))))))
Formula 4 simplified : !(("((u14.p27>=1)&&(u29.p399>=1))" U X"(u15.p57>=1)") U GXG"(u19.p174>=1)")
Computing Next relation with stutter on 16384 deadlock states
81 unique states visited
81 strongly connected components in search stack
82 transitions explored
81 items max in DFS search stack
172 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,44.1527,1027112,1,0,1.75024e+06,63679,2993,2.54911e+06,903,724316,4470335
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 5 : !(((G(G("(u15.p64>=1)")))U((X("(u27.p388>=1)"))U("((u27.p386>=1)&&(u30.p406>=1))"))))
Formula 5 simplified : !(G"(u15.p64>=1)" U (X"(u27.p388>=1)" U "((u27.p386>=1)&&(u30.p406>=1))"))
Computing Next relation with stutter on 16384 deadlock states
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,44.156,1027536,1,0,1.75024e+06,63679,3016,2.54911e+06,904,724316,4470459
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 6 : !((F("(u27.p387>=1)")))
Formula 6 simplified : !F"(u27.p387>=1)"
Computing Next relation with stutter on 16384 deadlock states
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
6 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,44.2235,1029912,1,0,1.75698e+06,63682,3051,2.55486e+06,905,724405,4485262
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 7 : !((F(F(G(G("(u24.p303>=1)"))))))
Formula 7 simplified : !FG"(u24.p303>=1)"
Computing Next relation with stutter on 16384 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 5587 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 74 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>([]([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 463 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 34 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(([](X((LTLAP13==true))))U(<>([]((LTLAP14==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 46 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP15==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 48 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 415 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP17==true)))U(<>((LTLAP18==true))))U(<>([](<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 460 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](((LTLAP19==true))U((LTLAP20==true))))U(<>(((LTLAP21==true))U((LTLAP22==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 444 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP23==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 423 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X([]((LTLAP16==true)))))U(X((LTLAP24==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 35 ms.
FORMULA DiscoveryGPU-PT-14b-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527921526977

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 80 ms
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 408 places.
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 434 transitions.
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 02, 2018 6:37:37 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 26 ms
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 79 ms
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 121 redundant transitions.
Jun 02, 2018 6:37:37 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 8 ms
Jun 02, 2018 6:37:37 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 0 ms
Jun 02, 2018 6:37:37 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 434 transitions.
Jun 02, 2018 6:37:38 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 16 place invariants in 135 ms
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 408 variables to be positive in 875 ms
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 434 transitions.
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/434 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 33 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 434 transitions.
Jun 02, 2018 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 24 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:37:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 434 transitions.
Jun 02, 2018 6:37:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/434) took 1455 ms. Total solver calls (SAT/UNSAT): 3738(39/3699)
Jun 02, 2018 6:37:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/434) took 4662 ms. Total solver calls (SAT/UNSAT): 4341(350/3991)
Jun 02, 2018 6:37:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/434) took 7865 ms. Total solver calls (SAT/UNSAT): 4863(579/4284)
Jun 02, 2018 6:37:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/434) took 10904 ms. Total solver calls (SAT/UNSAT): 5514(783/4731)
Jun 02, 2018 6:37:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(58/434) took 13930 ms. Total solver calls (SAT/UNSAT): 6050(975/5075)
Jun 02, 2018 6:37:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/434) took 17143 ms. Total solver calls (SAT/UNSAT): 6480(1275/5205)
Jun 02, 2018 6:38:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/434) took 21036 ms. Total solver calls (SAT/UNSAT): 6894(1559/5335)
Jun 02, 2018 6:38:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/434) took 24643 ms. Total solver calls (SAT/UNSAT): 7194(1761/5433)
Jun 02, 2018 6:38:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(74/434) took 28471 ms. Total solver calls (SAT/UNSAT): 7674(2079/5595)
Jun 02, 2018 6:38:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(78/434) took 31916 ms. Total solver calls (SAT/UNSAT): 8040(2315/5725)
Jun 02, 2018 6:38:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/434) took 34977 ms. Total solver calls (SAT/UNSAT): 8475(2587/5888)
Jun 02, 2018 6:38:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/434) took 38309 ms. Total solver calls (SAT/UNSAT): 9042(2939/6103)
Jun 02, 2018 6:38:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(95/434) took 41481 ms. Total solver calls (SAT/UNSAT): 9417(3161/6256)
Jun 02, 2018 6:38:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(102/434) took 45088 ms. Total solver calls (SAT/UNSAT): 9900(3431/6469)
Jun 02, 2018 6:38:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(109/434) took 48109 ms. Total solver calls (SAT/UNSAT): 10334(3651/6683)
Jun 02, 2018 6:38:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/434) took 51181 ms. Total solver calls (SAT/UNSAT): 10964(3933/7031)
Jun 02, 2018 6:38:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(174/434) took 54184 ms. Total solver calls (SAT/UNSAT): 12032(4103/7929)
Jun 02, 2018 6:38:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(379/434) took 57185 ms. Total solver calls (SAT/UNSAT): 13947(4143/9804)
Jun 02, 2018 6:38:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 57793 ms. Total solver calls (SAT/UNSAT): 14365(4151/10214)
Jun 02, 2018 6:38:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 434 transitions.
Jun 02, 2018 6:38:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 35 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 6:38:38 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 60825ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DiscoveryGPU-PT-14b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DiscoveryGPU-PT-14b.tgz
mv DiscoveryGPU-PT-14b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DiscoveryGPU-PT-14b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r284-csrt-152749174700159"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;