Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 2.7M
-rw-r--r-- 1 mcc users 2.9K May 29 17:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 15K May 29 17:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 28 12:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 28 12:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 28 09:33 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:33 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 28 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 12K May 28 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.4K May 27 05:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 27 05:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 107 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 345 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 26 06:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 26 06:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 3 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 2.5M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DLCflexbar-PT-3b, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149900395
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-3b-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1528018419451

Flatten gal took : 1520 ms
Constant places removed 1 places and 1 transitions.
Performed 4588 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 4589 rules applied. Total rules applied 4589 place count 7244 transition count 5966
Constant places removed 4589 places and 1 transitions.
Reduce isomorphic transitions removed 105 transitions.
Performed 100 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 4794 rules applied. Total rules applied 9383 place count 2655 transition count 5760
Constant places removed 100 places and 0 transitions.
Reduce isomorphic transitions removed 30 transitions.
Performed 30 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 160 rules applied. Total rules applied 9543 place count 2555 transition count 5700
Constant places removed 30 places and 0 transitions.
Iterating post reduction 3 with 30 rules applied. Total rules applied 9573 place count 2525 transition count 5700
Performed 30 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 30 Pre rules applied. Total rules applied 9573 place count 2525 transition count 5670
Constant places removed 30 places and 0 transitions.
Iterating post reduction 4 with 30 rules applied. Total rules applied 9603 place count 2495 transition count 5670
Symmetric choice reduction at 5 with 475 rule applications. Total rules 10078 place count 2495 transition count 5670
Constant places removed 475 places and 475 transitions.
Iterating post reduction 5 with 475 rules applied. Total rules applied 10553 place count 2020 transition count 5195
Performed 15 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 6 with 15 Pre rules applied. Total rules applied 10553 place count 2020 transition count 5180
Constant places removed 15 places and 0 transitions.
Iterating post reduction 6 with 15 rules applied. Total rules applied 10568 place count 2005 transition count 5180
Symmetric choice reduction at 7 with 35 rule applications. Total rules 10603 place count 2005 transition count 5180
Constant places removed 35 places and 320 transitions.
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 7 with 65 rules applied. Total rules applied 10668 place count 1970 transition count 4830
Performed 585 Post agglomeration using F-continuation condition.
Constant places removed 585 places and 0 transitions.
Iterating post reduction 8 with 585 rules applied. Total rules applied 11253 place count 1385 transition count 4240
Symmetric choice reduction at 9 with 20 rule applications. Total rules 11273 place count 1385 transition count 4240
Constant places removed 20 places and 680 transitions.
Iterating post reduction 9 with 20 rules applied. Total rules applied 11293 place count 1365 transition count 3560
Performed 101 Post agglomeration using F-continuation condition.
Constant places removed 101 places and 0 transitions.
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 10 with 126 rules applied. Total rules applied 11419 place count 1264 transition count 3989
Performed 29 Post agglomeration using F-continuation condition.
Constant places removed 29 places and 0 transitions.
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 11 with 39 rules applied. Total rules applied 11458 place count 1235 transition count 4235
Applied a total of 11458 rules in 10696 ms. Remains 1235 /7245 variables (removed 6010) and now considering 4235/10555 (removed 6320) transitions.
Normalized transition count is 3881
// Phase 1: matrix 3881 rows 1235 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 67710 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 97 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 1 ordering constraints for composite.
built 3330 ordering constraints for composite.
built 3024 ordering constraints for composite.
built 2718 ordering constraints for composite.
built 2412 ordering constraints for composite.
built 2106 ordering constraints for composite.
built 1800 ordering constraints for composite.
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terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 03, 2018 9:33:41 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 03, 2018 9:33:41 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 03, 2018 9:33:42 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 514 ms
Jun 03, 2018 9:33:42 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 7245 places.
Jun 03, 2018 9:33:42 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 10555 transitions.
Jun 03, 2018 9:33:42 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 03, 2018 9:33:44 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1511 ms
Jun 03, 2018 9:33:44 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 111 ms
Jun 03, 2018 9:33:45 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 10555 transitions.
Jun 03, 2018 9:33:58 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 4235 transitions.
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (4235) to apply POR reductions. Disabling POR matrices.
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 481 ms
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 603ms conformant to PINS in folder :/home/mcc/execution
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 414 ms
Jun 03, 2018 9:33:59 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 03, 2018 9:34:00 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 444 ms
Jun 03, 2018 9:34:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 03, 2018 9:46:56 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 5615 redundant transitions.
Jun 03, 2018 9:46:58 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 978 ms
ITS-tools command line returned an error code 134

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-3b"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-3b.tgz
mv DLCflexbar-PT-3b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DLCflexbar-PT-3b, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149900395"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;