Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 232K
-rw-r--r-- 1 mcc users 3.7K May 29 16:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 29 16:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 28 11:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 28 11:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.2K May 28 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.8K May 28 07:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.6K May 27 05:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 114 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 352 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 26 06:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 26 06:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 3 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 63K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is BusinessProcesses-PT-03, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149700206
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BusinessProcesses-PT-03-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527910820312

Flatten gal took : 141 ms
Constant places removed 4 places and 2 transitions.
Performed 195 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 199 rules applied. Total rules applied 199 place count 270 transition count 40
Constant places removed 209 places and 2 transitions.
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 211 rules applied. Total rules applied 410 place count 61 transition count 36
Constant places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 412 place count 59 transition count 36
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 1 places and 0 transitions.
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 414 place count 58 transition count 34
Applied a total of 414 rules in 66 ms. Remains 58 /274 variables (removed 216) and now considering 34/237 (removed 203) transitions.
// Phase 1: matrix 34 rows 58 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 34 rows 58 cols
invariant :p164 + p165 = 1
invariant :p15 + p213 = 1
invariant :p169 + p170 = 1
invariant :p70 + p257 = 1
invariant :p174 + p175 = 1
invariant :p88 + p269 = 1
invariant :p194 + p195 = 1
invariant :p144 + p145 = 1
invariant :p189 + p190 = 1
invariant :p179 + p180 = 1
invariant :p129 + p130 = 1
invariant :p184 + p185 = 1
invariant :p64 + p253 = 1
invariant :p57 + p249 = 1
invariant :p22 + p218 = 1
invariant :p149 + p150 = 1
invariant :p76 + p261 = 1
invariant :p82 + p265 = 1
invariant :p119 + p120 = 1
invariant :p134 + p135 = 1
invariant :p154 + p155 = 1
invariant :p50 + p243 = 1
invariant :p28 + p226 = 1
invariant :p37 + p231 = 1
invariant :p43 + p237 = 1
invariant :p159 + p160 = 1
invariant :p124 + p125 = 1
invariant :p139 + p140 = 1
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 1 ordering constraints for composite.
built 32 ordering constraints for composite.
built 31 ordering constraints for composite.
built 30 ordering constraints for composite.
built 32 ordering constraints for composite.
built 30 ordering constraints for composite.
built 28 ordering constraints for composite.
built 26 ordering constraints for composite.
built 24 ordering constraints for composite.
built 22 ordering constraints for composite.
built 20 ordering constraints for composite.
built 18 ordering constraints for composite.
built 16 ordering constraints for composite.
built 14 ordering constraints for composite.
built 12 ordering constraints for composite.
built 10 ordering constraints for composite.
built 8 ordering constraints for composite.
built 6 ordering constraints for composite.
built 4 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,48,0.054214,5684,237,105,1758,163,323,4199,81,428,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,18,0.066767,5684,87,18,1758,828,835,4199,285,2564,1690

System contains 18 deadlocks (shown below if less than --print-limit option) !
FORMULA BusinessProcesses-PT-03-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 18 states ] showing 10 first states
[ u60={[ ]
} i0={[ i1={[ u59={[ p195=1 ]
} i0={[ u58={[ p190=1 ]
} i0={[ u57={[ p185=1 ]
} i0={[ u56={[ p180=1 ]
} i0={[ u55={[ p175=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} i0={[ u28={[ ]
[ p101=1 ]
} i0={[ u26={[ p88=1 ]
} u25={[ p82=1 ]
} u24={[ p76=1 ]
} u23={[ p70=1 ]
} u22={[ p64=1 ]
} u21={[ p57=1 ]
} u20={[ p50=1 ]
} u19={[ p43=1 ]
} u18={[ p37=1 ]
} u17={[ p28=1 ]
} u16={[ p22=1 ]
} u15={[ p15=1 ]
} ]
} ]
} ]
[ i1={[ u59={[ p194=1 ]
} i0={[ u58={[ p190=1 ]
} i0={[ u57={[ p185=1 ]
} i0={[ u56={[ p180=1 ]
} i0={[ u55={[ p175=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u59={[ p195=1 ]
} i0={[ u58={[ p189=1 ]
} i0={[ u57={[ p185=1 ]
} i0={[ u56={[ p180=1 ]
} i0={[ u55={[ p175=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u58={[ p190=1 ]
} i0={[ u57={[ p184=1 ]
} i0={[ u56={[ p180=1 ]
} i0={[ u55={[ p175=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u57={[ p185=1 ]
} i0={[ u56={[ p179=1 ]
} i0={[ u55={[ p175=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u56={[ p180=1 ]
} i0={[ u55={[ p174=1 ]
} i0={[ u54={[ p170=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u55={[ p175=1 ]
} i0={[ u54={[ p169=1 ]
} i0={[ u53={[ p165=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u54={[ p170=1 ]
} i0={[ u53={[ p164=1 ]
} i0={[ u52={[ p160=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
[ u53={[ p165=1 ]
} i0={[ u52={[ p159=1 ]
} i0={[ u51={[ p155=1 ]
} i0={[ u50={[ p150=1 ]
} i0={[ u49={[ p145=1 ]
} i0={[ u48={[ p140=1 ]
} i0={[ u47={[ p135=1 ]
} i0={[ u46={[ p130=1 ]
} i0={[ u45={[ p125=1 ]
} u44={[ p120=1 ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} ]
} i0={[ u28={[ ]
} i0={[ u26={[ p88=1 ]
} u25={[ p82=1 ]
} u24={[ p76=1 ]
} u23={[ p70=1 ]
} u22={[ p64=1 ]
} u21={[ p57=1 ]
} u20={[ p50=1 ]
} u19={[ p43=1 ]
} u18={[ p37=1 ]
} u17={[ p28=1 ]
} u16={[ p22=1 ]
} u15={[ p15=1 ]
} ]
} ]
} ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527910825316

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 3:40:22 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 02, 2018 3:40:22 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 3:40:22 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 114 ms
Jun 02, 2018 3:40:22 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 274 places.
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 237 transitions.
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 02, 2018 3:40:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 24 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 134 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 8 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 237 transitions.
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 16 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 15 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 34 transitions.
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 15 ms
Jun 02, 2018 3:40:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 3:40:24 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 13 redundant transitions.
Jun 02, 2018 3:40:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 28 place invariants in 8 ms
Jun 02, 2018 3:40:24 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 7 ms
Jun 02, 2018 3:40:24 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Failed to check-sat")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 02, 2018 3:40:24 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 278ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BusinessProcesses-PT-03"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BusinessProcesses-PT-03.tgz
mv BusinessProcesses-PT-03 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is BusinessProcesses-PT-03, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149700206"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;