Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 3.4K May 29 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 29 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 28 11:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 11:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 28 09:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 28 09:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 28 07:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.3K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.3K May 26 06:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 06:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 1.2M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-08b, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149600143
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-08b-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527852551697

Flatten gal took : 925 ms
Constant places removed 1 places and 1 transitions.
Performed 1696 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 1697 rules applied. Total rules applied 1697 place count 3617 transition count 2762
Constant places removed 1806 places and 2 transitions.
Reduce isomorphic transitions removed 28 transitions.
Implicit places reduction removed 16 places :[p3347, p3219, p2824, p2798, p2429, p2403, p2034, p2008, p1639, p1613, p1244, p1218, p849, p823, p454, p428]
Performed 108 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 1958 rules applied. Total rules applied 3655 place count 1795 transition count 2624
Constant places removed 124 places and 0 transitions.
Performed 40 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 164 rules applied. Total rules applied 3819 place count 1671 transition count 2584
Constant places removed 40 places and 0 transitions.
Implicit places reduction removed 15 places :[p3188, p3174, p2793, p2779, p2398, p2384, p2003, p1989, p1608, p1594, p1213, p1199, p818, p804, p409]
Performed 15 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 70 rules applied. Total rules applied 3889 place count 1616 transition count 2569
Constant places removed 15 places and 0 transitions.
Iterating post reduction 4 with 15 rules applied. Total rules applied 3904 place count 1601 transition count 2569
Performed 245 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 5 with 245 Pre rules applied. Total rules applied 3904 place count 1601 transition count 2324
Constant places removed 246 places and 0 transitions.
Implicit places reduction removed 1 places :[p423]
Performed 1 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 248 rules applied. Total rules applied 4152 place count 1354 transition count 2323
Constant places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 4153 place count 1353 transition count 2323
Performed 1 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 4153 place count 1353 transition count 2322
Constant places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 4154 place count 1352 transition count 2322
Symmetric choice reduction at 8 with 29 rule applications. Total rules 4183 place count 1352 transition count 2322
Constant places removed 29 places and 29 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 1 places :[p3617]
Performed 11 Post agglomeration using F-continuation condition.
Iterating post reduction 8 with 42 rules applied. Total rules applied 4225 place count 1322 transition count 2281
Constant places removed 12 places and 0 transitions.
Iterating post reduction 9 with 12 rules applied. Total rules applied 4237 place count 1310 transition count 2281
Symmetric choice reduction at 10 with 18 rule applications. Total rules 4255 place count 1310 transition count 2281
Constant places removed 18 places and 66 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 9 places :[p3356, p3160, p2765, p2370, p1975, p1580, p1185, p790, p395]
Performed 19 Post agglomeration using F-continuation condition.
Iterating post reduction 10 with 47 rules applied. Total rules applied 4302 place count 1283 transition count 2195
Constant places removed 19 places and 0 transitions.
Iterating post reduction 11 with 19 rules applied. Total rules applied 4321 place count 1264 transition count 2195
Symmetric choice reduction at 12 with 9 rule applications. Total rules 4330 place count 1264 transition count 2195
Constant places removed 9 places and 16 transitions.
Iterating post reduction 12 with 9 rules applied. Total rules applied 4339 place count 1255 transition count 2179
Symmetric choice reduction at 13 with 1 rule applications. Total rules 4340 place count 1255 transition count 2179
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 4341 place count 1254 transition count 2171
Symmetric choice reduction at 14 with 1 rule applications. Total rules 4342 place count 1254 transition count 2171
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 4343 place count 1253 transition count 2163
Symmetric choice reduction at 15 with 1 rule applications. Total rules 4344 place count 1253 transition count 2163
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 4345 place count 1252 transition count 2155
Symmetric choice reduction at 16 with 1 rule applications. Total rules 4346 place count 1252 transition count 2155
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 4347 place count 1251 transition count 2147
Symmetric choice reduction at 17 with 1 rule applications. Total rules 4348 place count 1251 transition count 2147
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 4349 place count 1250 transition count 2139
Symmetric choice reduction at 18 with 1 rule applications. Total rules 4350 place count 1250 transition count 2139
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 4351 place count 1249 transition count 2131
Symmetric choice reduction at 19 with 1 rule applications. Total rules 4352 place count 1249 transition count 2131
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 4353 place count 1248 transition count 2123
Symmetric choice reduction at 20 with 1 rule applications. Total rules 4354 place count 1248 transition count 2123
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 4355 place count 1247 transition count 2115
Symmetric choice reduction at 21 with 1 rule applications. Total rules 4356 place count 1247 transition count 2115
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 4357 place count 1246 transition count 2107
Symmetric choice reduction at 22 with 1 rule applications. Total rules 4358 place count 1246 transition count 2107
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 4359 place count 1245 transition count 2099
Symmetric choice reduction at 23 with 1 rule applications. Total rules 4360 place count 1245 transition count 2099
Constant places removed 1 places and 8 transitions.
Iterating post reduction 23 with 1 rules applied. Total rules applied 4361 place count 1244 transition count 2091
Symmetric choice reduction at 24 with 1 rule applications. Total rules 4362 place count 1244 transition count 2091
Constant places removed 1 places and 8 transitions.
Iterating post reduction 24 with 1 rules applied. Total rules applied 4363 place count 1243 transition count 2083
Symmetric choice reduction at 25 with 1 rule applications. Total rules 4364 place count 1243 transition count 2083
Constant places removed 1 places and 8 transitions.
Iterating post reduction 25 with 1 rules applied. Total rules applied 4365 place count 1242 transition count 2075
Symmetric choice reduction at 26 with 1 rule applications. Total rules 4366 place count 1242 transition count 2075
Constant places removed 1 places and 8 transitions.
Iterating post reduction 26 with 1 rules applied. Total rules applied 4367 place count 1241 transition count 2067
Symmetric choice reduction at 27 with 1 rule applications. Total rules 4368 place count 1241 transition count 2067
Constant places removed 1 places and 8 transitions.
Iterating post reduction 27 with 1 rules applied. Total rules applied 4369 place count 1240 transition count 2059
Performed 89 Post agglomeration using F-continuation condition.
Constant places removed 89 places and 0 transitions.
Iterating post reduction 28 with 89 rules applied. Total rules applied 4458 place count 1151 transition count 1962
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 1 places and 0 transitions.
Iterating post reduction 29 with 1 rules applied. Total rules applied 4459 place count 1150 transition count 1971
Applied a total of 4459 rules in 3853 ms. Remains 1150 /3618 variables (removed 2468) and now considering 1971/4459 (removed 2488) transitions.
// Phase 1: matrix 1971 rows 1150 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 3 ordering constraints for composite.
built 1851 ordering constraints for composite.
built 1594 ordering constraints for composite.
built 1386 ordering constraints for composite.
built 1178 ordering constraints for composite.
built 970 ordering constraints for composite.
built 762 ordering constraints for composite.
built 554 ordering constraints for composite.
built 346 ordering constraints for composite.
built 140 ordering constraints for composite.
built 138 ordering constraints for composite.
built 336 ordering constraints for composite.
built 336 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 342 ordering constraints for composite.
built 391 ordering constraints for composite.
built 391 ordering constraints for composite.
built 293 ordering constraints for composite.
built 266 ordering constraints for composite.
built 264 ordering constraints for composite.
built 255 ordering constraints for composite.
built 111 ordering constraints for composite.
built 5 ordering constraints for composite.
Compilation finished in 29189 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 71 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 11:29:13 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 01, 2018 11:29:13 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 11:29:14 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 351 ms
Jun 01, 2018 11:29:14 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3618 places.
Jun 01, 2018 11:29:14 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 4459 transitions.
Jun 01, 2018 11:29:14 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 11:29:15 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 918 ms
Jun 01, 2018 11:29:15 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 71 ms
Jun 01, 2018 11:29:16 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 4459 transitions.
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1971 transitions.
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1971) to apply POR reductions. Disabling POR matrices.
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 328 ms
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 425ms conformant to PINS in folder :/home/mcc/execution
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 270 ms
Jun 01, 2018 11:29:22 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 11:29:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 230 ms
Jun 01, 2018 11:29:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 11:29:32 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2706 redundant transitions.
Jun 01, 2018 11:29:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 95 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-08b"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-08b.tgz
mv ASLink-PT-08b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-08b, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149600143"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;