Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......................
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 3.1K May 29 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 29 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 28 11:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 28 11:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 28 09:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K May 28 07:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.9K May 27 05:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 27 05:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.3K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 436K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-04a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149500062
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-04a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527782817555

Flatten gal took : 803 ms
Constant places removed 17 places and 1 transitions.
Reduce isomorphic transitions removed 16 transitions.
Implicit places reduction removed 8 places :[p873, p806, p611, p599, p416, p404, p221, p209]
Performed 181 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 222 rules applied. Total rules applied 222 place count 991 transition count 1356
Constant places removed 224 places and 0 transitions.
Performed 14 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 238 rules applied. Total rules applied 460 place count 767 transition count 1342
Constant places removed 15 places and 0 transitions.
Implicit places reduction removed 5 places :[p783, p588, p393, p206, p199]
Performed 5 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 25 rules applied. Total rules applied 485 place count 747 transition count 1337
Constant places removed 5 places and 0 transitions.
Iterating post reduction 3 with 5 rules applied. Total rules applied 490 place count 742 transition count 1337
Performed 16 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 16 Pre rules applied. Total rules applied 490 place count 742 transition count 1321
Constant places removed 16 places and 0 transitions.
Iterating post reduction 4 with 16 rules applied. Total rules applied 506 place count 726 transition count 1321
Symmetric choice reduction at 5 with 11 rule applications. Total rules 517 place count 726 transition count 1321
Constant places removed 11 places and 39 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 7 places :[p1015, p876, p774, p579, p384, p190, p23]
Performed 8 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 28 rules applied. Total rules applied 545 place count 708 transition count 1272
Constant places removed 8 places and 0 transitions.
Iterating post reduction 6 with 8 rules applied. Total rules applied 553 place count 700 transition count 1272
Symmetric choice reduction at 7 with 5 rule applications. Total rules 558 place count 700 transition count 1272
Constant places removed 5 places and 12 transitions.
Iterating post reduction 7 with 5 rules applied. Total rules applied 563 place count 695 transition count 1260
Symmetric choice reduction at 8 with 1 rule applications. Total rules 564 place count 695 transition count 1260
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 565 place count 694 transition count 1252
Symmetric choice reduction at 9 with 1 rule applications. Total rules 566 place count 694 transition count 1252
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 567 place count 693 transition count 1244
Symmetric choice reduction at 10 with 1 rule applications. Total rules 568 place count 693 transition count 1244
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 569 place count 692 transition count 1236
Symmetric choice reduction at 11 with 1 rule applications. Total rules 570 place count 692 transition count 1236
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 571 place count 691 transition count 1228
Symmetric choice reduction at 12 with 1 rule applications. Total rules 572 place count 691 transition count 1228
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 573 place count 690 transition count 1220
Symmetric choice reduction at 13 with 1 rule applications. Total rules 574 place count 690 transition count 1220
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 575 place count 689 transition count 1212
Symmetric choice reduction at 14 with 1 rule applications. Total rules 576 place count 689 transition count 1212
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 577 place count 688 transition count 1204
Symmetric choice reduction at 15 with 1 rule applications. Total rules 578 place count 688 transition count 1204
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 579 place count 687 transition count 1196
Symmetric choice reduction at 16 with 1 rule applications. Total rules 580 place count 687 transition count 1196
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 581 place count 686 transition count 1188
Symmetric choice reduction at 17 with 1 rule applications. Total rules 582 place count 686 transition count 1188
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 583 place count 685 transition count 1180
Symmetric choice reduction at 18 with 1 rule applications. Total rules 584 place count 685 transition count 1180
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 585 place count 684 transition count 1172
Symmetric choice reduction at 19 with 1 rule applications. Total rules 586 place count 684 transition count 1172
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 587 place count 683 transition count 1164
Symmetric choice reduction at 20 with 1 rule applications. Total rules 588 place count 683 transition count 1164
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 589 place count 682 transition count 1156
Symmetric choice reduction at 21 with 1 rule applications. Total rules 590 place count 682 transition count 1156
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 591 place count 681 transition count 1148
Symmetric choice reduction at 22 with 1 rule applications. Total rules 592 place count 681 transition count 1148
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 593 place count 680 transition count 1140
Performed 13 Post agglomeration using F-continuation condition.
Constant places removed 13 places and 0 transitions.
Iterating post reduction 23 with 13 rules applied. Total rules applied 606 place count 667 transition count 1127
Applied a total of 606 rules in 973 ms. Remains 667 /1016 variables (removed 349) and now considering 1127/1554 (removed 427) transitions.
// Phase 1: matrix 1127 rows 667 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1127 rows 667 cols
invariant :-1'p38 + -1'p40 + -1'p42 + -1'p44 + -1'p46 + -1'p48 + -1'p50 + -1'p52 + p268 + p270 + p272 + p274 + p276 + p278 + p280 + p282 = 0
invariant :p487 + p489 + p490 + -1'p491 + -1'p492 + -1'p493 + -1'p494 + -1'p495 + -1'p496 + -1'p497 + -1'p498 + -1'p499 + -1'p500 + p534 + p556 + p576 + p618 = 1
invariant :p943 + p944 + p945 + -1'p946 + -1'p947 + -1'p948 = 0
invariant :p22 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p445 + p447 + p449 + p451 + p453 + p455 + p457 + p459 + p489 + p523 + p545 + p565 + p600 + p603 + -1'p605 + -1'p608 + p789 = 1
invariant :p812 + p813 = 1
invariant :p903 + p904 + p905 + -1'p908 + -1'p909 + -1'p910 = 0
invariant :-1'p594 + p597 + p598 + p603 + -1'p605 + -1'p608 + p789 = 0
invariant :p755 + p757 + p758 + p760 + p761 + -1'p762 + -1'p763 + -1'p771 = 0
invariant :-1'p622 + -1'p624 + -1'p626 + -1'p628 + -1'p630 + -1'p632 + -1'p634 + -1'p636 + p816 + p818 + p820 + p822 + p824 + p826 + p828 + p830 = 0
invariant :p461 + p481 = 1
invariant :p852 + p855 + p856 + p857 + p858 + p859 + p860 + p861 + p862 + p863 + p864 + p865 + p866 + p867 + p868 + p869 + p870 + p871 + p896 + p897 + -1'p901 + -1'p902 + p904 + p905 + -1'p909 + -1'p910 + p912 + p913 + -1'p915 + -1'p916 + p918 + p919 + -1'p921 + -1'p922 + p924 + p925 + -1'p927 + -1'p928 + -1'p929 + p932 + p936 + p937 + -1'p941 + -1'p942 + p944 + p945 + -1'p947 + -1'p948 + -1'p949 + p952 + p956 + p957 + -1'p961 + -1'p962 + -1'p963 + p966 = 0
invariant :p996 + p997 + -1'p1000 + -1'p1001 + -1'p1002 = 0
invariant :p72 + p92 = 1
invariant :p621 + p622 + p623 + p624 + p625 + p626 + p627 + p628 + p629 + p630 + p631 + p632 + p633 + p634 + p635 + p636 + p637 + -1'p680 + -1'p686 + -1'p687 + -1'p688 + -1'p690 + -1'p692 + -1'p694 + -1'p720 + -1'p721 + -1'p742 + -1'p743 + -1'p762 + -1'p763 + -1'p777 + p813 = 1
invariant :p640 + p642 + p644 + p646 + p648 + p650 + p652 + p654 + p794 + p795 + p802 + p803 + p804 = 1
invariant :p788 + p789 = 1
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + p409 + p410 + p411 = 0
invariant :p877 + p879 + p880 + p881 + p882 + p883 + p884 + p885 + p886 = 1
invariant :p917 + p918 + p919 + -1'p920 + -1'p921 + -1'p922 = 0
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + p214 + p215 + p216 = 0
invariant :p911 + p912 + p913 + -1'p914 + -1'p915 + -1'p916 = 0
invariant :p969 + p970 + -1'p975 + -1'p976 + -1'p977 = 0
invariant :p849 + p902 + p910 + p916 + p922 + p928 + p934 + p942 + p948 + p954 + p962 + p968 = 1
invariant :p955 + p956 + p957 + -1'p960 + -1'p961 + -1'p962 = 0
invariant :p854 + -1'p905 + -1'p913 + -1'p919 + -1'p925 + -1'p937 + -1'p945 + -1'p957 = 0
invariant :p2 + p4 + p6 + p8 + p10 + p12 + p14 + p16 + p18 + p27 + p30 + p32 + p34 + p74 + p76 + p78 + p80 + p82 + p84 + p86 + p88 = 1
invariant :p874 + p974 + p980 + p986 + p1005 = 1
invariant :p426 + p428 + p430 + p432 + p434 + p436 + p438 + p440 + p442 + -1'p485 + -1'p491 + -1'p492 + -1'p493 + -1'p495 + -1'p497 + -1'p499 + -1'p525 + -1'p526 + -1'p547 + -1'p548 + -1'p567 + -1'p568 + -1'p582 + p618 + p658 + p660 + p662 + p664 + p666 + p668 + p670 + p672 = 1
invariant :p232 + p234 + p236 + p238 + p240 + p242 + p244 + p246 + p462 + p464 + p466 + p468 + p470 + p472 + p474 + p476 + p478 + -1'p481 = 0
invariant :p622 + p624 + p626 + p628 + p630 + p632 + p634 + p636 + p815 + p817 + p819 + p821 + p823 + p825 + p827 + p829 + p831 + -1'p879 + -1'p881 + -1'p883 + -1'p885 + -1'p977 + -1'p983 + -1'p989 + -1'p1002 + -1'p1008 = 0
invariant :p171 + p173 + p174 + p176 + p177 + -1'p178 + -1'p179 + -1'p187 = 0
invariant :p733 + p735 + p736 + p737 + p738 + p740 + p741 + -1'p742 + -1'p743 + -1'p751 = 0
invariant :p972 + p973 + p974 + -1'p975 + -1'p976 + -1'p977 = 0
invariant :-1'p640 + -1'p642 + -1'p644 + -1'p646 + -1'p648 + -1'p650 + -1'p652 + -1'p654 + p799 + p800 + p801 = 0
invariant :p231 + p232 + p233 + p234 + p235 + p236 + p237 + p238 + p239 + p240 + p241 + p242 + p243 + p244 + p245 + p246 + p247 + -1'p290 + -1'p296 + -1'p297 + -1'p298 + -1'p300 + -1'p302 + -1'p304 + -1'p330 + -1'p331 + -1'p352 + -1'p353 + -1'p372 + -1'p373 + -1'p387 + p423 = 1
invariant :-1'p232 + -1'p234 + -1'p236 + -1'p238 + -1'p240 + -1'p242 + -1'p244 + -1'p246 + p463 + p465 + p467 + p469 + p471 + p473 + p475 + p477 = 0
invariant :p1003 + p1004 + p1005 + -1'p1006 + -1'p1007 + -1'p1008 = 0
invariant :p227 + p228 = 1
invariant :p602 + p605 + p608 + -1'p789 = 0
invariant :p91 + p92 + p93 + p96 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + p109 + p110 + p111 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + p197 + p203 + -1'p228 = 0
invariant :p639 + p640 + p641 + p642 + p643 + p644 + p645 + p646 + p647 + p648 + p649 + p650 + p651 + p652 + p653 + p654 + p655 + -1'p709 + -1'p711 + -1'p713 + -1'p715 + -1'p735 + -1'p737 + -1'p757 = 0
invariant :p119 + p145 + p167 + p187 + p228 = 1
invariant :p443 + p514 + p516 + p518 + p520 + p540 + p542 + p562 = 1
invariant :-1'p640 + -1'p642 + -1'p644 + -1'p646 + -1'p648 + -1'p650 + -1'p652 + -1'p654 + -1'p794 + -1'p795 + p797 + p800 + -1'p802 + -1'p804 + p853 + p855 + p857 + p859 + p861 + p863 + p865 + p867 + p869 + p871 + -1'p902 + p905 + -1'p910 + p913 + -1'p916 + p919 + -1'p922 + p925 + -1'p928 + -1'p934 + p937 + -1'p942 + p945 + -1'p948 + -1'p954 + p957 + -1'p962 + -1'p968 = -1
invariant :p21 + -1'p22 + -1'p25 + -1'p29 + -1'p30 + -1'p31 + -1'p32 + -1'p34 + -1'p213 + p215 + p218 + -1'p399 = 0
invariant :p935 + p936 + p937 + -1'p940 + -1'p941 + -1'p942 = 0
invariant :p675 + p676 + p677 + p680 + p686 + p687 + p688 + p689 + p690 + p691 + p692 + p693 + p694 + p695 + p720 + p721 + p742 + p743 + p762 + p763 + p777 + p781 + p787 + -1'p813 = 0
invariant :p638 + p709 + p711 + p713 + p715 + p735 + p737 + p757 = 1
invariant :p229 + p290 + p296 + p297 + p298 + p300 + p302 + p304 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + -1'p423 = 0
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + -1'p294 + p317 + p319 + p320 + p321 + p322 + p323 + p324 + p325 + p326 + p329 + -1'p330 + -1'p331 + -1'p339 + -1'p350 + -1'p370 + -1'p405 + -1'p408 + p410 + p413 + -1'p594 = -1
invariant :p480 + p481 + p482 + p485 + p491 + p492 + p493 + p494 + p495 + p496 + p497 + p498 + p499 + p500 + p525 + p526 + p547 + p548 + p567 + p568 + p582 + p586 + p592 + -1'p618 = 0
invariant :p407 + p410 + p413 + -1'p594 = 0
invariant :p54 + p125 + p127 + p129 + p131 + p151 + p153 + p173 = 1
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p210 + p213 + -1'p215 + p217 + p219 + p399 = 1
invariant :p248 + p319 + p321 + p323 + p325 + p345 + p347 + p367 = 1
invariant :-1'p445 + -1'p447 + -1'p449 + -1'p451 + -1'p453 + -1'p455 + -1'p457 + -1'p459 + p604 + p605 + p606 = 0
invariant :p98 + p100 + p101 + -1'p102 + -1'p103 + -1'p104 + -1'p105 + -1'p106 + -1'p107 + -1'p108 + -1'p109 + -1'p110 + -1'p111 + p145 + p167 + p187 + p228 = 1
invariant :p427 + p429 + p431 + p433 + p435 + p437 + p439 + p441 + -1'p658 + -1'p660 + -1'p662 + -1'p664 + -1'p666 + -1'p668 + -1'p670 + -1'p672 = 0
invariant :p963 + p964 + p965 + -1'p966 + -1'p967 + -1'p968 = 0
invariant :p508 + p534 + p556 + p576 + p618 = 1
invariant :-1'p789 + p792 + p793 + p794 = 0
invariant :p398 + p399 = 1
invariant :p593 + p594 = 1
invariant :p1 + -1'p27 + -1'p30 + -1'p32 + -1'p34 = 0
invariant :p682 + p684 + p685 + -1'p686 + -1'p687 + -1'p688 + -1'p689 + -1'p690 + -1'p691 + -1'p692 + -1'p693 + -1'p694 + -1'p695 + p729 + p751 + p771 + p813 = 1
invariant :-1'p399 + p402 + p403 + p408 + -1'p410 + -1'p413 + p594 = 0
invariant :p617 + p618 = 1
invariant :p851 + -1'p897 + -1'p931 + -1'p951 + -1'p965 = 0
invariant :p560 + p562 + p563 + p565 + p566 + -1'p567 + -1'p568 + -1'p576 = 0
invariant :p285 + p286 + p287 + p290 + p296 + p297 + p298 + p299 + p300 + p301 + p302 + p303 + p304 + p305 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + p391 + p397 + -1'p423 = 0
invariant :p445 + p447 + p449 + p451 + p453 + p455 + p457 + p459 + p600 + p603 + -1'p605 + p607 + p609 + p789 = 1
invariant :p37 + p38 + p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + -1'p96 + -1'p102 + -1'p103 + -1'p104 + -1'p106 + -1'p108 + -1'p110 + -1'p136 + -1'p137 + -1'p158 + -1'p159 + -1'p178 + -1'p179 + -1'p193 + p228 = 1
invariant :p422 + p423 = 1
invariant :-1'p640 + -1'p642 + -1'p644 + -1'p646 + -1'p648 + -1'p650 + -1'p652 + -1'p654 + -1'p684 + p707 + p709 + p710 + p711 + p712 + p713 + p714 + p715 + p716 + p719 + -1'p720 + -1'p721 + -1'p729 + -1'p740 + -1'p760 + -1'p794 + -1'p795 = -1
invariant :p292 + p294 + p295 + -1'p296 + -1'p297 + -1'p298 + -1'p299 + -1'p300 + -1'p301 + -1'p302 + -1'p303 + -1'p304 + -1'p305 + p339 + p361 + p381 + p423 = 1
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p405 + p408 + -1'p410 + p412 + p414 + p594 = 1
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p294 + p328 + p350 + p370 + p405 + p408 + -1'p410 + -1'p413 + p594 = 1
invariant :p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 + p70 + p71 + -1'p125 + -1'p127 + -1'p129 + -1'p131 + -1'p151 + -1'p153 + -1'p173 = 0
invariant :p850 + p853 + -1'p896 + p901 + -1'p904 + p909 + -1'p912 + p915 + -1'p918 + p921 + -1'p924 + p927 + p929 + p931 + -1'p932 + -1'p934 + -1'p936 + p941 + -1'p944 + p947 + p949 + p951 + -1'p952 + -1'p954 + -1'p956 + p961 + p963 + p965 + -1'p966 + -1'p968 = 0
invariant :p424 + p485 + p491 + p492 + p493 + p495 + p497 + p499 + p525 + p526 + p547 + p548 + p567 + p568 + p582 + -1'p618 = 0
invariant :p619 + p680 + p686 + p687 + p688 + p690 + p692 + p694 + p720 + p721 + p742 + p743 + p762 + p763 + p777 + -1'p813 = 0
invariant :p343 + p345 + p346 + p347 + p348 + p350 + p351 + -1'p352 + -1'p353 + -1'p361 = 0
invariant :-1'p445 + -1'p447 + -1'p449 + -1'p451 + -1'p453 + -1'p455 + -1'p457 + -1'p459 + -1'p489 + p512 + p514 + p515 + p516 + p517 + p518 + p519 + p520 + p521 + p524 + -1'p525 + -1'p526 + -1'p534 + -1'p545 + -1'p565 + -1'p600 + -1'p603 + p605 + p608 + -1'p789 = -1
invariant :p949 + p950 + p951 + -1'p952 + -1'p953 + -1'p954 = 0
invariant :p313 + p339 + p361 + p381 + p423 = 1
invariant :p3 + p5 + p7 + p9 + p11 + p13 + p15 + p17 + -1'p74 + -1'p76 + -1'p78 + -1'p80 + -1'p82 + -1'p84 + -1'p86 + -1'p88 = 0
invariant :p204 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p923 + p924 + p925 + -1'p926 + -1'p927 + -1'p928 = 0
invariant :p703 + p729 + p751 + p771 + p813 = 1
invariant :p872 + -1'p974 + -1'p980 + -1'p986 + -1'p1005 = 0
invariant :p266 + p286 = 1
invariant :p895 + p896 + p897 + -1'p900 + -1'p901 + -1'p902 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p100 + p134 + p156 + p176 + p210 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p814 + p879 + p881 + p883 + p885 + p977 + p983 + p989 + p1002 + p1008 = 1
invariant :p657 + p658 + p659 + p660 + p661 + p662 + p663 + p664 + p665 + p666 + p667 + p668 + p669 + p670 + p671 + p672 + p673 + -1'p676 = 0
invariant :p73 + p74 + p75 + p76 + p77 + p78 + p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + p89 + -1'p92 = 0
invariant :p444 + p445 + p446 + p447 + p448 + p449 + p450 + p451 + p452 + p453 + p454 + p455 + p456 + p457 + p458 + p459 + p460 + -1'p514 + -1'p516 + -1'p518 + -1'p520 + -1'p540 + -1'p542 + -1'p562 = 0
invariant :p978 + p979 + p980 + -1'p981 + -1'p982 + -1'p983 = 0
invariant :p20 + p22 + p25 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p879 + p880 + p881 + p882 + p883 + p884 + p885 + p886 + p894 + p900 + p901 + p902 + p908 + p909 + p910 + p914 + p915 + p916 + p920 + p921 + p922 + p926 + p927 + p928 + p932 + p933 + p934 + p940 + p941 + p942 + p946 + p947 + p948 + p952 + p953 + p954 + p960 + p961 + p962 + p966 + p967 + p968 + p975 + p976 + p977 + p981 + p982 + p983 + p987 + p988 + p989 + p1000 + p1001 + p1002 + p1006 + p1007 + p1008 = 1
invariant :p640 + p642 + p644 + p646 + p648 + p650 + p652 + p654 + p795 + p796 + p798 + -1'p800 + p802 + p804 + -1'p853 + -1'p855 + -1'p857 + -1'p859 + -1'p861 + -1'p863 + -1'p865 + -1'p867 + -1'p869 + -1'p871 + p902 + -1'p905 + p910 + -1'p913 + p916 + -1'p919 + p922 + -1'p925 + p928 + p934 + -1'p937 + p942 + -1'p945 + p948 + p954 + -1'p957 + p962 + p968 = 1
invariant :p249 + p250 + p251 + p252 + p253 + p254 + p255 + p256 + p257 + p258 + p259 + p260 + p261 + p262 + p263 + p264 + p265 + -1'p319 + -1'p321 + -1'p323 + -1'p325 + -1'p345 + -1'p347 + -1'p367 = 0
invariant :p538 + p540 + p541 + p542 + p543 + p545 + p546 + -1'p547 + -1'p548 + -1'p556 = 0
invariant :p929 + p930 + p931 + -1'p932 + -1'p933 + -1'p934 = 0
invariant :p640 + p642 + p644 + p646 + p648 + p650 + p652 + p654 + p684 + p718 + p740 + p760 + p794 + p795 = 1
invariant :p149 + p151 + p152 + p153 + p154 + p156 + p157 + -1'p158 + -1'p159 + -1'p167 = 0
invariant :p984 + p985 + p986 + -1'p987 + -1'p988 + -1'p989 = 0
invariant :p38 + p40 + p42 + p44 + p46 + p48 + p50 + p52 + p267 + p269 + p271 + p273 + p275 + p277 + p279 + p281 + p283 + -1'p286 = 0
invariant :p35 + p96 + p102 + p103 + p104 + p106 + p108 + p110 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + -1'p228 = 0
invariant :p656 + p676 = 1
invariant :p365 + p367 + p368 + p370 + p371 + -1'p372 + -1'p373 + -1'p381 = 0
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + -1'p100 + p123 + p125 + p126 + p127 + p128 + p129 + p130 + p131 + p132 + p135 + -1'p136 + -1'p137 + -1'p145 + -1'p156 + -1'p176 + -1'p210 + -1'p213 + p215 + p218 + -1'p399 = -1
invariant :p212 + p215 + p218 + -1'p399 = 0
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 52 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,9.62886e+16,12.5687,304852,4127,586,597182,1832,2026,782657,150,13115,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,1.71905e+11,12.928,304852,985,249,597182,5767,6136,782657,728,15377,96657

System contains 1.71905e+11 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-04a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 171905206675 states ] showing 10 first states
[ u147={[ ]
} u145={[ p849=1 ]
} i35={[ u184={[ ]
} u183={[ ]
} u182={[ ]
} u181={[ ]
} u177={[ ]
} u176={[ ]
} u175={[ ]
} u174={[ ]
} u173={[ ]
} u171={[ ]
} u172={[ ]
} u170={[ ]
} u169={[ ]
} u209={[ p879=1 ]
[ p881=1 ]
} u168={[ ]
} u167={[ ]
} u166={[ ]
} u165={[ ]
} u164={[ ]
} u162={[ ]
} u163={[ ]
} u161={[ ]
} u160={[ ]
} u159={[ ]
} u150={[ ]
} u149={[ ]
} u158={[ ]
} u157={[ ]
} u156={[ ]
} u152={[ ]
} u155={[ ]
} u151={[ ]
} u154={[ ]
} u153={[ ]
} ]
} u146={[ p874=1 ]
} u144={[ p831=1 ]
} u140={[ p804=1 ]
} u110={[ p638=1 ]
} u109={[ p621=1 ]
} i27={[ u136={[ ]
} u134={[ ]
} u128={[ p760=1 ]
} u192={[ ]
} u123={[ ]
} i7={[ u203={[ p763=1 ]
} u132={[ ]
} ]
} i5={[ u204={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u205={[ ]
} u122={[ ]
} ]
} i1={[ u193={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u192={[ ]
} u123={[ ]
} i7={[ u203={[ ]
} u132={[ ]
} ]
} i5={[ u204={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ p684=1 ]
} i3={[ u205={[ ]
} u122={[ ]
} ]
} i1={[ u193={[ p687=1 ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u192={[ ]
} u123={[ ]
} i7={[ u203={[ ]
} u132={[ ]
} ]
} i5={[ u204={[ ]
} u127={[ ]
} ]
} u118={[ p718=1 ]
} u113={[ ]
} i3={[ u205={[ p721=1 ]
} u122={[ ]
} ]
} i1={[ u193={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u192={[ ]
} u123={[ p740=1 ]
} i7={[ u203={[ ]
} u132={[ ]
} ]
} i5={[ u204={[ p743=1 ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u205={[ ]
} u122={[ ]
} ]
} i1={[ u193={[ ]
} u117={[ ]
} ]
} ]
} u143={[ p813=1 ]
} u111={[ p656=1 ]
} u74={[ p426=1 ]
} i28={[ u212={[ ]
} u139={[ p792=1 ]
} u138={[ p789=1 ]
} ]
} u75={[ p443=1 ]
} u105={[ p608=1 ]
} i20={[ u101={[ ]
} u99={[ ]
} u93={[ p565=1 ]
} u188={[ ]
} u88={[ ]
} i7={[ u194={[ p568=1 ]
} u97={[ ]
} ]
} i5={[ u191={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u190={[ ]
} u87={[ ]
} ]
} i1={[ u189={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u188={[ ]
} u88={[ ]
} i7={[ u194={[ ]
} u97={[ ]
} ]
} i5={[ u191={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ p489=1 ]
} i3={[ u190={[ ]
} u87={[ ]
} ]
} i1={[ u189={[ p492=1 ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u188={[ ]
} u88={[ ]
} i7={[ u194={[ ]
} u97={[ ]
} ]
} i5={[ u191={[ ]
} u92={[ ]
} ]
} u83={[ p523=1 ]
} u78={[ ]
} i3={[ u190={[ p526=1 ]
} u87={[ ]
} ]
} i1={[ u189={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u188={[ ]
} u88={[ p545=1 ]
} i7={[ u194={[ ]
} u97={[ ]
} ]
} i5={[ u191={[ p548=1 ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u190={[ ]
} u87={[ ]
} ]
} i1={[ u189={[ ]
} u82={[ ]
} ]
} ]
} u108={[ p618=1 ]
} u76={[ p461=1 ]
} i21={[ u200={[ ]
} u104={[ p597=1 ]
} u103={[ p594=1 ]
} ]
} u39={[ p231=1 ]
} u70={[ p413=1 ]
} u40={[ p248=1 ]
} i14={[ u213={[ ]
} u69={[ p402=1 ]
} u68={[ p399=1 ]
} ]
} i13={[ u66={[ ]
} u64={[ ]
} u58={[ p370=1 ]
} u206={[ ]
} u53={[ ]
} i7={[ u211={[ p373=1 ]
} u62={[ ]
} ]
} i5={[ u210={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u208={[ ]
} u52={[ ]
} ]
} i1={[ u207={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u206={[ ]
} u53={[ ]
} i7={[ u211={[ ]
} u62={[ ]
} ]
} i5={[ u210={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ p294=1 ]
} i3={[ u208={[ ]
} u52={[ ]
} ]
} i1={[ u207={[ p297=1 ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u206={[ ]
} u53={[ ]
} i7={[ u211={[ ]
} u62={[ ]
} ]
} i5={[ u210={[ ]
} u57={[ ]
} ]
} u48={[ p328=1 ]
} u43={[ ]
} i3={[ u208={[ p331=1 ]
} u52={[ ]
} ]
} i1={[ u207={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u206={[ ]
} u53={[ p350=1 ]
} i7={[ u211={[ ]
} u62={[ ]
} ]
} i5={[ u210={[ p353=1 ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u208={[ ]
} u52={[ ]
} ]
} i1={[ u207={[ ]
} u47={[ ]
} ]
} ]
} u73={[ p423=1 ]
} u202={[ ]
} u35={[ p212=1 ]
} u41={[ p266=1 ]
} u3={[ ]
} u5={[ p54=1 ]
} u2={[ p21=1 ]
} u4={[ p37=1 ]
} i6={[ u31={[ ]
} u29={[ ]
} u23={[ p177=1 ]
} u198={[ ]
} u18={[ ]
} i7={[ u201={[ p179=1 ]
} u27={[ ]
} ]
} i5={[ u197={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u195={[ ]
} u17={[ ]
} ]
} i1={[ u199={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u198={[ ]
} u18={[ ]
} i7={[ u201={[ ]
} u27={[ ]
} ]
} i5={[ u197={[ ]
} u22={[ ]
} ]
} u13={[ p135=1 ]
} u8={[ ]
} i3={[ u195={[ p137=1 ]
} u17={[ ]
} ]
} i1={[ u199={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u198={[ ]
} u18={[ ]
} i7={[ u201={[ ]
} u27={[ ]
} ]
} i5={[ u197={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ p101=1 ]
} i3={[ u195={[ ]
} u17={[ ]
} ]
} i1={[ u199={[ p103=1 ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u198={[ ]
} u18={[ p157=1 ]
} i7={[ u201={[ ]
} u27={[ ]
} ]
} i5={[ u197={[ p159=1 ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u195={[ ]
} u17={[ ]
} ]
} i1={[ u199={[ ]
} u12={[ ]
} ]
} ]
} u38={[ p228=1 ]
} u1={[ p2=1 ]
[ p18=1 ]
} u6={[ p72=1 ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527782840714

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 4:07:00 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 4:07:00 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 4:07:00 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 253 ms
May 31, 2018 4:07:00 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1016 places.
May 31, 2018 4:07:01 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1554 transitions.
May 31, 2018 4:07:01 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 4:07:01 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 122 ms
May 31, 2018 4:07:02 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 793 ms
May 31, 2018 4:07:02 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 15 ms
May 31, 2018 4:07:02 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1554 transitions.
May 31, 2018 4:07:05 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 4:07:05 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1127 transitions.
May 31, 2018 4:07:05 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 245 ms
May 31, 2018 4:07:05 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 266 ms
May 31, 2018 4:07:05 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 4:07:05 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 218 ms
May 31, 2018 4:07:05 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 4:07:06 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 114 place invariants in 278 ms
May 31, 2018 4:07:06 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 1564 redundant transitions.
May 31, 2018 4:07:06 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 31 ms
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 667 variables to be positive in 2194 ms
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1127 transitions.
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1127 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 115 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1127 transitions.
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 59 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 4:07:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1127 transitions.
May 31, 2018 4:07:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/1127) took 4244 ms. Total solver calls (SAT/UNSAT): 648(548/100)
May 31, 2018 4:07:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/1127) took 7331 ms. Total solver calls (SAT/UNSAT): 3417(1812/1605)
May 31, 2018 4:07:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/1127) took 10360 ms. Total solver calls (SAT/UNSAT): 6592(4987/1605)
May 31, 2018 4:07:19 PM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (assert (and (>= (select s0 285) 1) (>= (select s0 437) 1))) with error
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:480)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 31, 2018 4:07:19 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 14507ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-04a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-04a.tgz
mv ASLink-PT-04a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-04a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149500062"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;