Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 3.9K May 29 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 29 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 28 11:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 11:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 8.8K May 28 09:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 28 07:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.4K May 27 05:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 27 05:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.4K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 357K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-03a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149500044
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-03a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527766995100

Flatten gal took : 546 ms
Constant places removed 13 places and 1 transitions.
Reduce isomorphic transitions removed 13 transitions.
Implicit places reduction removed 6 places :[p678, p611, p416, p404, p221, p209]
Performed 141 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 173 rules applied. Total rules applied 173 place count 802 transition count 1126
Constant places removed 174 places and 0 transitions.
Performed 11 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 185 rules applied. Total rules applied 358 place count 628 transition count 1115
Constant places removed 12 places and 0 transitions.
Implicit places reduction removed 4 places :[p588, p393, p206, p199]
Performed 4 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 20 rules applied. Total rules applied 378 place count 612 transition count 1111
Constant places removed 4 places and 0 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 382 place count 608 transition count 1111
Performed 12 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 12 Pre rules applied. Total rules applied 382 place count 608 transition count 1099
Constant places removed 12 places and 0 transitions.
Iterating post reduction 4 with 12 rules applied. Total rules applied 394 place count 596 transition count 1099
Symmetric choice reduction at 5 with 9 rule applications. Total rules 403 place count 596 transition count 1099
Constant places removed 9 places and 32 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 6 places :[p820, p681, p579, p384, p190, p23]
Performed 7 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 24 rules applied. Total rules applied 427 place count 581 transition count 1058
Constant places removed 7 places and 0 transitions.
Iterating post reduction 6 with 7 rules applied. Total rules applied 434 place count 574 transition count 1058
Symmetric choice reduction at 7 with 4 rule applications. Total rules 438 place count 574 transition count 1058
Constant places removed 4 places and 11 transitions.
Iterating post reduction 7 with 4 rules applied. Total rules applied 442 place count 570 transition count 1047
Symmetric choice reduction at 8 with 1 rule applications. Total rules 443 place count 570 transition count 1047
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 444 place count 569 transition count 1039
Symmetric choice reduction at 9 with 1 rule applications. Total rules 445 place count 569 transition count 1039
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 446 place count 568 transition count 1031
Symmetric choice reduction at 10 with 1 rule applications. Total rules 447 place count 568 transition count 1031
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 448 place count 567 transition count 1023
Symmetric choice reduction at 11 with 1 rule applications. Total rules 449 place count 567 transition count 1023
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 450 place count 566 transition count 1015
Symmetric choice reduction at 12 with 1 rule applications. Total rules 451 place count 566 transition count 1015
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 452 place count 565 transition count 1007
Symmetric choice reduction at 13 with 1 rule applications. Total rules 453 place count 565 transition count 1007
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 454 place count 564 transition count 999
Symmetric choice reduction at 14 with 1 rule applications. Total rules 455 place count 564 transition count 999
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 456 place count 563 transition count 991
Symmetric choice reduction at 15 with 1 rule applications. Total rules 457 place count 563 transition count 991
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 458 place count 562 transition count 983
Symmetric choice reduction at 16 with 1 rule applications. Total rules 459 place count 562 transition count 983
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 460 place count 561 transition count 975
Symmetric choice reduction at 17 with 1 rule applications. Total rules 461 place count 561 transition count 975
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 462 place count 560 transition count 967
Symmetric choice reduction at 18 with 1 rule applications. Total rules 463 place count 560 transition count 967
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 464 place count 559 transition count 959
Symmetric choice reduction at 19 with 1 rule applications. Total rules 465 place count 559 transition count 959
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 466 place count 558 transition count 951
Symmetric choice reduction at 20 with 1 rule applications. Total rules 467 place count 558 transition count 951
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 468 place count 557 transition count 943
Symmetric choice reduction at 21 with 1 rule applications. Total rules 469 place count 557 transition count 943
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 470 place count 556 transition count 935
Symmetric choice reduction at 22 with 1 rule applications. Total rules 471 place count 556 transition count 935
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 472 place count 555 transition count 927
Performed 10 Post agglomeration using F-continuation condition.
Constant places removed 10 places and 0 transitions.
Iterating post reduction 23 with 10 rules applied. Total rules applied 482 place count 545 transition count 917
Applied a total of 482 rules in 754 ms. Remains 545 /821 variables (removed 276) and now considering 917/1281 (removed 364) transitions.
// Phase 1: matrix 917 rows 545 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 917 rows 545 cols
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 41 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
invariant :p212 + p215 + p218 + -1'p399 = 0
invariant :p659 + -1'p710 + -1'p718 + -1'p724 + -1'p730 + -1'p742 + -1'p750 + -1'p762 = 0
invariant :p119 + p145 + p167 + p187 + p228 = 1
invariant :p654 + p707 + p715 + p721 + p727 + p733 + p739 + p747 + p753 + p759 + p767 + p773 = 1
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p294 + p328 + p350 + p370 + p405 + p408 + -1'p410 + -1'p413 + p594 = 1
invariant :p617 + p618 = 1
invariant :p560 + p562 + p563 + p565 + p566 + -1'p567 + -1'p568 + -1'p576 = 0
invariant :-1'p427 + -1'p429 + -1'p431 + -1'p433 + -1'p435 + -1'p437 + -1'p439 + -1'p441 + p621 + p623 + p625 + p627 + p629 + p631 + p633 + p635 = 0
invariant :p98 + p100 + p101 + -1'p102 + -1'p103 + -1'p104 + -1'p105 + -1'p106 + -1'p107 + -1'p108 + -1'p109 + -1'p110 + -1'p111 + p145 + p167 + p187 + p228 = 1
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p100 + p134 + p156 + p176 + p210 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p266 + p286 = 1
invariant :p722 + p723 + p724 + -1'p725 + -1'p726 + -1'p727 = 0
invariant :p716 + p717 + p718 + -1'p719 + -1'p720 + -1'p721 = 0
invariant :p774 + p775 + -1'p780 + -1'p781 + -1'p782 = 0
invariant :p2 + p4 + p6 + p8 + p10 + p12 + p14 + p16 + p18 + p27 + p30 + p32 + p34 + p74 + p76 + p78 + p80 + p82 + p84 + p86 + p88 = 1
invariant :p249 + p250 + p251 + p252 + p253 + p254 + p255 + p256 + p257 + p258 + p259 + p260 + p261 + p262 + p263 + p264 + p265 + -1'p319 + -1'p321 + -1'p323 + -1'p325 + -1'p345 + -1'p347 + -1'p367 = 0
invariant :p593 + p594 = 1
invariant :p760 + p761 + p762 + -1'p765 + -1'p766 + -1'p767 = 0
invariant :p426 + p427 + p428 + p429 + p430 + p431 + p432 + p433 + p434 + p435 + p436 + p437 + p438 + p439 + p440 + p441 + p442 + -1'p485 + -1'p491 + -1'p492 + -1'p493 + -1'p495 + -1'p497 + -1'p499 + -1'p525 + -1'p526 + -1'p547 + -1'p548 + -1'p567 + -1'p568 + -1'p582 + p618 = 1
invariant :p72 + p92 = 1
invariant :p445 + p447 + p449 + p451 + p453 + p455 + p457 + p459 + p599 + p600 + p607 + p608 + p609 = 1
invariant :-1'p38 + -1'p40 + -1'p42 + -1'p44 + -1'p46 + -1'p48 + -1'p50 + -1'p52 + p268 + p270 + p272 + p274 + p276 + p278 + p280 + p282 = 0
invariant :p171 + p173 + p174 + p176 + p177 + -1'p178 + -1'p179 + -1'p187 = 0
invariant :p149 + p151 + p152 + p153 + p154 + p156 + p157 + -1'p158 + -1'p159 + -1'p167 = 0
invariant :-1'p399 + p402 + p403 + p408 + -1'p410 + -1'p413 + p594 = 0
invariant :p700 + p701 + p702 + -1'p705 + -1'p706 + -1'p707 = 0
invariant :p508 + p534 + p556 + p576 + p618 = 1
invariant :p783 + p784 + p785 + -1'p786 + -1'p787 + -1'p788 = 0
invariant :p684 + p685 + p686 + p687 + p688 + p689 + p690 + p691 + p699 + p705 + p706 + p707 + p713 + p714 + p715 + p719 + p720 + p721 + p725 + p726 + p727 + p731 + p732 + p733 + p737 + p738 + p739 + p745 + p746 + p747 + p751 + p752 + p753 + p757 + p758 + p759 + p765 + p766 + p767 + p771 + p772 + p773 + p780 + p781 + p782 + p786 + p787 + p788 + p792 + p793 + p794 + p805 + p806 + p807 + p811 + p812 + p813 = 1
invariant :p682 + p684 + p685 + p686 + p687 + p688 + p689 + p690 + p691 = 1
invariant :p54 + p125 + p127 + p129 + p131 + p151 + p153 + p173 = 1
invariant :p619 + p684 + p686 + p688 + p690 + p782 + p788 + p794 + p807 + p813 = 1
invariant :p677 + -1'p779 + -1'p785 + -1'p791 + -1'p810 = 0
invariant :p734 + p735 + p736 + -1'p737 + -1'p738 + -1'p739 = 0
invariant :p424 + p485 + p491 + p492 + p493 + p495 + p497 + p499 + p525 + p526 + p547 + p548 + p567 + p568 + p582 + -1'p618 = 0
invariant :p801 + p802 + -1'p805 + -1'p806 + -1'p807 = 0
invariant :p789 + p790 + p791 + -1'p792 + -1'p793 + -1'p794 = 0
invariant :p21 + -1'p22 + -1'p25 + -1'p29 + -1'p30 + -1'p31 + -1'p32 + -1'p34 + -1'p213 + p215 + p218 + -1'p399 = 0
invariant :p204 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p22 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p343 + p345 + p346 + p347 + p348 + p350 + p351 + -1'p352 + -1'p353 + -1'p361 = 0
invariant :p445 + p447 + p449 + p451 + p453 + p455 + p457 + p459 + p602 + -1'p604 + -1'p606 + p608 + p658 + p660 + p662 + p664 + p666 + p668 + p670 + p672 + p674 + p676 + -1'p707 + p710 + -1'p715 + p718 + -1'p721 + p724 + -1'p727 + p730 + -1'p733 + -1'p739 + p742 + -1'p747 + p750 + -1'p753 + -1'p759 + p762 + -1'p767 + -1'p773 = 0
invariant :p292 + p294 + p295 + -1'p296 + -1'p297 + -1'p298 + -1'p299 + -1'p300 + -1'p301 + -1'p302 + -1'p303 + -1'p304 + -1'p305 + p339 + p361 + p381 + p423 = 1
invariant :p38 + p40 + p42 + p44 + p46 + p48 + p50 + p52 + p267 + p269 + p271 + p273 + p275 + p277 + p279 + p281 + p283 + -1'p286 = 0
invariant :p748 + p749 + p750 + -1'p751 + -1'p752 + -1'p753 = 0
invariant :p708 + p709 + p710 + -1'p713 + -1'p714 + -1'p715 = 0
invariant :p445 + p447 + p449 + p451 + p453 + p455 + p457 + p459 + p489 + p523 + p545 + p565 + p599 + p600 = 1
invariant :p487 + p489 + p490 + -1'p491 + -1'p492 + -1'p493 + -1'p494 + -1'p495 + -1'p496 + -1'p497 + -1'p498 + -1'p499 + -1'p500 + p534 + p556 + p576 + p618 = 1
invariant :p461 + p481 = 1
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + p214 + p215 + p216 = 0
invariant :p91 + p92 + p93 + p96 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + p109 + p110 + p111 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + p197 + p203 + -1'p228 = 0
invariant :-1'p445 + -1'p447 + -1'p449 + -1'p451 + -1'p453 + -1'p455 + -1'p457 + -1'p459 + -1'p489 + p512 + p514 + p515 + p516 + p517 + p518 + p519 + p520 + p521 + p524 + -1'p525 + -1'p526 + -1'p534 + -1'p545 + -1'p565 + -1'p599 + -1'p600 = -1
invariant :p398 + p399 = 1
invariant :p656 + -1'p702 + -1'p736 + -1'p756 + -1'p770 = 0
invariant :p422 + p423 = 1
invariant :p37 + p38 + p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + -1'p96 + -1'p102 + -1'p103 + -1'p104 + -1'p106 + -1'p108 + -1'p110 + -1'p136 + -1'p137 + -1'p158 + -1'p159 + -1'p178 + -1'p179 + -1'p193 + p228 = 1
invariant :p1 + -1'p27 + -1'p30 + -1'p32 + -1'p34 = 0
invariant :p754 + p755 + p756 + -1'p757 + -1'p758 + -1'p759 = 0
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + -1'p294 + p317 + p319 + p320 + p321 + p322 + p323 + p324 + p325 + p326 + p329 + -1'p330 + -1'p331 + -1'p339 + -1'p350 + -1'p370 + -1'p405 + -1'p408 + p410 + p413 + -1'p594 = -1
invariant :p227 + p228 = 1
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + -1'p100 + p123 + p125 + p126 + p127 + p128 + p129 + p130 + p131 + p132 + p135 + -1'p136 + -1'p137 + -1'p145 + -1'p156 + -1'p176 + -1'p210 + -1'p213 + p215 + p218 + -1'p399 = -1
invariant :p444 + p445 + p446 + p447 + p448 + p449 + p450 + p451 + p452 + p453 + p454 + p455 + p456 + p457 + p458 + p459 + p460 + -1'p514 + -1'p516 + -1'p518 + -1'p520 + -1'p540 + -1'p542 + -1'p562 = 0
invariant :p232 + p234 + p236 + p238 + p240 + p242 + p244 + p246 + p462 + p464 + p466 + p468 + p470 + p472 + p474 + p476 + p478 + -1'p481 = 0
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p405 + p408 + -1'p410 + p412 + p414 + p594 = 1
invariant :p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 + p70 + p71 + -1'p125 + -1'p127 + -1'p129 + -1'p131 + -1'p151 + -1'p153 + -1'p173 = 0
invariant :-1'p594 + p597 + p598 + p599 = 0
invariant :p655 + p658 + -1'p701 + p706 + -1'p709 + p714 + -1'p717 + p720 + -1'p723 + p726 + -1'p729 + p732 + p734 + p736 + -1'p737 + -1'p739 + -1'p741 + p746 + -1'p749 + p752 + p754 + p756 + -1'p757 + -1'p759 + -1'p761 + p766 + p768 + p770 + -1'p771 + -1'p773 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p210 + p213 + -1'p215 + p217 + p219 + p399 = 1
invariant :-1'p232 + -1'p234 + -1'p236 + -1'p238 + -1'p240 + -1'p242 + -1'p244 + -1'p246 + p463 + p465 + p467 + p469 + p471 + p473 + p475 + p477 = 0
invariant :p35 + p96 + p102 + p103 + p104 + p106 + p108 + p110 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + -1'p228 = 0
invariant :p313 + p339 + p361 + p381 + p423 = 1
invariant :p427 + p429 + p431 + p433 + p435 + p437 + p439 + p441 + p620 + p622 + p624 + p626 + p628 + p630 + p632 + p634 + p636 + -1'p684 + -1'p686 + -1'p688 + -1'p690 + -1'p782 + -1'p788 + -1'p794 + -1'p807 + -1'p813 = 0
invariant :-1'p445 + -1'p447 + -1'p449 + -1'p451 + -1'p453 + -1'p455 + -1'p457 + -1'p459 + -1'p599 + p601 + p603 + p604 + p606 + -1'p608 + -1'p658 + -1'p660 + -1'p662 + -1'p664 + -1'p666 + -1'p668 + -1'p670 + -1'p672 + -1'p674 + -1'p676 + p707 + -1'p710 + p715 + -1'p718 + p721 + -1'p724 + p727 + -1'p730 + p733 + p739 + -1'p742 + p747 + -1'p750 + p753 + p759 + -1'p762 + p767 + p773 = 0
invariant :p728 + p729 + p730 + -1'p731 + -1'p732 + -1'p733 = 0
invariant :-1'p445 + -1'p447 + -1'p449 + -1'p451 + -1'p453 + -1'p455 + -1'p457 + -1'p459 + p604 + p605 + p606 = 0
invariant :p285 + p286 + p287 + p290 + p296 + p297 + p298 + p299 + p300 + p301 + p302 + p303 + p304 + p305 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + p391 + p397 + -1'p423 = 0
invariant :p20 + p22 + p25 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p777 + p778 + p779 + -1'p780 + -1'p781 + -1'p782 = 0
invariant :p248 + p319 + p321 + p323 + p325 + p345 + p347 + p367 = 1
invariant :p443 + p514 + p516 + p518 + p520 + p540 + p542 + p562 = 1
invariant :p3 + p5 + p7 + p9 + p11 + p13 + p15 + p17 + -1'p74 + -1'p76 + -1'p78 + -1'p80 + -1'p82 + -1'p84 + -1'p86 + -1'p88 = 0
invariant :p740 + p741 + p742 + -1'p745 + -1'p746 + -1'p747 = 0
invariant :p538 + p540 + p541 + p542 + p543 + p545 + p546 + -1'p547 + -1'p548 + -1'p556 = 0
invariant :p229 + p290 + p296 + p297 + p298 + p300 + p302 + p304 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + -1'p423 = 0
invariant :p231 + p232 + p233 + p234 + p235 + p236 + p237 + p238 + p239 + p240 + p241 + p242 + p243 + p244 + p245 + p246 + p247 + -1'p290 + -1'p296 + -1'p297 + -1'p298 + -1'p300 + -1'p302 + -1'p304 + -1'p330 + -1'p331 + -1'p352 + -1'p353 + -1'p372 + -1'p373 + -1'p387 + p423 = 1
invariant :p808 + p809 + p810 + -1'p811 + -1'p812 + -1'p813 = 0
invariant :p365 + p367 + p368 + p370 + p371 + -1'p372 + -1'p373 + -1'p381 = 0
invariant :p407 + p410 + p413 + -1'p594 = 0
invariant :p657 + p660 + p661 + p662 + p663 + p664 + p665 + p666 + p667 + p668 + p669 + p670 + p671 + p672 + p673 + p674 + p675 + p676 + p701 + p702 + -1'p706 + -1'p707 + p709 + p710 + -1'p714 + -1'p715 + p717 + p718 + -1'p720 + -1'p721 + p723 + p724 + -1'p726 + -1'p727 + p729 + p730 + -1'p732 + -1'p733 + -1'p734 + p737 + p741 + p742 + -1'p746 + -1'p747 + p749 + p750 + -1'p752 + -1'p753 + -1'p754 + p757 + p761 + p762 + -1'p766 + -1'p767 + -1'p768 + p771 = 0
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + p409 + p410 + p411 = 0
invariant :p73 + p74 + p75 + p76 + p77 + p78 + p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + p89 + -1'p92 = 0
invariant :p480 + p481 + p482 + p485 + p491 + p492 + p493 + p494 + p495 + p496 + p497 + p498 + p499 + p500 + p525 + p526 + p547 + p548 + p567 + p568 + p582 + p586 + p592 + -1'p618 = 0
invariant :p679 + p779 + p785 + p791 + p810 = 1
invariant :p768 + p769 + p770 + -1'p771 + -1'p772 + -1'p773 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,4.16354e+13,8.24388,215088,3435,506,424994,1884,1707,551900,150,11939,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,6.78187e+08,8.47945,215472,898,244,424994,5016,5191,551900,700,12824,69597

System contains 6.78187e+08 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-03a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 678187228 states ] showing 10 first states
[ u112={[ ]
} u110={[ p654=1 ]
} i28={[ u149={[ ]
} u148={[ ]
} u147={[ ]
} u146={[ ]
} u142={[ ]
} u141={[ ]
} u140={[ ]
} u139={[ ]
} u138={[ ]
} u136={[ ]
} u137={[ ]
} u135={[ ]
} u134={[ ]
} u157={[ p688=1 ]
[ p690=1 ]
} u133={[ ]
} u132={[ ]
} u131={[ ]
} u130={[ ]
} u129={[ ]
} u127={[ ]
} u128={[ ]
} u126={[ ]
} u125={[ ]
} u124={[ ]
} u115={[ ]
} u114={[ ]
} u123={[ ]
} u122={[ ]
} u121={[ ]
} u117={[ ]
} u120={[ ]
} u116={[ ]
} u119={[ ]
} u118={[ ]
} ]
} u111={[ p679=1 ]
} u109={[ p636=1 ]
} u105={[ p606=1 ]
} u74={[ p426=1 ]
} u75={[ p445=1 ]
[ p447=1 ]
[ p449=1 ]
[ p451=1 ]
[ p453=1 ]
[ p455=1 ]
[ p457=1 ]
[ p459=1 ]
} i20={[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u153={[ ]
} u88={[ p540=1 ]
[ p542=1 ]
} i7={[ u158={[ ]
} u97={[ ]
} ]
} i5={[ u156={[ p548=1 ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u155={[ ]
} u87={[ ]
} ]
} i1={[ u154={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u153={[ ]
} u88={[ ]
} i7={[ u158={[ ]
} u97={[ ]
} ]
} i5={[ u156={[ ]
} u92={[ ]
} ]
} u83={[ p514=1 ]
[ p516=1 ]
[ p518=1 ]
[ p520=1 ]
} u78={[ ]
} i3={[ u155={[ p526=1 ]
} u87={[ ]
} ]
} i1={[ u154={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ p562=1 ]
} u153={[ ]
} u88={[ ]
} i7={[ u158={[ p568=1 ]
} u97={[ ]
} ]
} i5={[ u156={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u155={[ ]
} u87={[ ]
} ]
} i1={[ u154={[ ]
} u82={[ ]
} ]
} ]
} u108={[ p618=1 ]
} u76={[ p461=1 ]
} i21={[ u164={[ p593=1 ]
} u104={[ ]
} u103={[ ]
} ]
} u39={[ p247=1 ]
} u70={[ p405=1 ]
} u40={[ p248=1 ]
} i13={[ u66={[ ]
} u64={[ p387=1 ]
} u58={[ ]
} u167={[ ]
} u53={[ ]
} i7={[ u171={[ ]
} u62={[ ]
} ]
} i5={[ u170={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u169={[ ]
} u52={[ ]
} ]
} i1={[ u168={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u167={[ ]
} u53={[ ]
} i7={[ u171={[ ]
} u62={[ ]
} ]
} i5={[ u170={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ p292=1 ]
} i3={[ u169={[ ]
} u52={[ ]
} ]
} i1={[ u168={[ p300=1 ]
[ p296=1 ]
[ p302=1 ]
[ p304=1 ]
} u47={[ ]
} ]
} ]
} u73={[ p423=1 ]
} i14={[ u172={[ p398=1 ]
} u69={[ ]
} u68={[ ]
} ]
} u41={[ p266=1 ]
} u166={[ p204=1 ]
} u35={[ p210=1 ]
} u3={[ p22=1 ]
[ p31=1 ]
} u4={[ p53=1 ]
} u2={[ p21=1 ]
} u5={[ p54=1 ]
} i6={[ u31={[ ]
} u29={[ p193=1 ]
} u23={[ ]
} u162={[ ]
} u18={[ ]
} i7={[ u165={[ ]
} u27={[ ]
} ]
} i5={[ u161={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u159={[ ]
} u17={[ ]
} ]
} i1={[ u163={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u162={[ ]
} u18={[ ]
} i7={[ u165={[ ]
} u27={[ ]
} ]
} i5={[ u161={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ p98=1 ]
} i3={[ u159={[ ]
} u17={[ ]
} ]
} i1={[ u163={[ p106=1 ]
[ p102=1 ]
[ p108=1 ]
[ p110=1 ]
} u12={[ ]
} ]
} ]
} u38={[ p228=1 ]
} u1={[ p18=1 ]
} u6={[ p72=1 ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527767011439

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 11:43:17 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 11:43:17 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 11:43:18 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 236 ms
May 31, 2018 11:43:18 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 821 places.
May 31, 2018 11:43:18 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1281 transitions.
May 31, 2018 11:43:18 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 11:43:18 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 46 ms
May 31, 2018 11:43:19 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 540 ms
May 31, 2018 11:43:19 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 10 ms
May 31, 2018 11:43:19 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1281 transitions.
May 31, 2018 11:43:20 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 11:43:21 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 917 transitions.
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 196 ms
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 132 ms
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 122 ms
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 11:43:21 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 1270 redundant transitions.
May 31, 2018 11:43:21 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 21 ms
May 31, 2018 11:43:22 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 94 place invariants in 295 ms
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 545 variables to be positive in 1777 ms
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 917 transitions.
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/917 took 8 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 149 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 917 transitions.
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 48 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 11:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 917 transitions.
May 31, 2018 11:43:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/917) took 3049 ms. Total solver calls (SAT/UNSAT): 771(411/360)
May 31, 2018 11:43:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/917) took 6175 ms. Total solver calls (SAT/UNSAT): 3394(1814/1580)
May 31, 2018 11:43:30 AM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (assert (and (>= (select s0 221) 1) (>= (select s0 233) 1))) with error
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:480)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 31, 2018 11:43:30 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 9622ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-03a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-03a.tgz
mv ASLink-PT-03a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-03a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149500044"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;