Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 584K
-rw-r--r-- 1 mcc users 3.4K May 29 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 29 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 28 11:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 28 11:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 28 09:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 28 07:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.6K May 27 05:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 27 05:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 417K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-02b, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149400035
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-02b-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527762511471

Flatten gal took : 804 ms
Constant places removed 1 places and 1 transitions.
Performed 544 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 545 rules applied. Total rules applied 545 place count 1241 transition count 1076
Constant places removed 576 places and 2 transitions.
Reduce isomorphic transitions removed 10 transitions.
Implicit places reduction removed 4 places :[p971, p843, p448, p422]
Performed 30 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 620 rules applied. Total rules applied 1165 place count 661 transition count 1034
Constant places removed 34 places and 0 transitions.
Performed 10 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 44 rules applied. Total rules applied 1209 place count 627 transition count 1024
Constant places removed 10 places and 0 transitions.
Implicit places reduction removed 3 places :[p812, p798, p403]
Performed 3 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 16 rules applied. Total rules applied 1225 place count 614 transition count 1021
Constant places removed 3 places and 0 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 1228 place count 611 transition count 1021
Performed 101 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 5 with 101 Pre rules applied. Total rules applied 1228 place count 611 transition count 920
Constant places removed 102 places and 0 transitions.
Implicit places reduction removed 1 places :[p417]
Performed 1 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 104 rules applied. Total rules applied 1332 place count 508 transition count 919
Constant places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 1333 place count 507 transition count 919
Performed 1 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 1333 place count 507 transition count 918
Constant places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 1334 place count 506 transition count 918
Symmetric choice reduction at 8 with 11 rule applications. Total rules 1345 place count 506 transition count 918
Constant places removed 11 places and 11 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 1 places :[p1241]
Performed 5 Post agglomeration using F-continuation condition.
Iterating post reduction 8 with 18 rules applied. Total rules applied 1363 place count 494 transition count 901
Constant places removed 6 places and 0 transitions.
Iterating post reduction 9 with 6 rules applied. Total rules applied 1369 place count 488 transition count 901
Symmetric choice reduction at 10 with 6 rule applications. Total rules 1375 place count 488 transition count 901
Constant places removed 6 places and 24 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 3 places :[p980, p784, p389]
Performed 7 Post agglomeration using F-continuation condition.
Iterating post reduction 10 with 17 rules applied. Total rules applied 1392 place count 479 transition count 869
Constant places removed 7 places and 0 transitions.
Iterating post reduction 11 with 7 rules applied. Total rules applied 1399 place count 472 transition count 869
Symmetric choice reduction at 12 with 3 rule applications. Total rules 1402 place count 472 transition count 869
Constant places removed 3 places and 10 transitions.
Iterating post reduction 12 with 3 rules applied. Total rules applied 1405 place count 469 transition count 859
Symmetric choice reduction at 13 with 1 rule applications. Total rules 1406 place count 469 transition count 859
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 1407 place count 468 transition count 851
Symmetric choice reduction at 14 with 1 rule applications. Total rules 1408 place count 468 transition count 851
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 1409 place count 467 transition count 843
Symmetric choice reduction at 15 with 1 rule applications. Total rules 1410 place count 467 transition count 843
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 1411 place count 466 transition count 835
Symmetric choice reduction at 16 with 1 rule applications. Total rules 1412 place count 466 transition count 835
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 1413 place count 465 transition count 827
Symmetric choice reduction at 17 with 1 rule applications. Total rules 1414 place count 465 transition count 827
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 1415 place count 464 transition count 819
Symmetric choice reduction at 18 with 1 rule applications. Total rules 1416 place count 464 transition count 819
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 1417 place count 463 transition count 811
Symmetric choice reduction at 19 with 1 rule applications. Total rules 1418 place count 463 transition count 811
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 1419 place count 462 transition count 803
Symmetric choice reduction at 20 with 1 rule applications. Total rules 1420 place count 462 transition count 803
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 1421 place count 461 transition count 795
Symmetric choice reduction at 21 with 1 rule applications. Total rules 1422 place count 461 transition count 795
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 1423 place count 460 transition count 787
Symmetric choice reduction at 22 with 1 rule applications. Total rules 1424 place count 460 transition count 787
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 1425 place count 459 transition count 779
Symmetric choice reduction at 23 with 1 rule applications. Total rules 1426 place count 459 transition count 779
Constant places removed 1 places and 8 transitions.
Iterating post reduction 23 with 1 rules applied. Total rules applied 1427 place count 458 transition count 771
Symmetric choice reduction at 24 with 1 rule applications. Total rules 1428 place count 458 transition count 771
Constant places removed 1 places and 8 transitions.
Iterating post reduction 24 with 1 rules applied. Total rules applied 1429 place count 457 transition count 763
Symmetric choice reduction at 25 with 1 rule applications. Total rules 1430 place count 457 transition count 763
Constant places removed 1 places and 8 transitions.
Iterating post reduction 25 with 1 rules applied. Total rules applied 1431 place count 456 transition count 755
Symmetric choice reduction at 26 with 1 rule applications. Total rules 1432 place count 456 transition count 755
Constant places removed 1 places and 8 transitions.
Iterating post reduction 26 with 1 rules applied. Total rules applied 1433 place count 455 transition count 747
Symmetric choice reduction at 27 with 1 rule applications. Total rules 1434 place count 455 transition count 747
Constant places removed 1 places and 8 transitions.
Iterating post reduction 27 with 1 rules applied. Total rules applied 1435 place count 454 transition count 739
Performed 29 Post agglomeration using F-continuation condition.
Constant places removed 29 places and 0 transitions.
Iterating post reduction 28 with 29 rules applied. Total rules applied 1464 place count 425 transition count 708
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 1 places and 0 transitions.
Iterating post reduction 29 with 1 rules applied. Total rules applied 1465 place count 424 transition count 717
Applied a total of 1465 rules in 1187 ms. Remains 424 /1242 variables (removed 818) and now considering 717/1621 (removed 904) transitions.
// Phase 1: matrix 717 rows 424 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 717 rows 424 cols
invariant :p127 + p276 + p279 + p282 + p285 + p319 + p322 + p356 = 1
invariant :p524 + p526 + p528 + p529 + p531 + p532 + p534 + p535 + p537 + p538 + p540 + p541 + p543 + p544 + p546 + p547 + p549 + -1'p671 + -1'p674 + -1'p677 + -1'p680 + -1'p714 + -1'p717 + -1'p751 = 0
invariant :p982 + p990 + p992 + p993 + p995 + p996 + p998 + p999 + p1001 = 1
invariant :-1'p1121 + -1'p1122 + -1'p1123 + p1128 + p1129 + p1130 = 0
invariant :p605 + p608 + p610 + p615 + p616 + p627 + p628 + p632 + p633 + p637 + p638 + p641 + p642 + p646 + p647 + p688 + p689 + p725 + p726 + p759 + p760 + p790 + p796 + -1'p866 = 0
invariant :p1226 + p1227 + p1228 + -1'p1230 + -1'p1231 + -1'p1232 = 0
invariant :p932 + -1'p1069 + -1'p1115 + -1'p1142 + -1'p1161 = 0
invariant :p1180 + p1181 + p1182 + -1'p1184 + -1'p1185 + -1'p1186 = 0
invariant :p483 + p615 + p616 + p627 + p628 + p632 + p637 + p641 + p646 + p688 + p689 + p725 + p726 + p759 + p760 + p790 + -1'p866 = 0
invariant :-1'p1148 + -1'p1149 + -1'p1150 + p1155 + p1156 + p1157 = 0
invariant :p470 + p471 = 1
invariant :p210 + p213 + p215 + p220 + p221 + p232 + p233 + p237 + p238 + p242 + p243 + p246 + p247 + p251 + p252 + p293 + p294 + p330 + p331 + p364 + p365 + p395 + p401 + -1'p471 = 0
invariant :p1206 + p1214 + -1'p1222 + -1'p1223 + -1'p1224 = 0
invariant :p88 + p220 + p221 + p232 + p233 + p237 + p242 + p246 + p251 + p293 + p294 + p330 + p331 + p364 + p365 + p395 + -1'p471 = 0
invariant :p621 + p624 + p626 + -1'p627 + -1'p628 + -1'p632 + -1'p633 + -1'p637 + -1'p638 + -1'p641 + -1'p642 + -1'p646 + -1'p647 + p690 + p727 + p761 + p866 = 1
invariant :p1140 + p1141 + p1142 + -1'p1144 + -1'p1145 + -1'p1146 = 0
invariant :-1'p491 + -1'p495 + -1'p499 + -1'p503 + -1'p507 + -1'p511 + -1'p515 + -1'p519 + p877 + p880 + p883 + p886 + p889 + p892 + p895 + p898 = 0
invariant :p969 + -1'p1174 + -1'p1182 + -1'p1190 + -1'p1228 = 0
invariant :p234 + p295 + p332 + p366 + p471 = 1
invariant :p411 + p430 + -1'p434 + -1'p440 + -1'p806 = 0
invariant :-1'p526 + -1'p529 + -1'p532 + -1'p535 + -1'p538 + -1'p541 + -1'p544 + -1'p547 + -1'p624 + p667 + p671 + p673 + p674 + p676 + p677 + p679 + p680 + p682 + p687 + -1'p688 + -1'p689 + -1'p690 + -1'p722 + -1'p756 + -1'p817 + -1'p819 = -1
invariant :p747 + p751 + p753 + p756 + p758 + -1'p759 + -1'p760 + -1'p761 = 0
invariant :p522 + p671 + p674 + p677 + p680 + p714 + p717 + p751 = 1
invariant :p939 + -1'p1080 + -1'p1091 + -1'p1099 + -1'p1107 + -1'p1123 + -1'p1134 + -1'p1150 = 0
invariant :p131 + p134 + p137 + p140 + p143 + p146 + p149 + p152 + p229 + p290 + p327 + p361 + p424 + p430 + -1'p434 + -1'p440 + -1'p806 = 0
invariant :p158 + p160 + p161 + p163 + p164 + p166 + p167 + p169 + p170 + p172 + p173 + p175 + p176 + p178 + p179 + p181 + p182 + -1'p213 = 0
invariant :p526 + p529 + p532 + p535 + p538 + p541 + p544 + p547 + p817 + p819 + p834 + p836 + p837 = 1
invariant :p806 + p808 + p810 + p817 = 1
invariant :p352 + p356 + p358 + p361 + p363 + -1'p364 + -1'p365 + -1'p366 = 0
invariant :p1113 + p1114 + p1115 + -1'p1117 + -1'p1118 + -1'p1119 = 0
invariant :p48 + p52 + p56 + p61 + p68 + p69 + p71 + p73 + p430 + -1'p434 + -1'p440 + -1'p806 = 0
invariant :p1188 + p1189 + p1190 + -1'p1192 + -1'p1193 + -1'p1194 = 0
invariant :p52 + p56 + p61 + p63 + p64 + p66 + p68 + p69 + p71 + p73 + p430 + -1'p434 + -1'p440 + -1'p806 = 0
invariant :-1'p526 + -1'p529 + -1'p532 + -1'p535 + -1'p538 + -1'p541 + -1'p544 + -1'p547 + -1'p824 + p828 + p831 + -1'p836 + p933 + -1'p937 + p942 + p945 + p948 + p951 + p954 + p957 + p960 + p963 + p1068 + p1069 + -1'p1075 + p1079 + -1'p1086 + p1090 + -1'p1094 + p1098 + -1'p1102 + p1106 + -1'p1110 + -1'p1113 + p1117 + p1119 + p1122 + -1'p1129 + p1133 + -1'p1137 + -1'p1140 + p1144 + p1146 + p1149 + -1'p1156 + -1'p1159 + p1163 + p1165 = 0
invariant :p96 + p100 + p104 + p108 + p112 + p116 + p120 + p124 + -1'p555 + -1'p558 + -1'p561 + -1'p564 + -1'p567 + -1'p570 + -1'p573 + -1'p576 = 0
invariant :p155 + p213 = 1
invariant :-1'p1067 + -1'p1068 + -1'p1069 + p1074 + p1075 + p1076 = 0
invariant :p710 + p714 + p716 + p717 + p719 + p722 + p724 + -1'p725 + -1'p726 + -1'p727 = 0
invariant :p526 + p529 + p532 + p535 + p538 + p541 + p544 + p547 + p624 + p685 + p722 + p756 + p817 + p819 = 1
invariant :p824 + p830 + p836 + -1'p933 + p937 + -1'p942 + -1'p945 + -1'p948 + -1'p951 + -1'p954 + -1'p957 + -1'p960 + -1'p963 + -1'p1068 + -1'p1069 + p1075 + -1'p1079 + p1086 + -1'p1090 + p1094 + -1'p1098 + p1102 + -1'p1106 + p1110 + p1113 + -1'p1117 + -1'p1119 + -1'p1122 + p1129 + -1'p1133 + p1137 + p1140 + -1'p1144 + -1'p1146 + -1'p1149 + p1156 + p1159 + -1'p1163 + -1'p1165 = 0
invariant :p1172 + p1173 + p1174 + -1'p1176 + -1'p1177 + -1'p1178 = 0
invariant :p872 + p990 + p993 + p996 + p999 + p1178 + p1186 + p1194 + p1224 + p1232 = 1
invariant :p865 + p866 = 1
invariant :p315 + p319 + p321 + p322 + p324 + p327 + p329 + -1'p330 + -1'p331 + -1'p332 = 0
invariant :p553 + p555 + p556 + p558 + p559 + p561 + p562 + p564 + p565 + p567 + p568 + p570 + p571 + p573 + p574 + p576 + p577 + -1'p608 = 0
invariant :p933 + p934 + p940 + p942 + p943 + p945 + p946 + p948 + p949 + p951 + p952 + p954 + p955 + p957 + p958 + p960 + p961 + p963 + p964 + p1068 + p1069 + -1'p1075 + -1'p1076 + p1079 + p1080 + -1'p1086 + -1'p1087 + p1090 + p1091 + -1'p1094 + -1'p1095 + p1098 + p1099 + -1'p1102 + -1'p1103 + p1106 + p1107 + -1'p1110 + -1'p1111 + -1'p1113 + p1117 + p1122 + p1123 + -1'p1129 + -1'p1130 + p1133 + p1134 + -1'p1137 + -1'p1138 + -1'p1140 + p1144 + p1149 + p1150 + -1'p1156 + -1'p1157 + -1'p1159 + p1163 = 0
invariant :p131 + p134 + p137 + p140 + p143 + p146 + p149 + p152 + p424 + p430 + -1'p434 + p438 + p442 + -1'p806 = 0
invariant :p129 + p131 + p133 + p134 + p136 + p137 + p139 + p140 + p142 + p143 + p145 + p146 + p148 + p149 + p151 + p152 + p154 + -1'p276 + -1'p279 + -1'p282 + -1'p285 + -1'p319 + -1'p322 + -1'p356 = 0
invariant :-1'p817 + p822 + p824 + p825 = 0
invariant :p927 + p1076 + p1087 + p1095 + p1103 + p1111 + p1119 + p1130 + p1138 + p1146 + p1157 + p1165 = 1
invariant :-1'p1105 + -1'p1106 + -1'p1107 + p1109 + p1110 + p1111 = 0
invariant :p1168 + p1169 + -1'p1176 + -1'p1177 + -1'p1178 = 0
invariant :p629 + p690 + p727 + p761 + p866 = 1
invariant :p550 + p608 = 1
invariant :p930 + p937 + -1'p1068 + p1075 + -1'p1079 + p1086 + -1'p1090 + p1094 + -1'p1098 + p1102 + -1'p1106 + p1110 + p1113 + p1115 + -1'p1117 + -1'p1119 + -1'p1122 + p1129 + -1'p1133 + p1137 + p1140 + p1142 + -1'p1144 + -1'p1146 + -1'p1149 + p1156 + p1159 + p1161 + -1'p1163 + -1'p1165 = 0
invariant :p1159 + p1160 + p1161 + -1'p1163 + -1'p1164 + -1'p1165 = 0
invariant :p990 + p992 + p993 + p995 + p996 + p998 + p999 + p1001 + p1002 + p1063 + p1067 + p1068 + p1069 + p1078 + p1079 + p1080 + p1089 + p1090 + p1091 + p1097 + p1098 + p1099 + p1105 + p1106 + p1107 + p1117 + p1118 + p1119 + p1121 + p1122 + p1123 + p1132 + p1133 + p1134 + p1144 + p1145 + p1146 + p1148 + p1149 + p1150 + p1163 + p1164 + p1165 + p1176 + p1177 + p1178 + p1184 + p1185 + p1186 + p1192 + p1193 + p1194 + p1222 + p1223 + p1224 + p1230 + p1231 + p1232 = 1
invariant :-1'p1097 + -1'p1098 + -1'p1099 + p1101 + p1102 + p1103 = 0
invariant :-1'p131 + -1'p134 + -1'p137 + -1'p140 + -1'p143 + -1'p146 + -1'p149 + -1'p152 + -1'p229 + p272 + p276 + p278 + p279 + p281 + p282 + p284 + p285 + p287 + p292 + -1'p293 + -1'p294 + -1'p295 + -1'p327 + -1'p361 + -1'p424 + -1'p430 + p434 + p440 + p806 = 0
invariant :p9 + p13 + p17 + p21 + p25 + p29 + p33 + p37 + p41 + p56 + p64 + p69 + p73 + p160 + p163 + p166 + p169 + p172 + p175 + p178 + p181 = 1
invariant :-1'p1089 + -1'p1090 + -1'p1091 + p1093 + p1094 + p1095 = 0
invariant :p491 + p495 + p499 + p503 + p507 + p511 + p515 + p519 + p875 + p878 + p881 + p884 + p887 + p890 + p893 + p896 + p899 + -1'p990 + -1'p993 + -1'p996 + -1'p999 + -1'p1178 + -1'p1186 + -1'p1194 + -1'p1224 + -1'p1232 = 0
invariant :p12 + p16 + p20 + p24 + p28 + p32 + p36 + p40 + -1'p160 + -1'p163 + -1'p166 + -1'p169 + -1'p172 + -1'p175 + -1'p178 + -1'p181 = 0
invariant :p50 + -1'p52 + -1'p56 + -1'p61 + -1'p68 + -1'p69 + -1'p71 + -1'p73 + -1'p430 + p434 + p440 + p806 = 1
invariant :p488 + p491 + p492 + p495 + p496 + p499 + p500 + p503 + p504 + p507 + p508 + p511 + p512 + p515 + p516 + p519 + p520 + -1'p615 + -1'p616 + -1'p627 + -1'p628 + -1'p632 + -1'p637 + -1'p641 + -1'p646 + -1'p688 + -1'p689 + -1'p725 + -1'p726 + -1'p759 + -1'p760 + -1'p790 + p866 = 1
invariant :p226 + p229 + p231 + -1'p232 + -1'p233 + -1'p237 + -1'p238 + -1'p242 + -1'p243 + -1'p246 + -1'p247 + -1'p251 + -1'p252 + p295 + p332 + p366 + p471 = 1
invariant :p93 + p97 + p101 + p105 + p109 + p113 + p117 + p121 + p125 + -1'p220 + -1'p221 + -1'p232 + -1'p233 + -1'p237 + -1'p242 + -1'p246 + -1'p251 + -1'p293 + -1'p294 + -1'p330 + -1'p331 + -1'p364 + -1'p365 + -1'p395 + p471 + p555 + p558 + p561 + p564 + p567 + p570 + p573 + p576 = 1
invariant :p8 + -1'p56 + -1'p64 + -1'p69 + -1'p73 = 0
invariant :-1'p1132 + -1'p1133 + -1'p1134 + p1136 + p1137 + p1138 = 0
invariant :-1'p1078 + -1'p1079 + -1'p1080 + p1085 + p1086 + p1087 = 0
invariant :p428 + p434 + p440 + p806 = 1
invariant :p973 + p1174 + p1182 + p1190 + p1228 = 1
invariant :-1'p131 + -1'p134 + -1'p137 + -1'p140 + -1'p143 + -1'p146 + -1'p149 + -1'p152 + p432 + p434 + p436 = 0
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 3 ordering constraints for composite.
built 603 ordering constraints for composite.
built 346 ordering constraints for composite.
built 140 ordering constraints for composite.
built 138 ordering constraints for composite.
built 336 ordering constraints for composite.
built 336 ordering constraints for composite.
built 391 ordering constraints for composite.
built 391 ordering constraints for composite.
built 293 ordering constraints for composite.
built 266 ordering constraints for composite.
built 264 ordering constraints for composite.
built 255 ordering constraints for composite.
built 111 ordering constraints for composite.
built 5 ordering constraints for composite.
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 14093 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 111 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
LTSmin run took 1304 ms.
FORMULA ASLink-PT-02b-ReachabilityDeadlock-0 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527762657542

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 10:28:35 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 10:28:35 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 10:28:35 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 442 ms
May 31, 2018 10:28:35 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1242 places.
May 31, 2018 10:28:36 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1621 transitions.
May 31, 2018 10:28:36 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 10:28:36 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 119 ms
May 31, 2018 10:28:37 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 798 ms
May 31, 2018 10:28:37 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 11 ms
May 31, 2018 10:28:37 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1621 transitions.
May 31, 2018 10:28:40 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 10:28:40 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 717 transitions.
May 31, 2018 10:28:40 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 405 ms
May 31, 2018 10:28:41 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 388 ms
May 31, 2018 10:28:41 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 10:28:41 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 262 ms
May 31, 2018 10:28:41 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 10:28:41 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 73 place invariants in 192 ms
May 31, 2018 10:28:43 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 990 redundant transitions.
May 31, 2018 10:28:43 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 35 ms
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 424 variables to be positive in 2558 ms
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 717 transitions.
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/717 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 97 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 717 transitions.
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 51 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 717 transitions.
May 31, 2018 10:28:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/717) took 3219 ms. Total solver calls (SAT/UNSAT): 1118(1055/63)
May 31, 2018 10:28:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/717) took 6387 ms. Total solver calls (SAT/UNSAT): 3173(3110/63)
May 31, 2018 10:28:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/717) took 9478 ms. Total solver calls (SAT/UNSAT): 5230(5167/63)
May 31, 2018 10:28:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/717) took 12520 ms. Total solver calls (SAT/UNSAT): 7280(7217/63)
May 31, 2018 10:29:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/717) took 15690 ms. Total solver calls (SAT/UNSAT): 8437(7872/565)
May 31, 2018 10:29:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(91/717) took 18693 ms. Total solver calls (SAT/UNSAT): 10978(8013/2965)
May 31, 2018 10:29:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(122/717) took 21741 ms. Total solver calls (SAT/UNSAT): 13923(8120/5803)
May 31, 2018 10:29:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(142/717) took 24958 ms. Total solver calls (SAT/UNSAT): 15733(9182/6551)
May 31, 2018 10:29:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(158/717) took 28066 ms. Total solver calls (SAT/UNSAT): 17195(10454/6741)
May 31, 2018 10:29:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(172/717) took 31282 ms. Total solver calls (SAT/UNSAT): 19288(12547/6741)
May 31, 2018 10:29:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(187/717) took 34462 ms. Total solver calls (SAT/UNSAT): 21313(14572/6741)
May 31, 2018 10:29:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(204/717) took 37629 ms. Total solver calls (SAT/UNSAT): 23336(16595/6741)
May 31, 2018 10:29:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(230/717) took 40662 ms. Total solver calls (SAT/UNSAT): 25629(18608/7021)
May 31, 2018 10:29:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(265/717) took 43719 ms. Total solver calls (SAT/UNSAT): 27385(19735/7650)
May 31, 2018 10:29:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(288/717) took 47200 ms. Total solver calls (SAT/UNSAT): 28725(20461/8264)
May 31, 2018 10:29:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(295/717) took 50485 ms. Total solver calls (SAT/UNSAT): 29337(20557/8780)
May 31, 2018 10:29:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(300/717) took 55862 ms. Total solver calls (SAT/UNSAT): 29731(20655/9076)
May 31, 2018 10:29:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(302/717) took 59617 ms. Total solver calls (SAT/UNSAT): 29916(20729/9187)
May 31, 2018 10:29:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(304/717) took 64184 ms. Total solver calls (SAT/UNSAT): 30097(20803/9294)
May 31, 2018 10:29:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(315/717) took 67195 ms. Total solver calls (SAT/UNSAT): 30698(21142/9556)
May 31, 2018 10:29:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(322/717) took 70918 ms. Total solver calls (SAT/UNSAT): 31122(21365/9757)
May 31, 2018 10:29:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(328/717) took 74154 ms. Total solver calls (SAT/UNSAT): 31647(21714/9933)
May 31, 2018 10:30:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(382/717) took 77196 ms. Total solver calls (SAT/UNSAT): 34106(21924/12182)
May 31, 2018 10:30:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(418/717) took 80244 ms. Total solver calls (SAT/UNSAT): 35529(23126/12403)
May 31, 2018 10:30:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(467/717) took 83331 ms. Total solver calls (SAT/UNSAT): 36895(24492/12403)
May 31, 2018 10:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(492/717) took 86374 ms. Total solver calls (SAT/UNSAT): 38467(26000/12467)
May 31, 2018 10:30:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(536/717) took 89437 ms. Total solver calls (SAT/UNSAT): 39871(27404/12467)
May 31, 2018 10:30:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(544/717) took 92454 ms. Total solver calls (SAT/UNSAT): 40382(27672/12710)
May 31, 2018 10:30:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(569/717) took 95517 ms. Total solver calls (SAT/UNSAT): 41561(28638/12923)
May 31, 2018 10:30:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(634/717) took 98520 ms. Total solver calls (SAT/UNSAT): 42283(29057/13226)
May 31, 2018 10:30:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(676/717) took 101538 ms. Total solver calls (SAT/UNSAT): 43248(29317/13931)
May 31, 2018 10:30:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 104445 ms. Total solver calls (SAT/UNSAT): 43686(29549/14137)
May 31, 2018 10:30:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 717 transitions.
May 31, 2018 10:30:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 11776 ms. Total solver calls (SAT/UNSAT): 4834(0/4834)
May 31, 2018 10:30:40 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 120308ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-02b"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-02b.tgz
mv ASLink-PT-02b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-02b, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149400035"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;