fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r272-smll-152749149200420
Last Updated
June 26, 2018

About the Execution of ITS-Tools for DLCflexbar-PT-5a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15739.290 1697822.00 3413007.00 5242.50 FFFFFFFFFFFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 2.9M
-rw-r--r-- 1 mcc users 2.9K May 29 20:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 15K May 29 20:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 28 16:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 16:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:34 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.3K May 28 09:34 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.2K May 28 07:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.1K May 27 07:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 27 07:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 107 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 345 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 26 09:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 26 09:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 3 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 2.8M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DLCflexbar-PT-5a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749149200420

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-5a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527968865439

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Checking formula 0 : !(("((u9.p63>=1)&&(u459.p894>=1))"))
Formula 0 simplified : !"((u9.p63>=1)&&(u459.p894>=1))"
built 1821 ordering constraints for composite.
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
14158 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,143.449,824480,1,0,253834,3981,41006,247988,410,3422,1282437
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((F((("((u369.p804>=1)&&(u65.p461>=1))")U("((u599.p1034>=1)&&(u67.p481>=1))"))U(G(G("((u41.p284>=1)&&(u646.p1081>=1))"))))))
Formula 1 simplified : !F(("((u369.p804>=1)&&(u65.p461>=1))" U "((u599.p1034>=1)&&(u67.p481>=1))") U G"((u41.p284>=1)&&(u646.p1081>=1))")
Compilation finished in 169623 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 131 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((((LTLAP1==true))U((LTLAP2==true)))U([]([]((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((((LTLAP1==true))U((LTLAP2==true)))U([]([]((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X(X((LTLAP4==true))))U(<>((LTLAP5==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 746 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 885 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((X((LTLAP7==true)))U((LTLAP8==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 730 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 733 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]([]([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]([]([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X(X((LTLAP13==true)))))U(([]((LTLAP14==true)))U((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 655 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP16==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 871 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
98419 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1127.64,5085380,1,0,1.25006e+07,3981,22095,2.08661e+07,244,3758,7674534
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((F((X(X("((u69.p503>=1)&&(u926.p1361>=1))")))U(F("((u69.p502>=1)&&(u927.p1362>=1))")))))
Formula 2 simplified : !F(XX"((u69.p503>=1)&&(u926.p1361>=1))" U F"((u69.p502>=1)&&(u927.p1362>=1))")
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
2895 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1156.59,5085380,1,0,1.25006e+07,3981,29644,2.08661e+07,357,4343,7944158
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !((X(F(X("(u36.p247>=1)")))))
Formula 3 simplified : !XFX"(u36.p247>=1)"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
2402 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1180.61,5085380,1,0,1.25006e+07,3981,31058,2.08661e+07,358,4512,8259217
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 4 : !((F(X((X("((u69.p503>=1)&&(u844.p1279>=1))"))U("((u69.p495>=1)&&(u861.p1296>=1))")))))
Formula 4 simplified : !FX(X"((u69.p503>=1)&&(u844.p1279>=1))" U "((u69.p495>=1)&&(u861.p1296>=1))")
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
228 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1182.89,5085380,1,0,1.25006e+07,3981,31379,2.08661e+07,358,5041,8276999
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 5 : !((X(F("((u69.p503>=1)&&(u918.p1353>=1))"))))
Formula 5 simplified : !XF"((u69.p503>=1)&&(u918.p1353>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
130 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1184.19,5085380,1,0,1.25006e+07,3981,31548,2.08661e+07,358,5043,8286729
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 6 : !(("((u785.p1220>=1)&&(u68.p491>=1))"))
Formula 6 simplified : !"((u785.p1220>=1)&&(u68.p491>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
166 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1185.85,5085380,1,0,1.25006e+07,3981,31746,2.08661e+07,358,5043,8292455
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 7 : !((G(G(G(G("((u61.p427>=1)&&(u190.p625>=1))"))))))
Formula 7 simplified : !G"((u61.p427>=1)&&(u190.p625>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
12 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1185.97,5085380,1,0,1.25006e+07,3981,31766,2.08661e+07,358,5043,8293579
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 8 : !((F("((u23.p158>=1)&&(u238.p673>=1))")))
Formula 8 simplified : !F"((u23.p158>=1)&&(u238.p673>=1))"
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
1394 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1199.91,5085380,1,0,1.25006e+07,3981,33408,2.08661e+07,358,5070,8467010
an accepting run exists (use option '-e' to print it)
Formula 8 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 9 : !(((X(X(X("((u66.p474>=1)&&(u483.p918>=1))"))))U((G("((u495.p930>=1)&&(u66.p471>=1))"))U("(u60.p420>=1)"))))
Formula 9 simplified : !(XXX"((u66.p474>=1)&&(u483.p918>=1))" U (G"((u495.p930>=1)&&(u66.p471>=1))" U "(u60.p420>=1)"))
7 unique states visited
6 strongly connected components in search stack
7 transitions explored
6 items max in DFS search stack
239 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1202.3,5086884,1,0,1.25006e+07,3981,33443,2.08661e+07,359,5305,8882323
an accepting run exists (use option '-e' to print it)
Formula 9 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 10 : !((X(G("((u68.p488>=1)&&(u971.p1406>=1))"))))
Formula 10 simplified : !XG"((u68.p488>=1)&&(u971.p1406>=1))"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
14 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1202.45,5086884,1,0,1.25006e+07,3981,33463,2.08661e+07,359,5305,8883848
an accepting run exists (use option '-e' to print it)
Formula 10 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 11 : !(("((u67.p482>=1)&&(u673.p1108>=1))"))
Formula 11 simplified : !"((u67.p482>=1)&&(u673.p1108>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1202.45,5086884,1,0,1.25006e+07,3981,33468,2.08661e+07,359,5305,8884152
an accepting run exists (use option '-e' to print it)
Formula 11 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 12 : !((X(X(F("((u46.p322>=1)&&(u285.p720>=1))")))))
Formula 12 simplified : !XXF"((u46.p322>=1)&&(u285.p720>=1))"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1530 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1217.75,5086884,1,0,1.25006e+07,3981,34992,2.08661e+07,359,5355,9140453
an accepting run exists (use option '-e' to print it)
Formula 12 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 13 : !((F(X(F(F(G("((u68.p492>=1)&&(u737.p1172>=1))")))))))
Formula 13 simplified : !FXFG"((u68.p492>=1)&&(u737.p1172>=1))"
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>(<>([]((LTLAP19==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 604 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP20==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP20==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []((X(<>((LTLAP21==true))))U([](X((LTLAP22==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 621 ms.
FORMULA DLCflexbar-PT-5a-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP20==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
37732 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1595.06,6163184,1,0,1.64808e+07,3981,21180,2.37913e+07,244,5620,13152107
an accepting run exists (use option '-e' to print it)
Formula 13 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 14 : !((G(G("((u67.p478>=1)&&(u669.p1104>=1))"))))
Formula 14 simplified : !G"((u67.p478>=1)&&(u669.p1104>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
2091 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1615.98,6163184,1,0,1.64808e+07,3981,29346,2.37913e+07,357,5620,13325833
an accepting run exists (use option '-e' to print it)
Formula 14 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 15 : !((G((X(F("((u68.p489>=1)&&(u715.p1150>=1))")))U(G(X("((u32.p221>=1)&&(u504.p939>=1))"))))))
Formula 15 simplified : !G(XF"((u68.p489>=1)&&(u715.p1150>=1))" U GX"((u32.p221>=1)&&(u504.p939>=1))")
5 unique states visited
5 strongly connected components in search stack
6 transitions explored
5 items max in DFS search stack
1641 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1632.39,6163184,1,0,1.64808e+07,3981,31849,2.37913e+07,357,5620,13541507
an accepting run exists (use option '-e' to print it)
Formula 15 is FALSE accepting run found.
FORMULA DLCflexbar-PT-5a-LTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527970563261

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 7:47:47 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 7:47:47 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 7:47:48 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 582 ms
Jun 02, 2018 7:47:48 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1415 places.
Jun 02, 2018 7:47:48 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 10593 transitions.
Jun 02, 2018 7:47:48 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 02, 2018 7:47:49 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 7:47:49 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 7:47:51 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1713 ms
Jun 02, 2018 7:47:51 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 7:47:53 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 17954 redundant transitions.
Jun 02, 2018 7:47:53 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 117 ms
Jun 02, 2018 7:47:53 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Jun 02, 2018 7:47:54 PM fr.lip6.move.gal.semantics.CompositeNextBuilder getNextForLabel
INFO: Semantic construction discarded 1179 identical transitions.
Jun 02, 2018 7:47:54 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 9414 transitions.
Jun 02, 2018 7:47:54 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (9414) to apply POR reductions. Disabling POR matrices.
Jun 02, 2018 7:47:55 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1419ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DLCflexbar-PT-5a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749149200420"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;