Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......................
/home/mcc/execution
total 248K
-rw-r--r-- 1 mcc users 3.5K May 29 16:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 29 16:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 28 11:17 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 28 11:17 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 28 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.2K May 28 07:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.2K May 27 05:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 27 05:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 114 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 352 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 26 06:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 26 06:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 3 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 85K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BusinessProcesses-PT-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749148900222
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-00
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-01
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-02
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-03
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-04
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-05
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-06
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-07
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-08
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-09
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-10
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-11
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-12
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-13
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-14
FORMULA_NAME BusinessProcesses-PT-05-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527882916490

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G("(((u71.p224>=1)&&(u29.p95>=1))&&(u80.p343>=1))")))
Formula 0 simplified : !G"(((u71.p224>=1)&&(u29.p95>=1))&&(u80.p343>=1))"
built 84 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 319 rows 368 cols
invariant :u67:p201 + u67:p202 + u67:p203 + u67:p204 + u67:p205 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u30:p97 + u30:p98 + u30:p99 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p347 + u80:p348 + u109:p0 = 1
invariant :u30:p100 + u30:p101 + u30:p102 + -1'u80:p347 + -1'u80:p348 = 0
invariant :u21:p33 + u21:p34 + u21:p37 + u21:p38 + -1'u80:p288 + -1'u80:p289 + -1'u80:p292 + -1'u80:p293 + -1'u80:p294 = 0
invariant :u62:p176 + u62:p177 + u62:p178 + u62:p179 + u62:p180 + u101:p152 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u27:p76 + u27:p77 + u27:p78 + u27:p79 + u27:p80 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p331 + u80:p332 + u109:p0 = 1
invariant :u78:p256 + u78:p257 + u78:p258 + u78:p259 + u78:p260 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u75:p241 + u75:p242 + u75:p243 + u75:p244 + u75:p245 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u61:p171 + u61:p172 + u61:p173 + u61:p174 + u61:p175 + u99:p153 + u101:p152 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u65:p191 + u65:p192 + u65:p193 + u65:p194 + u65:p195 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u32:p112 + u32:p113 + u32:p114 + -1'u80:p355 + -1'u80:p356 = 0
invariant :u58:p156 + u58:p157 + u58:p158 + u58:p159 + u58:p160 + u103:p155 + u105:p154 + u99:p153 + u101:p152 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u68:p206 + u68:p207 + u68:p208 + u68:p209 + u68:p210 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u28:p88 + u28:p89 + -1'u80:p337 + -1'u80:p338 = 0
invariant :u33:p115 + u33:p116 + u33:p117 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p359 + u80:p360 + u109:p0 = 1
invariant :u63:p181 + u63:p182 + u63:p183 + u63:p184 + u63:p185 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u64:p186 + u64:p187 + u64:p188 + u64:p189 + u64:p190 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u66:p196 + u66:p197 + u66:p198 + u66:p199 + u66:p200 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u28:p83 + u28:p84 + u28:p85 + u28:p86 + u28:p87 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p337 + u80:p338 + u109:p0 = 1
invariant :u34:p121 + u34:p122 + u34:p123 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p363 + u80:p364 + u109:p0 = 1
invariant :u19:p19 + u19:p20 + u19:p21 + u113:p18 + u108:p17 + u110:p16 + u106:p15 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p280 + u80:p281 + u109:p0 = 1
invariant :u21:p32 + u21:p35 + u21:p36 + u108:p17 + u110:p16 + u106:p15 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p288 + u80:p289 + u80:p292 + u80:p293 + u80:p294 + u109:p0 = 1
invariant :u29:p90 + u29:p91 + u29:p92 + u29:p93 + u29:p94 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p343 + u80:p344 + u109:p0 = 1
invariant :u25:p60 + u25:p61 + u25:p62 + u25:p63 + u25:p64 + u25:p65 + u25:p68 + u25:p69 + u80:p266 + u80:p267 + u80:p268 + u80:p269 + u80:p270 + u80:p271 + u80:p272 + u80:p273 + u80:p274 + u80:p275 + u80:p276 + u80:p277 + u80:p278 + u80:p279 + u80:p280 + u80:p281 + u80:p282 + u80:p283 + u80:p284 + u80:p285 + u80:p286 + u80:p287 + u80:p288 + u80:p289 + u80:p290 + u80:p291 + u80:p292 + u80:p293 + u80:p294 + u80:p295 + u80:p296 + u80:p297 + u80:p298 + u80:p299 + u80:p300 + u80:p301 + u80:p302 + u80:p303 + u80:p304 + u80:p305 + u80:p306 + u80:p307 + u80:p308 + u80:p309 + u80:p310 + u80:p311 + u80:p318 + u80:p319 + u80:p323 + u80:p324 + u80:p325 + u80:p326 + u80:p327 + u80:p328 + u80:p329 + u80:p330 + u80:p331 + u80:p332 + u80:p333 + u80:p334 + u80:p335 + u80:p336 + u80:p337 + u80:p338 + u80:p339 + u80:p340 + u80:p341 + u80:p342 + u80:p343 + u80:p344 + u80:p345 + u80:p346 + u80:p347 + u80:p348 + u80:p349 + u80:p350 + u80:p351 + u80:p352 + u80:p353 + u80:p354 + u80:p355 + u80:p356 + u80:p357 + u80:p358 + u80:p359 + u80:p360 + u80:p361 + u80:p362 + u80:p363 + u80:p364 + u80:p365 + u80:p366 + u80:p367 + u109:p0 = 1
invariant :u22:p39 + u22:p40 + u22:p41 + u22:p42 + u22:p43 + u110:p16 + u106:p15 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p299 + u80:p300 + u109:p0 = 1
invariant :u25:p59 + u25:p66 + u25:p67 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + -1'u80:p266 + -1'u80:p267 + -1'u80:p268 + -1'u80:p269 + -1'u80:p270 + -1'u80:p271 + -1'u80:p272 + -1'u80:p273 + -1'u80:p274 + -1'u80:p275 + -1'u80:p276 + -1'u80:p277 + -1'u80:p278 + -1'u80:p279 + -1'u80:p280 + -1'u80:p281 + -1'u80:p282 + -1'u80:p283 + -1'u80:p284 + -1'u80:p285 + -1'u80:p286 + -1'u80:p287 + -1'u80:p288 + -1'u80:p289 + -1'u80:p290 + -1'u80:p291 + -1'u80:p292 + -1'u80:p293 + -1'u80:p294 + -1'u80:p295 + -1'u80:p296 + -1'u80:p297 + -1'u80:p298 + -1'u80:p299 + -1'u80:p300 + -1'u80:p301 + -1'u80:p302 + -1'u80:p303 + -1'u80:p304 + -1'u80:p305 + -1'u80:p306 + -1'u80:p307 + -1'u80:p308 + -1'u80:p309 + -1'u80:p310 + -1'u80:p311 + -1'u80:p318 + -1'u80:p319 + -1'u80:p323 + -1'u80:p324 + -1'u80:p325 + -1'u80:p326 + -1'u80:p327 + -1'u80:p328 + -1'u80:p329 + -1'u80:p330 + -1'u80:p331 + -1'u80:p332 + -1'u80:p333 + -1'u80:p334 + -1'u80:p335 + -1'u80:p336 + -1'u80:p337 + -1'u80:p338 + -1'u80:p339 + -1'u80:p340 + -1'u80:p341 + -1'u80:p342 + -1'u80:p343 + -1'u80:p344 + -1'u80:p345 + -1'u80:p346 + -1'u80:p347 + -1'u80:p348 + -1'u80:p349 + -1'u80:p350 + -1'u80:p351 + -1'u80:p352 + -1'u80:p353 + -1'u80:p354 + -1'u80:p355 + -1'u80:p356 + -1'u80:p357 + -1'u80:p358 + -1'u80:p359 + -1'u80:p360 + -1'u80:p361 + -1'u80:p362 + -1'u80:p363 + -1'u80:p364 + -1'u80:p365 + -1'u80:p366 + -1'u80:p367 = 0
invariant :u24:p53 + u24:p54 + u24:p55 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p310 + u80:p311 + u109:p0 = 1
invariant :u79:p261 + u79:p262 + u79:p263 + u79:p264 + u79:p265 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u31:p106 + u31:p107 + u31:p108 + -1'u80:p351 + -1'u80:p352 = 0
invariant :u24:p56 + u24:p57 + u24:p58 + -1'u80:p310 + -1'u80:p311 = 0
invariant :u34:p124 + u34:p125 + u34:p126 + -1'u80:p363 + -1'u80:p364 = 0
invariant :u80:p266 + u80:p267 + u80:p268 + u80:p269 + u80:p270 + u80:p271 + u80:p272 + u80:p273 + u80:p274 + u80:p275 + u80:p276 + u80:p277 + u80:p278 + u80:p279 + u80:p280 + u80:p281 + u80:p282 + u80:p283 + u80:p284 + u80:p285 + u80:p286 + u80:p287 + u80:p288 + u80:p289 + u80:p290 + u80:p291 + u80:p292 + u80:p293 + u80:p294 + u80:p295 + u80:p296 + u80:p297 + u80:p298 + u80:p299 + u80:p300 + u80:p301 + u80:p302 + u80:p303 + u80:p304 + u80:p305 + u80:p306 + u80:p307 + u80:p308 + u80:p309 + u80:p310 + u80:p311 + u80:p312 + u80:p313 + u80:p314 + u80:p315 + u80:p316 + u80:p317 + u80:p318 + u80:p319 + u80:p320 + u80:p321 + u80:p322 + u80:p323 + u80:p324 + u80:p325 + u80:p326 + u80:p327 + u80:p328 + u80:p329 + u80:p330 + u80:p331 + u80:p332 + u80:p333 + u80:p334 + u80:p335 + u80:p336 + u80:p337 + u80:p338 + u80:p339 + u80:p340 + u80:p341 + u80:p342 + u80:p343 + u80:p344 + u80:p345 + u80:p346 + u80:p347 + u80:p348 + u80:p349 + u80:p350 + u80:p351 + u80:p352 + u80:p353 + u80:p354 + u80:p355 + u80:p356 + u80:p357 + u80:p358 + u80:p359 + u80:p360 + u80:p361 + u80:p362 + u80:p363 + u80:p364 + u80:p365 + u80:p366 + u80:p367 + u109:p0 = 1
invariant :u32:p109 + u32:p110 + u32:p111 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p355 + u80:p356 + u109:p0 = 1
invariant :u71:p221 + u71:p222 + u71:p223 + u71:p224 + u71:p225 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u23:p47 + u23:p48 + u23:p51 + u23:p52 + -1'u80:p301 + -1'u80:p302 + -1'u80:p305 + -1'u80:p306 + -1'u80:p307 = 0
invariant :u36:p131 + u36:p132 + u36:p133 + u36:p134 + u112:p2 + u111:p1 + u109:p0 = 1
invariant :u29:p95 + u29:p96 + -1'u80:p343 + -1'u80:p344 = 0
invariant :u20:p25 + u20:p26 + u20:p27 + u20:p28 + u20:p29 + u113:p18 + u108:p17 + u110:p16 + u106:p15 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p286 + u80:p287 + u109:p0 = 1
invariant :u33:p118 + u33:p119 + u33:p120 + -1'u80:p359 + -1'u80:p360 = 0
invariant :u35:p127 + u35:p128 + u35:p129 + u35:p130 + u114:p3 + u112:p2 + u111:p1 + u109:p0 = 1
invariant :u76:p246 + u76:p247 + u76:p248 + u76:p249 + u76:p250 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u20:p30 + u20:p31 + -1'u80:p286 + -1'u80:p287 = 0
invariant :u19:p22 + u19:p23 + u19:p24 + -1'u80:p280 + -1'u80:p281 = 0
invariant :u72:p226 + u72:p227 + u72:p228 + u72:p229 + u72:p230 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u27:p81 + u27:p82 + -1'u80:p331 + -1'u80:p332 = 0
invariant :u60:p166 + u60:p167 + u60:p168 + u60:p169 + u60:p170 + u105:p154 + u99:p153 + u101:p152 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u74:p236 + u74:p237 + u74:p238 + u74:p239 + u74:p240 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u26:p70 + u26:p71 + u26:p72 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p325 + u80:p326 + u109:p0 = 1
invariant :u70:p216 + u70:p217 + u70:p218 + u70:p219 + u70:p220 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u26:p73 + u26:p74 + u26:p75 + -1'u80:p325 + -1'u80:p326 = 0
invariant :u59:p161 + u59:p162 + u59:p163 + u59:p164 + u59:p165 + u103:p155 + u105:p154 + u99:p153 + u101:p152 + u96:p151 + u97:p150 + u94:p149 + u95:p148 + u93:p147 + u91:p146 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u22:p44 + u22:p45 + -1'u80:p299 + -1'u80:p300 = 0
invariant :u23:p46 + u23:p49 + u23:p50 + u106:p15 + u107:p14 + u102:p13 + u104:p12 + u98:p11 + u100:p10 + u120:p9 + u119:p8 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p301 + u80:p302 + u80:p305 + u80:p306 + u80:p307 + u109:p0 = 1
invariant :u31:p103 + u31:p104 + u31:p105 + u118:p7 + u117:p6 + u116:p5 + u115:p4 + u114:p3 + u112:p2 + u111:p1 + u80:p351 + u80:p352 + u109:p0 = 1
invariant :u69:p211 + u69:p212 + u69:p213 + u69:p214 + u69:p215 + u92:p145 + u89:p144 + u90:p143 + u87:p142 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u73:p231 + u73:p232 + u73:p233 + u73:p234 + u73:p235 + u88:p141 + u85:p140 + u86:p139 + u84:p138 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
invariant :u77:p251 + u77:p252 + u77:p253 + u77:p254 + u77:p255 + u82:p137 + u83:p136 + u81:p135 + u111:p1 + u109:p0 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6015 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions t182, t244, t250, t256, u19.t264, u20.t259, u20.t261, u21.t251, u21.t253, u21.t255, u22.t247, u22.t249, u23.t239, u23.t241, u23.t243, u24.t237, u25.t225, u25.t227, u25.t229, u25.t231, u25.t233, u26.t223, u27.t217, u27.t219, u28.t211, u28.t213, u29.t205, u29.t207, u30.t201, u31.t197, u32.t193, u33.t189, u34.t185, u35.t181, u58.t175, u58.t176, u59.t172, u59.t173, u60.t168, u60.t169, u61.t164, u61.t165, u62.t160, u62.t161, u63.t156, u63.t157, u64.t152, u64.t153, u65.t148, u65.t149, u66.t144, u66.t145, u67.t140, u67.t141, u68.t136, u68.t137, u69.t132, u69.t133, u70.t128, u70.t129, u71.t124, u71.t125, u72.t120, u72.t121, u73.t116, u73.t117, u74.t112, u74.t113, u75.t108, u75.t109, u76.t104, u76.t105, u77.t100, u77.t101, u78.t96, u78.t97, u79.t92, u79.t93, u80.t1, u80.t3, u80.t6, u80.t9, u80.t12, u80.t15, u80.t18, u80.t21, u80.t23, u80.t26, u80.t28, u80.t31, u80.t33, u80.t36, u80.t38, u80.t40, u80.t42, u80.t44, u80.t46, u80.t49, u80.t51, u80.t53, u80.t55, u80.t58, u80.t60, u80.t62, u80.t64, u80.t66, u80.t69, u80.t71, u80.t74, u80.t76, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :1/208/110/319
Link finished in 43 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 256 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(<>(X(((LTLAP1==true))U((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 31 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>(((LTLAP3==true))U((LTLAP4==true))))U((LTLAP5==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 239 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((X(<>((LTLAP6==true))))U(((LTLAP7==true))U((LTLAP8==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 22 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP9==true))U(<>((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 264 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X(<>([]((LTLAP11==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 22 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]([](<>(<>((LTLAP12==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 238 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP13==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 31 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP14==true))U(<>([]([]((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Computing Next relation with stutter on 24 deadlock states
LTSmin run took 253 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 240 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(<>((LTLAP17==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 240 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP18==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 290 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(<>(X([](X((LTLAP19==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 31 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 239 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP21==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 239 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(<>((LTLAP22==true))))U(X((LTLAP23==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 38 ms.
FORMULA BusinessProcesses-PT-05-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527882947278

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 7:55:19 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 01, 2018 7:55:19 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 7:55:19 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 100 ms
Jun 01, 2018 7:55:19 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 368 places.
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 319 transitions.
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 7:55:20 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 25 ms
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 105 ms
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 7:55:20 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 17 ms
Jun 01, 2018 7:55:20 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Jun 01, 2018 7:55:20 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 319 transitions.
Jun 01, 2018 7:55:21 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 57 place invariants in 185 ms
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 368 variables to be positive in 1024 ms
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 319 transitions.
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/319 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 56 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 319 transitions.
Jun 01, 2018 7:55:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 37 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 7:55:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 319 transitions.
Jun 01, 2018 7:55:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/319) took 2173 ms. Total solver calls (SAT/UNSAT): 694(61/633)
Jun 01, 2018 7:55:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/319) took 5357 ms. Total solver calls (SAT/UNSAT): 2582(259/2323)
Jun 01, 2018 7:55:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/319) took 8946 ms. Total solver calls (SAT/UNSAT): 3432(639/2793)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Jun 01, 2018 7:55:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 11913 ms. Total solver calls (SAT/UNSAT): 4201(1007/3194)
Jun 01, 2018 7:55:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 319 transitions.
Jun 01, 2018 7:55:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 2153 ms. Total solver calls (SAT/UNSAT): 1479(0/1479)
Jun 01, 2018 7:55:37 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 16738ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BusinessProcesses-PT-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BusinessProcesses-PT-05.tgz
mv BusinessProcesses-PT-05 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BusinessProcesses-PT-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749148900222"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;