fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r272-smll-152749148800098
Last Updated
June 26, 2018

About the Execution of ITS-Tools for ASLink-PT-06a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15753.080 3600000.00 4380837.00 8684.10 [undef] Time out reached

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 764K
-rw-r--r-- 1 mcc users 3.5K May 29 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 29 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 28 11:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 11:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 28 09:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.3K May 28 07:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.7K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.2K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 597K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ASLink-PT-06a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749148800098

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-06a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527807593375

Flatten gal took : 678 ms
Constant places removed 25 places and 1 transitions.
Reduce isomorphic transitions removed 22 transitions.
Implicit places reduction removed 12 places :[p1263, p1196, p1001, p989, p806, p794, p611, p599, p416, p404, p221, p209]
Performed 261 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 320 rules applied. Total rules applied 320 place count 1369 transition count 1816
Constant places removed 324 places and 0 transitions.
Performed 20 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 344 rules applied. Total rules applied 664 place count 1045 transition count 1796
Constant places removed 21 places and 0 transitions.
Implicit places reduction removed 7 places :[p1173, p978, p783, p588, p393, p206, p199]
Performed 7 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 35 rules applied. Total rules applied 699 place count 1017 transition count 1789
Constant places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 706 place count 1010 transition count 1789
Performed 24 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 24 Pre rules applied. Total rules applied 706 place count 1010 transition count 1765
Constant places removed 24 places and 0 transitions.
Iterating post reduction 4 with 24 rules applied. Total rules applied 730 place count 986 transition count 1765
Symmetric choice reduction at 5 with 15 rule applications. Total rules 745 place count 986 transition count 1765
Constant places removed 15 places and 53 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 9 places :[p1405, p1266, p1164, p969, p774, p579, p384, p190, p23]
Performed 10 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 36 rules applied. Total rules applied 781 place count 962 transition count 1700
Constant places removed 10 places and 0 transitions.
Iterating post reduction 6 with 10 rules applied. Total rules applied 791 place count 952 transition count 1700
Symmetric choice reduction at 7 with 7 rule applications. Total rules 798 place count 952 transition count 1700
Constant places removed 7 places and 14 transitions.
Iterating post reduction 7 with 7 rules applied. Total rules applied 805 place count 945 transition count 1686
Symmetric choice reduction at 8 with 1 rule applications. Total rules 806 place count 945 transition count 1686
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 807 place count 944 transition count 1678
Symmetric choice reduction at 9 with 1 rule applications. Total rules 808 place count 944 transition count 1678
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 809 place count 943 transition count 1670
Symmetric choice reduction at 10 with 1 rule applications. Total rules 810 place count 943 transition count 1670
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 811 place count 942 transition count 1662
Symmetric choice reduction at 11 with 1 rule applications. Total rules 812 place count 942 transition count 1662
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 813 place count 941 transition count 1654
Symmetric choice reduction at 12 with 1 rule applications. Total rules 814 place count 941 transition count 1654
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 815 place count 940 transition count 1646
Symmetric choice reduction at 13 with 1 rule applications. Total rules 816 place count 940 transition count 1646
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 817 place count 939 transition count 1638
Symmetric choice reduction at 14 with 1 rule applications. Total rules 818 place count 939 transition count 1638
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 819 place count 938 transition count 1630
Symmetric choice reduction at 15 with 1 rule applications. Total rules 820 place count 938 transition count 1630
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 821 place count 937 transition count 1622
Symmetric choice reduction at 16 with 1 rule applications. Total rules 822 place count 937 transition count 1622
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 823 place count 936 transition count 1614
Symmetric choice reduction at 17 with 1 rule applications. Total rules 824 place count 936 transition count 1614
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 825 place count 935 transition count 1606
Symmetric choice reduction at 18 with 1 rule applications. Total rules 826 place count 935 transition count 1606
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 827 place count 934 transition count 1598
Symmetric choice reduction at 19 with 1 rule applications. Total rules 828 place count 934 transition count 1598
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 829 place count 933 transition count 1590
Symmetric choice reduction at 20 with 1 rule applications. Total rules 830 place count 933 transition count 1590
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 831 place count 932 transition count 1582
Symmetric choice reduction at 21 with 1 rule applications. Total rules 832 place count 932 transition count 1582
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 833 place count 931 transition count 1574
Symmetric choice reduction at 22 with 1 rule applications. Total rules 834 place count 931 transition count 1574
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 835 place count 930 transition count 1566
Performed 19 Post agglomeration using F-continuation condition.
Constant places removed 19 places and 0 transitions.
Iterating post reduction 23 with 19 rules applied. Total rules applied 854 place count 911 transition count 1547
Applied a total of 854 rules in 1678 ms. Remains 911 /1406 variables (removed 495) and now considering 1547/2100 (removed 553) transitions.
// Phase 1: matrix 1547 rows 911 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 21741 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 60 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
sparsehash FATAL ERROR: failed to allocate 44 groups

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 10:59:55 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 31, 2018 10:59:55 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 10:59:55 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 294 ms
May 31, 2018 10:59:55 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1406 places.
May 31, 2018 10:59:56 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2100 transitions.
May 31, 2018 10:59:56 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 10:59:56 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 92 ms
May 31, 2018 10:59:57 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 670 ms
May 31, 2018 10:59:57 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 27 ms
May 31, 2018 10:59:57 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2100 transitions.
May 31, 2018 11:00:00 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 10 ms
May 31, 2018 11:00:00 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1547 transitions.
May 31, 2018 11:00:00 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1547) to apply POR reductions. Disabling POR matrices.
May 31, 2018 11:00:00 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 293ms conformant to PINS in folder :/home/mcc/execution
ITS-tools command line returned an error code 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-06a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-06a.tgz
mv ASLink-PT-06a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ASLink-PT-06a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749148800098"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;