fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r272-smll-152749148700026
Last Updated
June 26, 2018

About the Execution of ITS-Tools for ASLink-PT-02a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15754.200 100779.00 216396.00 615.70 T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......................
/home/mcc/execution
total 452K
-rw-r--r-- 1 mcc users 3.2K May 29 16:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 29 16:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 28 11:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 11:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.6K May 28 09:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 28 07:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.9K May 27 05:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 27 05:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 279K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ASLink-PT-02a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749148700026

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-02a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527760784611

Flatten gal took : 354 ms
Constant places removed 9 places and 1 transitions.
Reduce isomorphic transitions removed 10 transitions.
Implicit places reduction removed 4 places :[p483, p416, p221, p209]
Performed 101 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 124 rules applied. Total rules applied 124 place count 613 transition count 896
Constant places removed 124 places and 0 transitions.
Performed 8 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 132 rules applied. Total rules applied 256 place count 489 transition count 888
Constant places removed 9 places and 0 transitions.
Implicit places reduction removed 3 places :[p393, p206, p199]
Performed 3 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 15 rules applied. Total rules applied 271 place count 477 transition count 885
Constant places removed 3 places and 0 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 274 place count 474 transition count 885
Performed 8 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 8 Pre rules applied. Total rules applied 274 place count 474 transition count 877
Constant places removed 8 places and 0 transitions.
Iterating post reduction 4 with 8 rules applied. Total rules applied 282 place count 466 transition count 877
Symmetric choice reduction at 5 with 7 rule applications. Total rules 289 place count 466 transition count 877
Constant places removed 7 places and 25 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 5 places :[p625, p486, p384, p190, p23]
Performed 6 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 20 rules applied. Total rules applied 309 place count 454 transition count 844
Constant places removed 6 places and 0 transitions.
Iterating post reduction 6 with 6 rules applied. Total rules applied 315 place count 448 transition count 844
Symmetric choice reduction at 7 with 3 rule applications. Total rules 318 place count 448 transition count 844
Constant places removed 3 places and 10 transitions.
Iterating post reduction 7 with 3 rules applied. Total rules applied 321 place count 445 transition count 834
Symmetric choice reduction at 8 with 1 rule applications. Total rules 322 place count 445 transition count 834
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 323 place count 444 transition count 826
Symmetric choice reduction at 9 with 1 rule applications. Total rules 324 place count 444 transition count 826
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 325 place count 443 transition count 818
Symmetric choice reduction at 10 with 1 rule applications. Total rules 326 place count 443 transition count 818
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 327 place count 442 transition count 810
Symmetric choice reduction at 11 with 1 rule applications. Total rules 328 place count 442 transition count 810
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 329 place count 441 transition count 802
Symmetric choice reduction at 12 with 1 rule applications. Total rules 330 place count 441 transition count 802
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 331 place count 440 transition count 794
Symmetric choice reduction at 13 with 1 rule applications. Total rules 332 place count 440 transition count 794
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 333 place count 439 transition count 786
Symmetric choice reduction at 14 with 1 rule applications. Total rules 334 place count 439 transition count 786
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 335 place count 438 transition count 778
Symmetric choice reduction at 15 with 1 rule applications. Total rules 336 place count 438 transition count 778
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 337 place count 437 transition count 770
Symmetric choice reduction at 16 with 1 rule applications. Total rules 338 place count 437 transition count 770
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 339 place count 436 transition count 762
Symmetric choice reduction at 17 with 1 rule applications. Total rules 340 place count 436 transition count 762
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 341 place count 435 transition count 754
Symmetric choice reduction at 18 with 1 rule applications. Total rules 342 place count 435 transition count 754
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 343 place count 434 transition count 746
Symmetric choice reduction at 19 with 1 rule applications. Total rules 344 place count 434 transition count 746
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 345 place count 433 transition count 738
Symmetric choice reduction at 20 with 1 rule applications. Total rules 346 place count 433 transition count 738
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 347 place count 432 transition count 730
Symmetric choice reduction at 21 with 1 rule applications. Total rules 348 place count 432 transition count 730
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 349 place count 431 transition count 722
Symmetric choice reduction at 22 with 1 rule applications. Total rules 350 place count 431 transition count 722
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 351 place count 430 transition count 714
Performed 7 Post agglomeration using F-continuation condition.
Constant places removed 7 places and 0 transitions.
Iterating post reduction 23 with 7 rules applied. Total rules applied 358 place count 423 transition count 707
Applied a total of 358 rules in 549 ms. Remains 423 /626 variables (removed 203) and now considering 707/1008 (removed 301) transitions.
// Phase 1: matrix 707 rows 423 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 707 rows 423 cols
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + -1'p100 + p123 + p125 + p126 + p127 + p128 + p129 + p130 + p131 + p132 + p135 + -1'p136 + -1'p137 + -1'p145 + -1'p156 + -1'p176 + -1'p210 + -1'p213 + p215 + p218 + -1'p399 = -1
invariant :p313 + p339 + p361 + p381 + p423 = 1
invariant :p248 + p319 + p321 + p323 + p325 + p345 + p347 + p367 = 1
invariant :p545 + p546 + p547 + -1'p550 + -1'p551 + -1'p552 = 0
invariant :p38 + p40 + p42 + p44 + p46 + p48 + p50 + p52 + -1'p268 + -1'p270 + -1'p272 + -1'p274 + -1'p276 + -1'p278 + -1'p280 + -1'p282 = 0
invariant :p20 + p22 + p25 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p343 + p345 + p346 + p347 + p348 + p350 + p351 + -1'p352 + -1'p353 + -1'p361 = 0
invariant :p229 + p290 + p296 + p297 + p298 + p300 + p302 + p304 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + -1'p423 = 0
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + -1'p405 + -1'p406 + -1'p408 + p410 + -1'p412 + -1'p414 + p463 + p465 + p467 + p469 + p471 + p473 + p475 + p477 + p479 + p481 + -1'p512 + p515 + -1'p520 + p523 + -1'p526 + p529 + -1'p532 + p535 + -1'p538 + -1'p544 + p547 + -1'p552 + p555 + -1'p558 + -1'p564 + p567 + -1'p572 + -1'p578 = -1
invariant :p482 + -1'p584 + -1'p590 + -1'p596 + -1'p615 = 0
invariant :p212 + p215 + p218 + -1'p399 = 0
invariant :p484 + p584 + p590 + p596 + p615 = 1
invariant :p489 + p490 + p491 + p492 + p493 + p494 + p495 + p496 + p504 + p510 + p511 + p512 + p518 + p519 + p520 + p524 + p525 + p526 + p530 + p531 + p532 + p536 + p537 + p538 + p542 + p543 + p544 + p550 + p551 + p552 + p556 + p557 + p558 + p562 + p563 + p564 + p570 + p571 + p572 + p576 + p577 + p578 + p585 + p586 + p587 + p591 + p592 + p593 + p597 + p598 + p599 + p610 + p611 + p612 + p616 + p617 + p618 = 1
invariant :p573 + p574 + p575 + -1'p576 + -1'p577 + -1'p578 = 0
invariant :p22 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p34 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p292 + p294 + p295 + -1'p296 + -1'p297 + -1'p298 + -1'p299 + -1'p300 + -1'p301 + -1'p302 + -1'p303 + -1'p304 + -1'p305 + p339 + p361 + p381 + p423 = 1
invariant :p2 + p4 + p6 + p8 + p10 + p12 + p14 + p16 + p18 + p27 + p30 + p32 + p34 + p74 + p76 + p78 + p80 + p82 + p84 + p86 + p88 = 1
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p294 + p328 + p350 + p370 + p404 + p405 = 1
invariant :p73 + p74 + p75 + p76 + p77 + p78 + p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + p89 + -1'p92 = 0
invariant :p266 + p286 = 1
invariant :p464 + -1'p515 + -1'p523 + -1'p529 + -1'p535 + -1'p547 + -1'p555 + -1'p567 = 0
invariant :p204 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p35 + p96 + p102 + p103 + p104 + p106 + p108 + p110 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + -1'p228 = 0
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + p214 + p215 + p216 = 0
invariant :p171 + p173 + p174 + p176 + p177 + -1'p178 + -1'p179 + -1'p187 = 0
invariant :p422 + p423 = 1
invariant :-1'p232 + -1'p234 + -1'p236 + -1'p238 + -1'p240 + -1'p242 + -1'p244 + -1'p246 + p426 + p428 + p430 + p432 + p434 + p436 + p438 + p440 = 0
invariant :p559 + p560 + p561 + -1'p562 + -1'p563 + -1'p564 = 0
invariant :p579 + p580 + -1'p585 + -1'p586 + -1'p587 = 0
invariant :p424 + p489 + p491 + p493 + p495 + p587 + p593 + p599 + p612 + p618 = 1
invariant :p461 + -1'p507 + -1'p541 + -1'p561 + -1'p575 = 0
invariant :p267 + p268 + p269 + p270 + p271 + p272 + p273 + p274 + p275 + p276 + p277 + p278 + p279 + p280 + p281 + p282 + p283 + -1'p286 = 0
invariant :p231 + p232 + p233 + p234 + p235 + p236 + p237 + p238 + p239 + p240 + p241 + p242 + p243 + p244 + p245 + p246 + p247 + -1'p290 + -1'p296 + -1'p297 + -1'p298 + -1'p300 + -1'p302 + -1'p304 + -1'p330 + -1'p331 + -1'p352 + -1'p353 + -1'p372 + -1'p373 + -1'p387 + p423 = 1
invariant :p21 + -1'p22 + -1'p25 + -1'p29 + -1'p30 + -1'p31 + -1'p32 + -1'p34 + -1'p213 + p215 + p218 + -1'p399 = 0
invariant :p119 + p145 + p167 + p187 + p228 = 1
invariant :p533 + p534 + p535 + -1'p536 + -1'p537 + -1'p538 = 0
invariant :p149 + p151 + p152 + p153 + p154 + p156 + p157 + -1'p158 + -1'p159 + -1'p167 = 0
invariant :p505 + p506 + p507 + -1'p510 + -1'p511 + -1'p512 = 0
invariant :p3 + p5 + p7 + p9 + p11 + p13 + p15 + p17 + -1'p74 + -1'p76 + -1'p78 + -1'p80 + -1'p82 + -1'p84 + -1'p86 + -1'p88 = 0
invariant :p588 + p589 + p590 + -1'p591 + -1'p592 + -1'p593 = 0
invariant :p487 + p489 + p490 + p491 + p492 + p493 + p494 + p495 + p496 = 1
invariant :p539 + p540 + p541 + -1'p542 + -1'p543 + -1'p544 = 0
invariant :p594 + p595 + p596 + -1'p597 + -1'p598 + -1'p599 = 0
invariant :p72 + p92 = 1
invariant :p1 + -1'p27 + -1'p30 + -1'p32 + -1'p34 = 0
invariant :p462 + p465 + p466 + p467 + p468 + p469 + p470 + p471 + p472 + p473 + p474 + p475 + p476 + p477 + p478 + p479 + p480 + p481 + p506 + p507 + -1'p511 + -1'p512 + p514 + p515 + -1'p519 + -1'p520 + p522 + p523 + -1'p525 + -1'p526 + p528 + p529 + -1'p531 + -1'p532 + p534 + p535 + -1'p537 + -1'p538 + -1'p539 + p542 + p546 + p547 + -1'p551 + -1'p552 + p554 + p555 + -1'p557 + -1'p558 + -1'p559 + p562 + p566 + p567 + -1'p571 + -1'p572 + -1'p573 + p576 = 0
invariant :p98 + p100 + p101 + -1'p102 + -1'p103 + -1'p104 + -1'p105 + -1'p106 + -1'p107 + -1'p108 + -1'p109 + -1'p110 + -1'p111 + p145 + p167 + p187 + p228 = 1
invariant :p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 + p70 + p71 + -1'p125 + -1'p127 + -1'p129 + -1'p131 + -1'p151 + -1'p153 + -1'p173 = 0
invariant :p606 + p607 + -1'p610 + -1'p611 + -1'p612 = 0
invariant :p613 + p614 + p615 + -1'p616 + -1'p617 + -1'p618 = 0
invariant :p37 + p39 + p41 + p43 + p45 + p47 + p49 + p51 + p53 + -1'p96 + -1'p102 + -1'p103 + -1'p104 + -1'p106 + -1'p108 + -1'p110 + -1'p136 + -1'p137 + -1'p158 + -1'p159 + -1'p178 + -1'p179 + -1'p193 + p228 + p268 + p270 + p272 + p274 + p276 + p278 + p280 + p282 = 1
invariant :p54 + p125 + p127 + p129 + p131 + p151 + p153 + p173 = 1
invariant :p285 + p286 + p287 + p290 + p296 + p297 + p298 + p299 + p300 + p301 + p302 + p303 + p304 + p305 + p330 + p331 + p352 + p353 + p372 + p373 + p387 + p391 + p397 + -1'p423 = 0
invariant :p553 + p554 + p555 + -1'p556 + -1'p557 + -1'p558 = 0
invariant :-1'p404 + p406 + p407 + p408 = 0
invariant :p513 + p514 + p515 + -1'p518 + -1'p519 + -1'p520 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p100 + p134 + p156 + p176 + p210 + p213 + -1'p215 + -1'p218 + p399 = 1
invariant :p459 + p512 + p520 + p526 + p532 + p538 + p544 + p552 + p558 + p564 + p572 + p578 = 1
invariant :-1'p250 + -1'p252 + -1'p254 + -1'p256 + -1'p258 + -1'p260 + -1'p262 + -1'p264 + -1'p294 + p317 + p319 + p320 + p321 + p322 + p323 + p324 + p325 + p326 + p329 + -1'p330 + -1'p331 + -1'p339 + -1'p350 + -1'p370 + -1'p404 + -1'p405 = -1
invariant :p527 + p528 + p529 + -1'p530 + -1'p531 + -1'p532 = 0
invariant :p365 + p367 + p368 + p370 + p371 + -1'p372 + -1'p373 + -1'p381 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p210 + p213 + -1'p215 + p217 + p219 + p399 = 1
invariant :p227 + p228 = 1
invariant :p521 + p522 + p523 + -1'p524 + -1'p525 + -1'p526 = 0
invariant :p565 + p566 + p567 + -1'p570 + -1'p571 + -1'p572 = 0
invariant :p250 + p252 + p254 + p256 + p258 + p260 + p262 + p264 + p404 + p405 + p412 + p413 + p414 = 1
invariant :p398 + p399 = 1
invariant :-1'p399 + p402 + p403 + p404 = 0
invariant :p232 + p234 + p236 + p238 + p240 + p242 + p244 + p246 + p425 + p427 + p429 + p431 + p433 + p435 + p437 + p439 + p441 + -1'p489 + -1'p491 + -1'p493 + -1'p495 + -1'p587 + -1'p593 + -1'p599 + -1'p612 + -1'p618 = 0
invariant :p405 + p406 + p408 + p409 + p411 + p412 + p414 + -1'p463 + -1'p465 + -1'p467 + -1'p469 + -1'p471 + -1'p473 + -1'p475 + -1'p477 + -1'p479 + -1'p481 + p512 + -1'p515 + p520 + -1'p523 + p526 + -1'p529 + p532 + -1'p535 + p538 + p544 + -1'p547 + p552 + -1'p555 + p558 + p564 + -1'p567 + p572 + p578 = 1
invariant :p91 + p92 + p93 + p96 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + p109 + p110 + p111 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + p197 + p203 + -1'p228 = 0
invariant :p249 + p250 + p251 + p252 + p253 + p254 + p255 + p256 + p257 + p258 + p259 + p260 + p261 + p262 + p263 + p264 + p265 + -1'p319 + -1'p321 + -1'p323 + -1'p325 + -1'p345 + -1'p347 + -1'p367 = 0
invariant :p460 + p463 + -1'p506 + p511 + -1'p514 + p519 + -1'p522 + p525 + -1'p528 + p531 + -1'p534 + p537 + p539 + p541 + -1'p542 + -1'p544 + -1'p546 + p551 + -1'p554 + p557 + p559 + p561 + -1'p562 + -1'p564 + -1'p566 + p571 + p573 + p575 + -1'p576 + -1'p578 = 0
invariant :p582 + p583 + p584 + -1'p585 + -1'p586 + -1'p587 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12188 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 84 ms.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.79898e+10,74.2434,1309980,2,33818,5,3.50004e+06,6,0,2402,5.46038e+06,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,2.67658e+06,93.7844,1309980,2,7877,7,3.50004e+06,9,1,12319,5.46038e+06,2

System contains 2.67658e+06 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-02a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 2676577 states ] showing 10 first states
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p53=1 p210=1 p193=1 p54=1 p72=1 p18=1 p21=1 p31=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p53=1 p210=1 p193=1 p22=1 p54=1 p72=1 p18=1 p21=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p108=1 p54=1 p72=1 p18=1 p21=1 p31=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p110=1 p54=1 p72=1 p18=1 p21=1 p31=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p106=1 p54=1 p72=1 p18=1 p21=1 p31=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p22=1 p108=1 p54=1 p72=1 p18=1 p21=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p22=1 p110=1 p54=1 p72=1 p18=1 p21=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p22=1 p106=1 p54=1 p72=1 p18=1 p21=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p102=1 p54=1 p72=1 p18=1 p21=1 p31=1 ]
[ p484=1 p459=1 p491=1 p414=1 p441=1 p328=1 p423=1 p331=1 p231=1 p248=1 p266=1 p228=1 p398=1 p204=1 p98=1 p53=1 p210=1 p102=1 p22=1 p54=1 p72=1 p18=1 p21=1 ]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527760885390

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 9:59:47 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 31, 2018 9:59:47 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 9:59:47 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 179 ms
May 31, 2018 9:59:47 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 626 places.
May 31, 2018 9:59:47 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1008 transitions.
May 31, 2018 9:59:47 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 9:59:47 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 48 ms
May 31, 2018 9:59:48 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 348 ms
May 31, 2018 9:59:48 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 11 ms
May 31, 2018 9:59:48 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1008 transitions.
May 31, 2018 9:59:49 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 4 ms
May 31, 2018 9:59:49 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 707 transitions.
May 31, 2018 9:59:50 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 74 place invariants in 108 ms
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 423 variables to be positive in 1102 ms
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 707 transitions.
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/707 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 72 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 707 transitions.
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 38 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 9:59:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 707 transitions.
May 31, 2018 9:59:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/707) took 3187 ms. Total solver calls (SAT/UNSAT): 1734(282/1452)
May 31, 2018 9:59:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/707) took 6205 ms. Total solver calls (SAT/UNSAT): 3918(2363/1555)
May 31, 2018 10:00:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(58/707) took 9314 ms. Total solver calls (SAT/UNSAT): 6834(5279/1555)
May 31, 2018 10:00:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/707) took 12388 ms. Total solver calls (SAT/UNSAT): 9826(8271/1555)
May 31, 2018 10:00:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(144/707) took 15403 ms. Total solver calls (SAT/UNSAT): 12553(10998/1555)
May 31, 2018 10:00:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(186/707) took 18452 ms. Total solver calls (SAT/UNSAT): 17066(11226/5840)
May 31, 2018 10:00:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(241/707) took 21475 ms. Total solver calls (SAT/UNSAT): 20916(11387/9529)
May 31, 2018 10:00:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(288/707) took 24653 ms. Total solver calls (SAT/UNSAT): 23017(12482/10535)
May 31, 2018 10:00:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(309/707) took 27687 ms. Total solver calls (SAT/UNSAT): 24834(14019/10815)
May 31, 2018 10:00:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(337/707) took 30724 ms. Total solver calls (SAT/UNSAT): 27225(16186/11039)
May 31, 2018 10:00:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(360/707) took 33820 ms. Total solver calls (SAT/UNSAT): 30376(19337/11039)
May 31, 2018 10:00:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(386/707) took 36871 ms. Total solver calls (SAT/UNSAT): 33301(22262/11039)
May 31, 2018 10:00:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(421/707) took 39920 ms. Total solver calls (SAT/UNSAT): 36171(25132/11039)
May 31, 2018 10:00:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(478/707) took 44567 ms. Total solver calls (SAT/UNSAT): 38558(26955/11603)
May 31, 2018 10:00:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(486/707) took 48384 ms. Total solver calls (SAT/UNSAT): 38996(27197/11799)
May 31, 2018 10:00:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(497/707) took 52334 ms. Total solver calls (SAT/UNSAT): 39536(27485/12051)
May 31, 2018 10:00:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(504/707) took 56100 ms. Total solver calls (SAT/UNSAT): 39852(27636/12216)
May 31, 2018 10:00:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(511/707) took 60382 ms. Total solver calls (SAT/UNSAT): 40149(27819/12330)
May 31, 2018 10:00:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(535/707) took 63390 ms. Total solver calls (SAT/UNSAT): 40825(28083/12742)
May 31, 2018 10:00:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(575/707) took 66433 ms. Total solver calls (SAT/UNSAT): 41727(28749/12978)
May 31, 2018 10:01:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(635/707) took 69467 ms. Total solver calls (SAT/UNSAT): 43083(29771/13312)
May 31, 2018 10:01:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 72127 ms. Total solver calls (SAT/UNSAT): 43531(30019/13512)
May 31, 2018 10:01:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 707 transitions.
May 31, 2018 10:01:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 7539 ms. Total solver calls (SAT/UNSAT): 4796(0/4796)
May 31, 2018 10:01:11 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 81630ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-02a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-02a.tgz
mv ASLink-PT-02a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ASLink-PT-02a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749148700026"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;