About the Execution of ITS-Tools.L for ParamProductionCell-PT-0
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15755.840 | 64705.00 | 180063.00 | 185.00 | FFTFFFFFTFTFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 292K
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.8K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.8K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 115 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 353 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 144K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ParamProductionCell-PT-0, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r261-csrt-152732585900099
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-00
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-01
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-02
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-03
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-04
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-05
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-06
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-07
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-08
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-09
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-10
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-11
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-12
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-13
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-14
FORMULA_NAME ParamProductionCell-PT-0-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1527502732476
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("(deposit_belt_empty>=1)"))
Formula 0 simplified : !"(deposit_belt_empty>=1)"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 176 rows 198 cols
invariant :arm2_stop + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run = 1
invariant :arm2_magnet_off + arm2_magnet_on = 1
invariant :press_stop + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_lower_rs + PL_lower_run = 1
invariant :arm2_backward + -1'A2U_ret_rs + -1'A2U_ret_run + -1'A2L_ret_rs + -1'A2L_ret_run = 0
invariant :table_upward + -1'TL_lower_rs + -1'TL_lower_run + -1'TU_lift_rs + -1'TU_lift_run = 0
invariant :robot_stop + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run = 1
invariant :belt1_light_barrier_true + belt1_light_barrier_false = 1
invariant :deposit_belt_idle + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :arm2_storing + arm2_having_swivel_1 + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended + -1'arm2_magnet_on + A2U_ext_rs + A2U_ext_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = 0
invariant :press_upward + -1'forge_rs + -1'forge_run = 0
invariant :arm1_storing + arm1_having_swivel_1 + arm1_waiting_for_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_ext_rs + A1U_ext_run = 1
invariant :belt2_start + -1'DB_trans_rs + -1'DB_trans_run + -1'DB_deliver_rs + -1'DB_deliver_run = 0
invariant :c_p2 + c_p1 = 1
invariant :ch_FT_free + ch_FT_full + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :p_p2 + p_p1 = 1
invariant :press_up + -1'PL_lower_rs + -1'PL_lower_run = 0
invariant :arm2_release_ext + arm2_retract_ext + arm2_pick_up_ext = 1
invariant :ch_TA1_full + ch_TA1_free + -1'table_ready_for_unloading + -1'arm1_store_free + -1'arm1_having_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + -1'A1U_out + -1'A1U_unloadet + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :belt1_stop + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm2_forward + -1'A2U_ext_rs + -1'A2U_ext_run + -1'A2L_ext_rs + -1'A2L_ext_run = 0
invariant :ch_CF_free + ch_CF_full + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm1_magnet_on + arm1_magnet_off = 1
invariant :table_bottom_pos + table_top_pos = 1
invariant :robot_left + -1'A2U_rot2_rs + -1'A2U_rot2_run + -1'A2L_rot1_rs + -1'A2L_rot1_run + -1'A2L_rot2_rs + -1'A2L_rot2_run + -1'A2L_rot3_rs + -1'A2L_rot3_run + -1'A1L_rot1_rs + -1'A1L_rot1_run + -1'A1L_rot2_rs + -1'A1L_rot2_run + -1'A1L_rot3_rs + -1'A1L_rot3_run + -1'A1U_rot3_rs + -1'A1U_rot3_run = 0
invariant :arm1_store_free + arm1_waiting_for_swivel_1 + arm1_having_swivel_2 + A1L_rotated + A1L_in + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended + -1'arm1_magnet_off + A1L_ext_rs + A1L_ext_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :arm1_forward + -1'A1L_ext_rs + -1'A1L_ext_run + -1'A1U_ext_rs + -1'A1U_ext_run = 0
invariant :table_ready_for_loading + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run = 1
invariant :arm2_release_angle + arm1_pick_up_angle + arm1_release_angle + arm2_pick_up_angle = 1
invariant :table_load_angle + table_unload_angle = 1
invariant :arm1_pick_up_ext + arm1_retract_ext + arm1_release_ext = 1
invariant :ch_A1P_full + ch_A1P_free + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run + -1'arm1_storing + -1'arm1_having_swivel_1 + -1'A1L_out + -1'A1L_loaded + -1'arm1_magnet_off + -1'A1L_ret_rs + -1'A1L_ret_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :table_stop_v + TL_lower_rs + TL_lower_run + TU_lift_rs + TU_lift_run = 1
invariant :belt1_start + -1'FB_trans_rs + -1'FB_trans_run + -1'FB_deliver_rs + -1'FB_deliver_run = 0
invariant :press_at_upper_pos + press_at_lower_pos + press_at_middle_pos = 1
invariant :belt2_stop + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :ch_A2D_full + ch_A2D_free + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run + -1'arm2_storing + -1'arm2_having_swivel_1 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + -1'A2L_out + -1'A2L_loaded + -1'A2L_ret_rs + -1'A2L_ret_run = 1
invariant :table_stop_h + TL_rot_rs + TL_rot_run + TU_rot_rs + TU_rot_run = 1
invariant :table_right + -1'TL_rot_rs + -1'TL_rot_run + -1'TU_rot_rs + -1'TU_rot_run = 0
invariant :arm1_backward + -1'A1L_ret_rs + -1'A1L_ret_run + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :swivel + -1'arm2_store_free + -1'arm2_waiting_for_swivel_1 + -1'arm2_storing + -1'arm2_waiting_for_swivel_2 + -1'arm1_store_free + -1'arm1_waiting_for_swivel_1 + -1'arm1_storing + -1'arm1_waiting_for_swivel_2 = -1
invariant :ch_DC_full + ch_DC_free + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :arm1_stop + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
invariant :feed_belt_idle + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :press_down + -1'PU_lower_rs + -1'PU_lower_run = 0
invariant :robot_right + -1'A2U_rot1_rs + -1'A2U_rot1_run + -1'A2U_rot3_rs + -1'A2U_rot3_run + -1'A1U_rot1_rs + -1'A1U_rot1_run + -1'A1U_rot2_rs + -1'A1U_rot2_run = 0
invariant :belt2_light_barrier_true + belt2_light_barrier_false = 1
invariant :arm2_store_free + arm2_waiting_for_swivel_1 + arm2_having_swivel_2 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + A2L_rotated + A2L_in + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_ext_rs + A2L_ext_run = 1
invariant :ch_PA2_free + ch_PA2_full + -1'press_ready_for_unloading + -1'arm2_store_free + -1'arm2_having_swivel_2 + -1'A2U_out + -1'A2U_unloaded + -1'arm2_magnet_on + -1'A2U_ret_rs + -1'A2U_ret_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = -1
invariant :press_ready_for_loading + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run = 1
Reverse transition relation is NOT exact ! Due to transitions PU_lower_Pstart, forge_Pstart, PL_lower_Pstart, TL_rot_Pstart, TL_lower_Pstart, TU_lift_Pstart, TU_rot_Pstart, DB_trans_Pstart, DB_deliver_Pstart, FB_trans_Pstart, FB_deliver_Pstart, arm2_unlock_swivel_1, arm2_unlock_swivel_2, A2U_rot1_Pstop, A2U_rot1_Pstart, A2U_rot2_Pstop, A2U_rot2_Pstart, A2U_rot3_Pstop, A2U_rot3_Pstart, A2U_ext_Pstart, A2U_ret_Pstart, A2L_rot1_Pstop, A2L_rot1_Pstart, A2L_rot2_Pstop, A2L_rot2_Pstart, A2L_rot3_Pstart, A2L_ext_Pstart, A2L_ret_Pstart, arm1_unlock_swivel_1, arm1_unlock_swivel_2, A1L_rot1_Pstop, A1L_rot1_Pstart, A1L_rot2_Pstop, A1L_rot2_Pstart, A1L_rot3_Pstop, A1L_rot3_Pstart, A1L_ext_Pstart, A1L_ret_Pstart, A1U_rot1_Pstart, A1U_rot2_Pstop, A1U_rot2_Pstart, A1U_rot3_Pstop, A1U_rot3_Pstart, A1U_ext_Pstart, A1U_ret_Pstart, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/131/45/176
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
706 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,7.15031,165308,1,0,311,544955,378,179,6303,406100,373
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !(((G(F("(TU_lift_rs<=ch_TA1_full)")))U(("(A1U_rot1_run>=2)")U("(A2U_rot2_rs>=3)"))))
Formula 1 simplified : !(GF"(TU_lift_rs<=ch_TA1_full)" U ("(A1U_rot1_run>=2)" U "(A2U_rot2_rs>=3)"))
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
2889 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,36.044,738492,1,0,1100,3.64626e+06,393,833,6315,4.10203e+06,3658
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((F((F("(arm2_waiting_for_swivel_1>=1)"))U(F("(A1U_ext_run<=arm1_waiting_for_swivel_2)")))))
Formula 2 simplified : !F(F"(arm2_waiting_for_swivel_1>=1)" U F"(A1U_ext_run<=arm1_waiting_for_swivel_2)")
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,36.0457,738492,1,0,1100,3.64626e+06,402,833,6319,4.10204e+06,3662
no accepting run found
Formula 2 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !(((F(X("(c_p1>=2)")))U(("(A2U_ext_run>=1)")U("(arm1_magnet_on>=3)"))))
Formula 3 simplified : !(FX"(c_p1>=2)" U ("(A2U_ext_run>=1)" U "(arm1_magnet_on>=3)"))
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
211 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,38.1603,801024,1,0,1105,3.66764e+06,417,835,6326,4.13969e+06,6305
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 4 : !((X(F(X(G("(deposit_belt_empty>=3)"))))))
Formula 4 simplified : !XFXG"(deposit_belt_empty>=3)"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
110 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,39.2582,831116,1,0,1240,3.6848e+06,430,970,6328,4.18308e+06,9333
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 5 : !((F("(belt1_light_barrier_true>=3)")))
Formula 5 simplified : !F"(belt1_light_barrier_true>=3)"
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
129 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,40.5523,859100,1,0,1375,3.69526e+06,439,1106,6330,4.20815e+06,11055
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 6 : !((F(X(G(F("(ch_PA2_full>=2)"))))))
Formula 6 simplified : !FXGF"(ch_PA2_full>=2)"
4 unique states visited
4 strongly connected components in search stack
5 transitions explored
4 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,40.5561,859340,1,0,1375,3.69526e+06,448,1106,6332,4.20818e+06,11061
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 7 : !((F((G("(press_down>=1)"))U(G("(A2L_extended>=2)")))))
Formula 7 simplified : !F(G"(press_down>=1)" U G"(A2L_extended>=2)")
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
313 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,43.6876,885700,1,0,1375,3.69526e+06,461,1106,6334,4.20821e+06,13692
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 8 : !((X(F("(TL_lower_rs>=1)"))))
Formula 8 simplified : !XF"(TL_lower_rs>=1)"
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
91 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,44.5889,886756,1,0,1915,3.80345e+06,470,1197,6335,4.30174e+06,14915
no accepting run found
Formula 8 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 9 : !((G(X("(arm2_release_ext<=table_unload_angle)"))))
Formula 9 simplified : !GX"(arm2_release_ext<=table_unload_angle)"
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1140 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,55.9932,1110648,1,0,3068,5.07736e+06,476,1753,6340,6.00496e+06,17908
an accepting run exists (use option '-e' to print it)
Formula 9 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 10 : !(((("(A2L_ret_rs<=PL_out)")U("(FB_in>=1)"))U("(FB_deliver_run<=ch_A1P_full)")))
Formula 10 simplified : !(("(A2L_ret_rs<=PL_out)" U "(FB_in>=1)") U "(FB_deliver_run<=ch_A1P_full)")
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,55.9952,1111084,1,0,3068,5.07736e+06,498,1753,6360,6.00496e+06,17914
no accepting run found
Formula 10 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 11 : !(("(PL_out>=2)"))
Formula 11 simplified : !"(PL_out>=2)"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,55.9955,1111084,1,0,3068,5.07736e+06,501,1753,6362,6.00496e+06,17916
an accepting run exists (use option '-e' to print it)
Formula 11 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 12 : !((X(X(G(X("(arm2_having_swivel_2<=arm2_storing)"))))))
Formula 12 simplified : !XXGX"(arm2_having_swivel_2<=arm2_storing)"
Compilation finished in 3552 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 102 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X([](X((LTLAP20==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 923 ms.
FORMULA ParamProductionCell-PT-0-LTLCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP21==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 120 ms.
FORMULA ParamProductionCell-PT-0-LTLCardinality-13 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]([]((LTLAP22==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 181 ms.
FORMULA ParamProductionCell-PT-0-LTLCardinality-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP23==true))U([](X((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 134 ms.
FORMULA ParamProductionCell-PT-0-LTLCardinality-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.
BK_STOP 1527502797181
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 10:18:55 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 28, 2018 10:18:55 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 10:18:55 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 137 ms
May 28, 2018 10:18:55 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 198 places.
May 28, 2018 10:18:55 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 176 transitions.
May 28, 2018 10:18:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 18 ms
May 28, 2018 10:18:55 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 121 ms
May 28, 2018 10:18:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 8 ms
May 28, 2018 10:18:55 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 1 ms
May 28, 2018 10:18:57 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 176 transitions.
May 28, 2018 10:18:57 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 49 place invariants in 155 ms
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 198 variables to be positive in 2742 ms
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 176 transitions.
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/176 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 46 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 176 transitions.
May 28, 2018 10:19:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 4 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:19:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 176 transitions.
May 28, 2018 10:19:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/176) took 121 ms. Total solver calls (SAT/UNSAT): 28(13/15)
May 28, 2018 10:19:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/176) took 3435 ms. Total solver calls (SAT/UNSAT): 299(182/117)
May 28, 2018 10:19:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/176) took 6459 ms. Total solver calls (SAT/UNSAT): 669(234/435)
May 28, 2018 10:19:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(49/176) took 9470 ms. Total solver calls (SAT/UNSAT): 999(390/609)
May 28, 2018 10:19:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/176) took 12755 ms. Total solver calls (SAT/UNSAT): 1311(515/796)
May 28, 2018 10:19:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(76/176) took 17010 ms. Total solver calls (SAT/UNSAT): 1806(657/1149)
May 28, 2018 10:19:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(88/176) took 20336 ms. Total solver calls (SAT/UNSAT): 2231(740/1491)
May 28, 2018 10:19:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/176) took 23498 ms. Total solver calls (SAT/UNSAT): 2886(784/2102)
May 28, 2018 10:19:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(118/176) took 26675 ms. Total solver calls (SAT/UNSAT): 2991(851/2140)
May 28, 2018 10:19:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(120/176) took 29805 ms. Total solver calls (SAT/UNSAT): 3053(881/2172)
May 28, 2018 10:19:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(125/176) took 33507 ms. Total solver calls (SAT/UNSAT): 3200(951/2249)
May 28, 2018 10:19:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(131/176) took 37360 ms. Total solver calls (SAT/UNSAT): 3386(1020/2366)
May 28, 2018 10:19:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(139/176) took 40636 ms. Total solver calls (SAT/UNSAT): 3598(1094/2504)
May 28, 2018 10:19:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(157/176) took 43697 ms. Total solver calls (SAT/UNSAT): 3899(1098/2801)
May 28, 2018 10:19:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 45817 ms. Total solver calls (SAT/UNSAT): 3968(1099/2869)
May 28, 2018 10:19:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 176 transitions.
May 28, 2018 10:19:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1224 ms. Total solver calls (SAT/UNSAT): 55(0/55)
May 28, 2018 10:19:51 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 54163ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-0"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-0.tgz
mv ParamProductionCell-PT-0 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ParamProductionCell-PT-0, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r261-csrt-152732585900099"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;