Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................................................
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 39K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 26K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 36K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 200K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is LamportFastMutEx-PT-6, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r261-csrt-152732585800040
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-6-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527499805021

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph2459857728110736850.txt, -o, /tmp/graph2459857728110736850.bin, -w, /tmp/graph2459857728110736850.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph2459857728110736850.bin, -l, -1, -v, -w, /tmp/graph2459857728110736850.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((("(((((((((((((((((((((((((((((((((((((((((((i0.u0.y_1>=1)&&(i3.u71.P_ifyi_15_0>=1))||((i0.u0.y_2>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_3>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_4>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_5>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_6>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_0>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_2>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_3>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_4>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_5>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_6>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_0>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_1>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_3>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_4>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_5>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_6>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_0>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_1>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_2>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_4>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_5>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_6>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_0>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_1>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_2>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_3>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_5>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_6>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_0>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_1>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_2>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_3>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_4>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_6>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_0>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_1>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_2>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_3>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_4>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_5>=1)&&(i2.u76.P_ifyi_15_6>=1)))")U(X(X(F("(((((((((((((((((((((((((((((((((((((((((((i0.u0.y_1>=1)&&(i3.u71.P_ifyi_15_0>=1))||((i0.u0.y_2>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_3>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_4>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_5>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_6>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_0>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_2>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_3>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_4>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_5>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_6>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_0>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_1>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_3>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_4>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_5>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_6>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_0>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_1>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_2>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_4>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_5>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_6>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_0>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_1>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_2>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_3>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_5>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_6>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_0>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_1>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_2>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_3>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_4>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_6>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_0>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_1>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_2>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_3>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_4>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_5>=1)&&(i2.u76.P_ifyi_15_6>=1)))"))))))
Formula 0 simplified : !("(((((((((((((((((((((((((((((((((((((((((((i0.u0.y_1>=1)&&(i3.u71.P_ifyi_15_0>=1))||((i0.u0.y_2>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_3>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_4>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_5>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_6>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_0>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_2>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_3>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_4>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_5>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_6>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_0>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_1>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_3>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_4>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_5>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_6>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_0>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_1>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_2>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_4>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_5>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_6>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_0>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_1>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_2>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_3>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_5>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_6>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_0>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_1>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_2>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_3>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_4>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_6>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_0>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_1>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_2>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_3>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_4>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_5>=1)&&(i2.u76.P_ifyi_15_6>=1)))" U XXF"(((((((((((((((((((((((((((((((((((((((((((i0.u0.y_1>=1)&&(i3.u71.P_ifyi_15_0>=1))||((i0.u0.y_2>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_3>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_4>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_5>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_6>=1)&&(i3.u71.P_ifyi_15_0>=1)))||((i0.u0.y_0>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_2>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_3>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_4>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_5>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_6>=1)&&(i4.u72.P_ifyi_15_1>=1)))||((i0.u0.y_0>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_1>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_3>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_4>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_5>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_6>=1)&&(i1.u73.P_ifyi_15_2>=1)))||((i0.u0.y_0>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_1>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_2>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_4>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_5>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_6>=1)&&(i7.u77.P_ifyi_15_3>=1)))||((i0.u0.y_0>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_1>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_2>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_3>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_5>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_6>=1)&&(i5.u74.P_ifyi_15_4>=1)))||((i0.u0.y_0>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_1>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_2>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_3>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_4>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_6>=1)&&(i6.u75.P_ifyi_15_5>=1)))||((i0.u0.y_0>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_1>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_2>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_3>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_4>=1)&&(i2.u76.P_ifyi_15_6>=1)))||((i0.u0.y_5>=1)&&(i2.u76.P_ifyi_15_6>=1)))")
built 36 ordering constraints for composite.
built 221 ordering constraints for composite.
built 70 ordering constraints for composite.
built 70 ordering constraints for composite.
built 77 ordering constraints for composite.
built 70 ordering constraints for composite.
built 70 ordering constraints for composite.
built 70 ordering constraints for composite.
built 70 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 315
// Phase 1: matrix 315 rows 217 cols
invariant :i4:u25:P_wait_1_5 + i4:u25:P_done_1_5 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i3:u1:P_b_0_false + i3:u1:P_b_0_true = 0
invariant :i5:u34:P_await_13_4 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i5:u34:P_wait_4_0 + i5:u34:P_done_4_0 = 0
invariant :i3:u49:P_wait_0_4 + i3:u49:P_done_0_4 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i2:u45:P_wait_6_5 + i2:u45:P_done_6_5 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i2:u42:P_wait_6_0 + i2:u42:P_done_6_0 = 0
invariant :i6:u41:P_wait_5_5 + i6:u41:P_done_5_5 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i6:u6:P_b_5_false + i6:u6:P_b_5_true = 1
invariant :i1:u27:P_await_13_2 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i3:u1:P_start_1_0 + i3:u1:P_fordo_12_0 + i3:u12:P_setx_3_0 + i3:u12:P_setbi_5_0 + i3:u12:P_ify0_4_0 + i3:u19:P_sety_9_0 + i3:u19:P_ifxi_10_0 + i3:u19:P_setbi_11_0 + i3:u71:P_ifyi_15_0 + i3:u71:P_awaity_0 + i3:u80:P_CS_21_0 + i3:u80:P_setbi_24_0 + i3:u51:P_wait_0_6 + i3:u51:P_done_0_6 = 0
invariant :i3:u23:P_wait_0_3 + i3:u23:P_done_0_3 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i2:u43:P_wait_6_1 + i2:u43:P_done_6_1 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i4:u2:P_b_1_false + i4:u2:P_b_1_true = 1
invariant :i7:u60:P_wait_3_2 + i7:u60:P_done_3_2 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i6:u40:P_wait_5_3 + i6:u40:P_done_5_3 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i2:u42:P_await_13_6 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i7:u32:P_wait_3_3 + i7:u32:P_done_3_3 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i6:u66:P_wait_5_2 + i6:u66:P_done_5_2 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i7:u31:P_wait_3_1 + i7:u31:P_done_3_1 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i7:u33:P_wait_3_4 + i7:u33:P_done_3_4 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i6:u39:P_await_13_5 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i6:u39:P_wait_5_0 + i6:u39:P_done_5_0 = 0
invariant :i6:u67:P_wait_5_4 + i6:u67:P_done_5_4 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i6:u65:P_wait_5_1 + i6:u65:P_done_5_1 + -1'i6:u68:P_wait_5_6 + -1'i6:u68:P_done_5_6 = 0
invariant :i3:u48:P_wait_0_2 + i3:u48:P_done_0_2 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i1:u56:P_wait_2_1 + i1:u56:P_done_2_1 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i0:u78:P_CS_21_3 + i0:u78:P_setbi_24_3 + i7:u4:P_start_1_3 + i7:u4:P_fordo_12_3 + i7:u9:P_setx_3_3 + i7:u9:P_setbi_5_3 + i7:u9:P_ify0_4_3 + i7:u21:P_sety_9_3 + i7:u21:P_ifxi_10_3 + i7:u21:P_setbi_11_3 + i7:u77:P_ifyi_15_3 + i7:u77:P_awaity_3 + i7:u62:P_wait_3_6 + i7:u62:P_done_3_6 = 1
invariant :i5:u5:P_b_4_false + i5:u5:P_b_4_true = 1
invariant :i4:u52:P_wait_1_0 + i4:u52:P_done_1_0 = 0
invariant :i7:u4:P_b_3_false + i7:u4:P_b_3_true = 1
invariant :i4:u26:P_wait_1_6 + i4:u26:P_done_1_6 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i1:u3:P_b_2_false + i1:u3:P_b_2_true = 1
invariant :i2:u7:P_b_6_false + i2:u7:P_b_6_true = 1
invariant :i7:u61:P_wait_3_5 + i7:u61:P_done_3_5 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i1:u28:P_wait_2_2 + i1:u28:P_done_2_2 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i5:u38:P_wait_4_6 + i5:u38:P_done_4_6 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i1:u29:P_wait_2_5 + i1:u29:P_done_2_5 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i5:u37:P_wait_4_3 + i5:u37:P_done_4_3 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i2:u44:P_wait_6_2 + i2:u44:P_done_6_2 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i7:u59:P_await_13_3 + -1'i7:u62:P_wait_3_6 + -1'i7:u62:P_done_3_6 = 0
invariant :i1:u27:P_wait_2_0 + i1:u27:P_done_2_0 = 0
invariant :i4:u54:P_wait_1_2 + i4:u54:P_done_1_2 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i2:u69:P_wait_6_3 + i2:u69:P_done_6_3 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i3:u47:P_wait_0_1 + i3:u47:P_done_0_1 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i4:u53:P_wait_1_1 + i4:u53:P_done_1_1 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i3:u22:P_wait_0_0 + i3:u22:P_done_0_0 = 0
invariant :i1:u8:x_2 + i2:u14:x_6 + i3:u12:x_0 + i4:u13:x_1 + i5:u10:x_4 + i6:u11:x_5 + i7:u9:x_3 = 1
invariant :i0:u79:P_CS_21_6 + i0:u79:P_setbi_24_6 + i2:u7:P_start_1_6 + i2:u7:P_fordo_12_6 + i2:u14:P_setx_3_6 + i2:u14:P_setbi_5_6 + i2:u14:P_ify0_4_6 + i2:u18:P_sety_9_6 + i2:u18:P_ifxi_10_6 + i2:u18:P_setbi_11_6 + i2:u76:P_ifyi_15_6 + i2:u76:P_awaity_6 + i2:u70:P_wait_6_4 + i2:u70:P_done_6_4 = 1
invariant :i3:u50:P_wait_0_5 + i3:u50:P_done_0_5 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i0:u83:P_CS_21_4 + i0:u83:P_setbi_24_4 + i5:u5:P_start_1_4 + i5:u5:P_fordo_12_4 + i5:u10:P_setx_3_4 + i5:u10:P_setbi_5_4 + i5:u10:P_ify0_4_4 + i5:u16:P_sety_9_4 + i5:u16:P_ifxi_10_4 + i5:u16:P_setbi_11_4 + i5:u74:P_ifyi_15_4 + i5:u74:P_awaity_4 + i5:u64:P_wait_4_5 + i5:u64:P_done_4_5 = 1
invariant :i5:u36:P_wait_4_2 + i5:u36:P_done_4_2 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i5:u35:P_wait_4_1 + i5:u35:P_done_4_1 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i2:u46:P_wait_6_6 + i2:u46:P_done_6_6 + -1'i2:u70:P_wait_6_4 + -1'i2:u70:P_done_6_4 = 0
invariant :i4:u24:P_wait_1_3 + i4:u24:P_done_1_3 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i1:u57:P_wait_2_3 + i1:u57:P_done_2_3 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i0:u81:P_CS_21_1 + i0:u81:P_setbi_24_1 + i4:u2:P_start_1_1 + i4:u2:P_fordo_12_1 + i4:u13:P_setx_3_1 + i4:u13:P_setbi_5_1 + i4:u13:P_ify0_4_1 + i4:u15:P_sety_9_1 + i4:u15:P_ifxi_10_1 + i4:u15:P_setbi_11_1 + i4:u72:P_ifyi_15_1 + i4:u72:P_awaity_1 + i4:u55:P_wait_1_4 + i4:u55:P_done_1_4 = 1
invariant :i0:u0:y_0 + i0:u0:y_1 + i0:u0:y_2 + i0:u0:y_3 + i0:u0:y_4 + i0:u0:y_5 + i0:u0:y_6 = 1
invariant :i4:u52:P_await_13_1 + -1'i4:u55:P_wait_1_4 + -1'i4:u55:P_done_1_4 = 0
invariant :i5:u63:P_wait_4_4 + i5:u63:P_done_4_4 + -1'i5:u64:P_wait_4_5 + -1'i5:u64:P_done_4_5 = 0
invariant :i7:u59:P_wait_3_0 + i7:u59:P_done_3_0 = 0
invariant :i3:u22:P_await_13_0 + -1'i3:u51:P_wait_0_6 + -1'i3:u51:P_done_0_6 = 0
invariant :i0:u82:P_CS_21_2 + i0:u82:P_setbi_24_2 + i1:u3:P_start_1_2 + i1:u3:P_fordo_12_2 + i1:u8:P_setx_3_2 + i1:u8:P_setbi_5_2 + i1:u8:P_ify0_4_2 + i1:u20:P_sety_9_2 + i1:u20:P_ifxi_10_2 + i1:u20:P_setbi_11_2 + i1:u73:P_ifyi_15_2 + i1:u73:P_awaity_2 + i1:u58:P_wait_2_4 + i1:u58:P_done_2_4 = 1
invariant :i1:u30:P_wait_2_6 + i1:u30:P_done_2_6 + -1'i1:u58:P_wait_2_4 + -1'i1:u58:P_done_2_4 = 0
invariant :i0:u84:P_CS_21_5 + i0:u84:P_setbi_24_5 + i6:u6:P_start_1_5 + i6:u6:P_fordo_12_5 + i6:u11:P_setx_3_5 + i6:u11:P_setbi_5_5 + i6:u11:P_ify0_4_5 + i6:u17:P_sety_9_5 + i6:u17:P_ifxi_10_5 + i6:u17:P_setbi_11_5 + i6:u75:P_ifyi_15_5 + i6:u75:P_awaity_5 + i6:u68:P_wait_5_6 + i6:u68:P_done_5_6 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6670 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 111 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP0==true))U(X(X(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 382 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](<>(X([]((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP1==true))U((LTLAP4==true)))U((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 72 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](<>(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56375 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 328 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 262 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP8==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 255 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP9==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 259 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(X((LTLAP10==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 83 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (([]((LTLAP11==true)))U([]((LTLAP12==true))))U(<>((LTLAP13==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 410 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 324 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 267 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X(<>((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 87 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 294 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP18==true)))U(<>((LTLAP19==true))))U(((LTLAP20==true))U((LTLAP21==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 252 ms.
FORMULA LamportFastMutEx-PT-6-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions T_setx_3_8, T_setx_3_10, T_setx_3_11, T_setx_3_12, T_setx_3_13, T_setx_3_14, T_setx_3_15, T_setx_3_16, T_setx_3_18, T_setx_3_19, T_setx_3_20, T_setx_3_21, T_setx_3_22, T_setx_3_23, T_setx_3_24, T_setx_3_26, T_setx_3_27, T_setx_3_28, T_setx_3_29, T_setx_3_30, T_setx_3_31, T_setx_3_32, T_setx_3_34, T_setx_3_35, T_setx_3_36, T_setx_3_37, T_setx_3_38, T_setx_3_39, T_setx_3_40, T_setx_3_42, T_setx_3_43, T_setx_3_44, T_setx_3_45, T_setx_3_46, T_setx_3_47, T_setx_3_48, T_setbi_5_4, T_setbi_5_6, T_setbi_5_8, T_setbi_5_10, T_setbi_5_12, T_setbi_5_14, T_awaity_2, T_awaity_3, T_awaity_4, T_awaity_5, T_awaity_6, T_awaity_7, T_sety_9_8, T_sety_9_10, T_sety_9_11, T_sety_9_12, T_sety_9_13, T_sety_9_14, T_sety_9_15, T_sety_9_16, T_sety_9_18, T_sety_9_19, T_sety_9_20, T_sety_9_21, T_sety_9_22, T_sety_9_23, T_sety_9_24, T_sety_9_26, T_sety_9_27, T_sety_9_28, T_sety_9_29, T_sety_9_30, T_sety_9_31, T_sety_9_32, T_sety_9_34, T_sety_9_35, T_sety_9_36, T_sety_9_37, T_sety_9_38, T_sety_9_39, T_sety_9_40, T_sety_9_42, T_sety_9_43, T_sety_9_44, T_sety_9_45, T_sety_9_46, T_sety_9_47, T_sety_9_48, T_setbi_11_4, T_setbi_11_6, T_setbi_11_8, T_setbi_11_10, T_setbi_11_12, T_setbi_11_14, T_ynei_15_8, T_ynei_15_10, T_ynei_15_11, T_ynei_15_12, T_ynei_15_13, T_ynei_15_14, T_ynei_15_15, T_ynei_15_16, T_ynei_15_18, T_ynei_15_19, T_ynei_15_20, T_ynei_15_21, T_ynei_15_22, T_ynei_15_23, T_ynei_15_24, T_ynei_15_26, T_ynei_15_27, T_ynei_15_28, T_ynei_15_29, T_ynei_15_30, T_ynei_15_31, T_ynei_15_32, T_ynei_15_34, T_ynei_15_35, T_ynei_15_36, T_ynei_15_37, T_ynei_15_38, T_ynei_15_39, T_ynei_15_40, T_ynei_15_42, T_ynei_15_43, T_ynei_15_44, T_ynei_15_45, T_ynei_15_46, T_ynei_15_47, T_ynei_15_48, T_yeqi_15_9, T_yeqi_15_17, T_yeqi_15_25, T_yeqi_15_33, T_yeqi_15_41, T_yeqi_15_49, T_sety0_23_9, T_sety0_23_10, T_sety0_23_11, T_sety0_23_12, T_sety0_23_13, T_sety0_23_14, T_sety0_23_16, T_sety0_23_17, T_sety0_23_18, T_sety0_23_19, T_sety0_23_20, T_sety0_23_21, T_sety0_23_23, T_sety0_23_24, T_sety0_23_25, T_sety0_23_26, T_sety0_23_27, T_sety0_23_28, T_sety0_23_30, T_sety0_23_31, T_sety0_23_32, T_sety0_23_33, T_sety0_23_34, T_sety0_23_35, T_sety0_23_37, T_sety0_23_38, T_sety0_23_39, T_sety0_23_40, T_sety0_23_41, T_sety0_23_42, T_sety0_23_44, T_sety0_23_45, T_sety0_23_46, T_sety0_23_47, T_sety0_23_48, T_sety0_23_49, T_setbi_24_3, T_setbi_24_4, T_setbi_24_5, T_setbi_24_6, T_setbi_24_7, T_setbi_24_8, T_setbi_24_9, T_setbi_24_10, T_setbi_24_11, T_setbi_24_12, T_setbi_24_13, T_setbi_24_14, i1.u8.T_setx_3_17, i2.u14.T_setx_3_49, i4.u13.T_setx_3_9, i5.u10.T_setx_3_33, i6.u11.T_setx_3_41, i7.u9.T_setx_3_25, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :108/126/186/420
WARNING : LTSmin timed out (>1800 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 9:30:07 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 28, 2018 9:30:07 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 9:30:07 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 113 ms
May 28, 2018 9:30:07 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 217 places.
May 28, 2018 9:30:08 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 420 transitions.
May 28, 2018 9:30:08 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 34 ms
May 28, 2018 9:30:08 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 105 ms
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 74 ms
Begin: Mon May 28 09:30:08 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Mon May 28 09:30:08 2018
network size: 217 nodes, 1578 links, 840 weight
quality increased from -0.0105649 to 0.377219
end computation: Mon May 28 09:30:08 2018
level 1:
start computation: Mon May 28 09:30:08 2018
network size: 85 nodes, 771 links, 840 weight
quality increased from 0.377219 to 0.488893
end computation: Mon May 28 09:30:08 2018
level 2:
start computation: Mon May 28 09:30:08 2018
network size: 15 nodes, 169 links, 840 weight
quality increased from 0.488893 to 0.504608
end computation: Mon May 28 09:30:08 2018
level 3:
start computation: Mon May 28 09:30:08 2018
network size: 8 nodes, 64 links, 840 weight
quality increased from 0.504608 to 0.504608
end computation: Mon May 28 09:30:08 2018
End: Mon May 28 09:30:08 2018
Total duration: 0 sec
0.504608
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 49 ms
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 28, 2018 9:30:08 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 581 redundant transitions.
May 28, 2018 9:30:09 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 14 ms
May 28, 2018 9:30:09 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 7 ms
May 28, 2018 9:30:09 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 420 transitions.
May 28, 2018 9:30:09 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 65 place invariants in 76 ms
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 217 variables to be positive in 628 ms
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 420 transitions.
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/420 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 45 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 420 transitions.
May 28, 2018 9:30:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 15 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 9:30:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 420 transitions.
May 28, 2018 9:30:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/420) took 20 ms. Total solver calls (SAT/UNSAT): 60(0/60)
May 28, 2018 9:30:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/420) took 3613 ms. Total solver calls (SAT/UNSAT): 2387(109/2278)
May 28, 2018 9:30:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/420) took 7116 ms. Total solver calls (SAT/UNSAT): 3458(201/3257)
May 28, 2018 9:30:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/420) took 12212 ms. Total solver calls (SAT/UNSAT): 4342(272/4070)
May 28, 2018 9:30:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/420) took 15576 ms. Total solver calls (SAT/UNSAT): 4657(296/4361)
May 28, 2018 9:30:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/420) took 18844 ms. Total solver calls (SAT/UNSAT): 5642(369/5273)
May 28, 2018 9:30:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(60/420) took 23064 ms. Total solver calls (SAT/UNSAT): 6727(369/6358)
May 28, 2018 9:30:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/420) took 26315 ms. Total solver calls (SAT/UNSAT): 7577(438/7139)
May 28, 2018 9:30:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/420) took 31200 ms. Total solver calls (SAT/UNSAT): 7787(461/7326)
May 28, 2018 9:30:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/420) took 35423 ms. Total solver calls (SAT/UNSAT): 8204(507/7697)
May 28, 2018 9:30:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(74/420) took 38465 ms. Total solver calls (SAT/UNSAT): 9632(660/8972)
May 28, 2018 9:30:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/420) took 41518 ms. Total solver calls (SAT/UNSAT): 11204(825/10379)
May 28, 2018 9:31:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/420) took 44526 ms. Total solver calls (SAT/UNSAT): 15988(1308/14680)
May 28, 2018 9:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(132/420) took 47670 ms. Total solver calls (SAT/UNSAT): 18081(1431/16650)
May 28, 2018 9:31:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(135/420) took 52183 ms. Total solver calls (SAT/UNSAT): 18540(1482/17058)
May 28, 2018 9:31:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(143/420) took 58178 ms. Total solver calls (SAT/UNSAT): 19720(1614/18106)
May 28, 2018 9:31:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(148/420) took 61198 ms. Total solver calls (SAT/UNSAT): 20425(1692/18733)
May 28, 2018 9:31:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(154/420) took 65368 ms. Total solver calls (SAT/UNSAT): 21238(1781/19457)
May 28, 2018 9:31:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(157/420) took 68481 ms. Total solver calls (SAT/UNSAT): 21631(1823/19808)
May 28, 2018 9:31:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(165/420) took 73027 ms. Total solver calls (SAT/UNSAT): 22635(1930/20705)
May 28, 2018 9:31:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(175/420) took 76987 ms. Total solver calls (SAT/UNSAT): 23764(2040/21724)
May 28, 2018 9:31:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(184/420) took 80249 ms. Total solver calls (SAT/UNSAT): 24403(2065/22338)
May 28, 2018 9:31:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(186/420) took 83963 ms. Total solver calls (SAT/UNSAT): 24534(2077/22457)
May 28, 2018 9:31:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(190/420) took 88101 ms. Total solver calls (SAT/UNSAT): 24784(2099/22685)
May 28, 2018 9:31:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(196/420) took 91258 ms. Total solver calls (SAT/UNSAT): 25129(2128/23001)
May 28, 2018 9:31:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(198/420) took 94544 ms. Total solver calls (SAT/UNSAT): 25236(2136/23100)
May 28, 2018 9:31:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(202/420) took 98202 ms. Total solver calls (SAT/UNSAT): 25438(2152/23286)
May 28, 2018 9:31:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(210/420) took 102263 ms. Total solver calls (SAT/UNSAT): 25794(2175/23619)
May 28, 2018 9:32:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(214/420) took 106124 ms. Total solver calls (SAT/UNSAT): 25948(2183/23765)
May 28, 2018 9:32:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(225/420) took 109131 ms. Total solver calls (SAT/UNSAT): 26276(2215/24061)
May 28, 2018 9:32:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(238/420) took 112176 ms. Total solver calls (SAT/UNSAT): 26573(2229/24344)
May 28, 2018 9:32:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(249/420) took 115546 ms. Total solver calls (SAT/UNSAT): 26738(2325/24413)
May 28, 2018 9:32:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(265/420) took 118676 ms. Total solver calls (SAT/UNSAT): 26924(2434/24490)
May 28, 2018 9:32:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(284/420) took 122220 ms. Total solver calls (SAT/UNSAT): 27118(2525/24593)
May 28, 2018 9:32:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(300/420) took 125948 ms. Total solver calls (SAT/UNSAT): 27937(2542/25395)
May 28, 2018 9:32:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(311/420) took 129033 ms. Total solver calls (SAT/UNSAT): 28916(2659/26257)
May 28, 2018 9:32:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(315/420) took 132211 ms. Total solver calls (SAT/UNSAT): 29242(2698/26544)
May 28, 2018 9:32:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(319/420) took 135275 ms. Total solver calls (SAT/UNSAT): 29552(2734/26818)
May 28, 2018 9:32:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(326/420) took 138524 ms. Total solver calls (SAT/UNSAT): 30056(2792/27264)
May 28, 2018 9:32:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(328/420) took 142100 ms. Total solver calls (SAT/UNSAT): 30191(2808/27383)
May 28, 2018 9:32:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(337/420) took 145756 ms. Total solver calls (SAT/UNSAT): 30749(2863/27886)
May 28, 2018 9:32:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(347/420) took 148758 ms. Total solver calls (SAT/UNSAT): 31124(2893/28231)
May 28, 2018 9:32:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(357/420) took 153024 ms. Total solver calls (SAT/UNSAT): 31537(2898/28639)
May 28, 2018 9:32:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(365/420) took 156117 ms. Total solver calls (SAT/UNSAT): 31853(2936/28917)
May 28, 2018 9:32:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(369/420) took 159972 ms. Total solver calls (SAT/UNSAT): 31987(2952/29035)
May 28, 2018 9:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(374/420) took 163668 ms. Total solver calls (SAT/UNSAT): 32132(2968/29164)
May 28, 2018 9:33:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(383/420) took 166850 ms. Total solver calls (SAT/UNSAT): 32330(2989/29341)
May 28, 2018 9:33:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(397/420) took 169895 ms. Total solver calls (SAT/UNSAT): 32477(2998/29479)
May 28, 2018 9:33:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 170752 ms. Total solver calls (SAT/UNSAT): 32522(2998/29524)
May 28, 2018 9:33:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 420 transitions.
May 28, 2018 9:33:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 133 ms. Total solver calls (SAT/UNSAT): 42(0/42)
May 28, 2018 9:33:06 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 177833ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-6"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-6.tgz
mv LamportFastMutEx-PT-6 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is LamportFastMutEx-PT-6, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r261-csrt-152732585800040"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;