About the Execution of ITS-Tools for Peterson-PT-4
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15755.220 | 2413856.00 | 3360434.00 | 386.00 | FFTTFFFF?TFTFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 40K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 114K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 82K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 20K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 53K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 37K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 29K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 12K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 25K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 511K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is Peterson-PT-4, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585400163
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-PT-4-LTLCardinality-00
FORMULA_NAME Peterson-PT-4-LTLCardinality-01
FORMULA_NAME Peterson-PT-4-LTLCardinality-02
FORMULA_NAME Peterson-PT-4-LTLCardinality-03
FORMULA_NAME Peterson-PT-4-LTLCardinality-04
FORMULA_NAME Peterson-PT-4-LTLCardinality-05
FORMULA_NAME Peterson-PT-4-LTLCardinality-06
FORMULA_NAME Peterson-PT-4-LTLCardinality-07
FORMULA_NAME Peterson-PT-4-LTLCardinality-08
FORMULA_NAME Peterson-PT-4-LTLCardinality-09
FORMULA_NAME Peterson-PT-4-LTLCardinality-10
FORMULA_NAME Peterson-PT-4-LTLCardinality-11
FORMULA_NAME Peterson-PT-4-LTLCardinality-12
FORMULA_NAME Peterson-PT-4-LTLCardinality-13
FORMULA_NAME Peterson-PT-4-LTLCardinality-14
FORMULA_NAME Peterson-PT-4-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1527489586640
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(((G("(((((Idle_4+Idle_3)+Idle_2)+Idle_1)+Idle_0)<=(((((((((((((((((((Turn_3_1+Turn_0_2)+Turn_1_2)+Turn_2_2)+Turn_3_2)+Turn_0_3)+Turn_1_3)+Turn_2_3)+Turn_0_0)+Turn_1_0)+Turn_2_0)+Turn_3_0)+Turn_0_1)+Turn_1_1)+Turn_2_1)+Turn_3_4)+Turn_2_4)+Turn_1_4)+Turn_0_4)+Turn_3_3))"))U(G(F("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((IsEndLoop_0_0_0+IsEndLoop_1_0_0)+IsEndLoop_2_0_0)+IsEndLoop_3_0_0)+IsEndLoop_4_0_0)+IsEndLoop_0_1_0)+IsEndLoop_1_1_0)+IsEndLoop_2_1_0)+IsEndLoop_3_1_0)+IsEndLoop_4_1_0)+IsEndLoop_0_2_0)+IsEndLoop_1_2_0)+IsEndLoop_2_2_0)+IsEndLoop_4_2_0)+IsEndLoop_3_2_0)+IsEndLoop_1_3_0)+IsEndLoop_0_3_0)+IsEndLoop_3_3_0)+IsEndLoop_2_3_0)+IsEndLoop_0_0_1)+IsEndLoop_4_3_0)+IsEndLoop_2_0_1)+IsEndLoop_1_0_1)+IsEndLoop_4_0_1)+IsEndLoop_3_0_1)+IsEndLoop_1_1_1)+IsEndLoop_0_1_1)+IsEndLoop_3_1_1)+IsEndLoop_2_1_1)+IsEndLoop_1_2_1)+IsEndLoop_2_2_1)+IsEndLoop_4_1_1)+IsEndLoop_0_2_1)+IsEndLoop_0_3_1)+IsEndLoop_1_3_1)+IsEndLoop_3_2_1)+IsEndLoop_4_2_1)+IsEndLoop_4_3_1)+IsEndLoop_0_0_2)+IsEndLoop_2_3_1)+IsEndLoop_3_3_1)+IsEndLoop_3_0_2)+IsEndLoop_4_0_2)+IsEndLoop_1_0_2)+IsEndLoop_2_0_2)+IsEndLoop_3_1_2)+IsEndLoop_2_1_2)+IsEndLoop_1_1_2)+IsEndLoop_0_1_2)+IsEndLoop_2_2_2)+IsEndLoop_1_2_2)+IsEndLoop_0_2_2)+IsEndLoop_4_1_2)+IsEndLoop_1_3_2)+IsEndLoop_0_3_2)+IsEndLoop_4_2_2)+IsEndLoop_3_2_2)+IsEndLoop_0_0_3)+IsEndLoop_4_3_2)+IsEndLoop_3_3_2)+IsEndLoop_2_3_2)+IsEndLoop_0_1_3)+IsEndLoop_1_1_3)+IsEndLoop_2_1_3)+IsEndLoop_3_1_3)+IsEndLoop_1_0_3)+IsEndLoop_2_0_3)+IsEndLoop_3_0_3)+IsEndLoop_4_0_3)+IsEndLoop_3_2_3)+IsEndLoop_4_2_3)+IsEndLoop_0_3_3)+IsEndLoop_1_3_3)+IsEndLoop_4_1_3)+IsEndLoop_0_2_3)+IsEndLoop_1_2_3)+IsEndLoop_2_2_3)+IsEndLoop_2_0_4)+IsEndLoop_1_0_4)+IsEndLoop_4_0_4)+IsEndLoop_3_0_4)+IsEndLoop_3_3_3)+IsEndLoop_2_3_3)+IsEndLoop_0_0_4)+IsEndLoop_4_3_3)+IsEndLoop_0_2_4)+IsEndLoop_4_1_4)+IsEndLoop_2_2_4)+IsEndLoop_1_2_4)+IsEndLoop_1_1_4)+IsEndLoop_0_1_4)+IsEndLoop_3_1_4)+IsEndLoop_2_1_4)+IsEndLoop_4_3_4)+IsEndLoop_2_3_4)+IsEndLoop_3_3_4)+IsEndLoop_0_3_4)+IsEndLoop_1_3_4)+IsEndLoop_3_2_4)+IsEndLoop_4_2_4)>=3)")))))
Formula 0 simplified : !(G"(((((Idle_4+Idle_3)+Idle_2)+Idle_1)+Idle_0)<=(((((((((((((((((((Turn_3_1+Turn_0_2)+Turn_1_2)+Turn_2_2)+Turn_3_2)+Turn_0_3)+Turn_1_3)+Turn_2_3)+Turn_0_0)+Turn_1_0)+Turn_2_0)+Turn_3_0)+Turn_0_1)+Turn_1_1)+Turn_2_1)+Turn_3_4)+Turn_2_4)+Turn_1_4)+Turn_0_4)+Turn_3_3))" U GF"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((IsEndLoop_0_0_0+IsEndLoop_1_0_0)+IsEndLoop_2_0_0)+IsEndLoop_3_0_0)+IsEndLoop_4_0_0)+IsEndLoop_0_1_0)+IsEndLoop_1_1_0)+IsEndLoop_2_1_0)+IsEndLoop_3_1_0)+IsEndLoop_4_1_0)+IsEndLoop_0_2_0)+IsEndLoop_1_2_0)+IsEndLoop_2_2_0)+IsEndLoop_4_2_0)+IsEndLoop_3_2_0)+IsEndLoop_1_3_0)+IsEndLoop_0_3_0)+IsEndLoop_3_3_0)+IsEndLoop_2_3_0)+IsEndLoop_0_0_1)+IsEndLoop_4_3_0)+IsEndLoop_2_0_1)+IsEndLoop_1_0_1)+IsEndLoop_4_0_1)+IsEndLoop_3_0_1)+IsEndLoop_1_1_1)+IsEndLoop_0_1_1)+IsEndLoop_3_1_1)+IsEndLoop_2_1_1)+IsEndLoop_1_2_1)+IsEndLoop_2_2_1)+IsEndLoop_4_1_1)+IsEndLoop_0_2_1)+IsEndLoop_0_3_1)+IsEndLoop_1_3_1)+IsEndLoop_3_2_1)+IsEndLoop_4_2_1)+IsEndLoop_4_3_1)+IsEndLoop_0_0_2)+IsEndLoop_2_3_1)+IsEndLoop_3_3_1)+IsEndLoop_3_0_2)+IsEndLoop_4_0_2)+IsEndLoop_1_0_2)+IsEndLoop_2_0_2)+IsEndLoop_3_1_2)+IsEndLoop_2_1_2)+IsEndLoop_1_1_2)+IsEndLoop_0_1_2)+IsEndLoop_2_2_2)+IsEndLoop_1_2_2)+IsEndLoop_0_2_2)+IsEndLoop_4_1_2)+IsEndLoop_1_3_2)+IsEndLoop_0_3_2)+IsEndLoop_4_2_2)+IsEndLoop_3_2_2)+IsEndLoop_0_0_3)+IsEndLoop_4_3_2)+IsEndLoop_3_3_2)+IsEndLoop_2_3_2)+IsEndLoop_0_1_3)+IsEndLoop_1_1_3)+IsEndLoop_2_1_3)+IsEndLoop_3_1_3)+IsEndLoop_1_0_3)+IsEndLoop_2_0_3)+IsEndLoop_3_0_3)+IsEndLoop_4_0_3)+IsEndLoop_3_2_3)+IsEndLoop_4_2_3)+IsEndLoop_0_3_3)+IsEndLoop_1_3_3)+IsEndLoop_4_1_3)+IsEndLoop_0_2_3)+IsEndLoop_1_2_3)+IsEndLoop_2_2_3)+IsEndLoop_2_0_4)+IsEndLoop_1_0_4)+IsEndLoop_4_0_4)+IsEndLoop_3_0_4)+IsEndLoop_3_3_3)+IsEndLoop_2_3_3)+IsEndLoop_0_0_4)+IsEndLoop_4_3_3)+IsEndLoop_0_2_4)+IsEndLoop_4_1_4)+IsEndLoop_2_2_4)+IsEndLoop_1_2_4)+IsEndLoop_1_1_4)+IsEndLoop_0_1_4)+IsEndLoop_3_1_4)+IsEndLoop_2_1_4)+IsEndLoop_4_3_4)+IsEndLoop_2_3_4)+IsEndLoop_3_3_4)+IsEndLoop_0_3_4)+IsEndLoop_1_3_4)+IsEndLoop_3_2_4)+IsEndLoop_4_2_4)>=3)")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 630
// Phase 1: matrix 630 rows 480 cols
invariant :IsEndLoop_0_0_0 + IsEndLoop_0_1_0 + IsEndLoop_0_2_0 + IsEndLoop_0_3_0 + IsEndLoop_0_0_1 + IsEndLoop_0_1_1 + IsEndLoop_0_2_1 + IsEndLoop_0_3_1 + IsEndLoop_0_0_2 + IsEndLoop_0_1_2 + IsEndLoop_0_2_2 + IsEndLoop_0_3_2 + IsEndLoop_0_0_3 + IsEndLoop_0_1_3 + IsEndLoop_0_3_3 + IsEndLoop_0_2_3 + IsEndLoop_0_0_4 + IsEndLoop_0_2_4 + IsEndLoop_0_1_4 + EndTurn_0_0 + IsEndLoop_0_3_4 + EndTurn_0_1 + EndTurn_0_3 + EndTurn_0_2 + BeginLoop_0_0_0 + BeginLoop_0_3_0 + BeginLoop_0_0_1 + BeginLoop_0_1_0 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_3_1 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_2_2 + BeginLoop_0_0_2 + BeginLoop_0_1_3 + BeginLoop_0_3_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_3_3 + BeginLoop_0_2_3 + BeginLoop_0_3_4 + BeginLoop_0_2_4 + BeginLoop_0_1_4 + TestAlone_0_1_1 + TestAlone_0_0_1 + TestAlone_0_2_2 + TestAlone_0_3_2 + TestAlone_0_0_3 + TestAlone_0_1_3 + TestAlone_0_2_1 + TestAlone_0_3_1 + TestAlone_0_0_2 + TestAlone_0_1_2 + TestAlone_0_2_4 + TestAlone_0_3_4 + TestTurn_0_0 + TestTurn_0_1 + TestAlone_0_2_3 + TestAlone_0_3_3 + TestAlone_0_0_4 + TestAlone_0_1_4 + TestIdentity_0_2_0 + TestIdentity_0_1_0 + TestIdentity_0_3_0 + TestTurn_0_2 + TestIdentity_0_0_0 + TestTurn_0_3 + TestIdentity_0_0_2 + TestIdentity_0_3_1 + TestIdentity_0_2_2 + TestIdentity_0_1_2 + TestIdentity_0_1_1 + TestIdentity_0_0_1 + TestIdentity_0_2_1 + TestIdentity_0_3_3 + TestIdentity_0_0_4 + TestIdentity_0_2_3 + TestIdentity_0_0_3 + TestIdentity_0_1_3 + TestIdentity_0_3_2 + TestIdentity_0_3_4 + TestIdentity_0_1_4 + TestIdentity_0_2_4 + CS_0 + AskForSection_0_3 + AskForSection_0_2 + AskForSection_0_1 + AskForSection_0_0 + Idle_0 = 1
invariant :IsEndLoop_1_0_0 + IsEndLoop_1_1_0 + IsEndLoop_1_2_0 + IsEndLoop_1_3_0 + IsEndLoop_1_0_1 + IsEndLoop_1_1_1 + IsEndLoop_1_2_1 + IsEndLoop_1_3_1 + IsEndLoop_1_0_2 + IsEndLoop_1_1_2 + IsEndLoop_1_2_2 + IsEndLoop_1_3_2 + IsEndLoop_1_1_3 + IsEndLoop_1_0_3 + IsEndLoop_1_3_3 + IsEndLoop_1_2_3 + IsEndLoop_1_0_4 + IsEndLoop_1_2_4 + IsEndLoop_1_1_4 + IsEndLoop_1_3_4 + EndTurn_1_1 + EndTurn_1_0 + EndTurn_1_3 + EndTurn_1_2 + BeginLoop_1_0_0 + BeginLoop_1_3_0 + BeginLoop_1_1_0 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_3_1 + BeginLoop_1_0_1 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_2_2 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_1_3 + BeginLoop_1_3_2 + BeginLoop_1_0_4 + BeginLoop_1_3_3 + BeginLoop_1_2_3 + BeginLoop_1_3_4 + BeginLoop_1_2_4 + BeginLoop_1_1_4 + TestAlone_1_1_0 + TestAlone_1_0_0 + TestAlone_1_3_0 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_3_2 + TestAlone_1_0_3 + TestAlone_1_1_3 + TestAlone_1_0_2 + TestAlone_1_1_2 + TestAlone_1_2_4 + TestAlone_1_3_4 + TestTurn_1_0 + TestTurn_1_1 + TestAlone_1_2_3 + TestAlone_1_3_3 + TestAlone_1_0_4 + TestAlone_1_1_4 + TestIdentity_1_1_0 + TestIdentity_1_3_0 + TestIdentity_1_2_0 + TestTurn_1_2 + TestIdentity_1_0_0 + TestTurn_1_3 + TestIdentity_1_0_2 + TestIdentity_1_3_1 + TestIdentity_1_1_2 + TestIdentity_1_1_1 + TestIdentity_1_0_1 + TestIdentity_1_2_1 + TestIdentity_1_3_3 + TestIdentity_1_0_4 + TestIdentity_1_2_3 + TestIdentity_1_0_3 + TestIdentity_1_1_3 + TestIdentity_1_2_2 + TestIdentity_1_3_2 + TestIdentity_1_2_4 + TestIdentity_1_3_4 + TestIdentity_1_1_4 + CS_1 + AskForSection_1_3 + AskForSection_1_2 + AskForSection_1_1 + AskForSection_1_0 + Idle_1 = 1
invariant :WantSection_1_F + -1'Idle_1 = 0
invariant :Turn_0_2 + Turn_0_3 + Turn_0_0 + Turn_0_1 + Turn_0_4 = 1
invariant :WantSection_3_F + -1'Idle_3 = 0
invariant :Turn_1_2 + Turn_1_3 + Turn_1_0 + Turn_1_1 + Turn_1_4 = 1
invariant :WantSection_4_F + -1'Idle_4 = 0
invariant :WantSection_3_T + Idle_3 = 1
invariant :WantSection_0_F + -1'Idle_0 = 0
invariant :IsEndLoop_4_0_0 + IsEndLoop_4_1_0 + IsEndLoop_4_2_0 + IsEndLoop_4_3_0 + IsEndLoop_4_0_1 + IsEndLoop_4_1_1 + IsEndLoop_4_2_1 + IsEndLoop_4_3_1 + IsEndLoop_4_0_2 + IsEndLoop_4_1_2 + IsEndLoop_4_2_2 + IsEndLoop_4_3_2 + IsEndLoop_4_0_3 + IsEndLoop_4_2_3 + IsEndLoop_4_1_3 + IsEndLoop_4_0_4 + IsEndLoop_4_3_3 + IsEndLoop_4_1_4 + IsEndLoop_4_3_4 + IsEndLoop_4_2_4 + EndTurn_4_0 + EndTurn_4_2 + EndTurn_4_1 + BeginLoop_4_0_0 + EndTurn_4_3 + BeginLoop_4_2_0 + BeginLoop_4_3_0 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_2_1 + BeginLoop_4_0_1 + BeginLoop_4_1_2 + BeginLoop_4_3_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_2_2 + BeginLoop_4_3_2 + BeginLoop_4_0_4 + BeginLoop_4_3_3 + BeginLoop_4_2_3 + BeginLoop_4_1_3 + BeginLoop_4_3_4 + BeginLoop_4_2_4 + BeginLoop_4_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_3_0 + TestAlone_4_2_0 + TestAlone_4_1_0 + TestAlone_4_1_2 + TestAlone_4_2_2 + TestAlone_4_3_2 + TestAlone_4_0_3 + TestAlone_4_1_1 + TestAlone_4_2_1 + TestAlone_4_3_1 + TestAlone_4_0_2 + TestTurn_4_0 + TestAlone_4_1_3 + TestAlone_4_2_3 + TestAlone_4_3_3 + TestIdentity_4_1_0 + TestIdentity_4_0_0 + TestIdentity_4_2_0 + TestTurn_4_2 + TestTurn_4_1 + TestTurn_4_3 + TestIdentity_4_3_1 + TestIdentity_4_1_2 + TestIdentity_4_0_2 + TestIdentity_4_0_1 + TestIdentity_4_3_0 + TestIdentity_4_2_1 + TestIdentity_4_1_1 + TestIdentity_4_3_3 + TestIdentity_4_1_3 + TestIdentity_4_2_3 + TestIdentity_4_3_2 + TestIdentity_4_0_3 + TestIdentity_4_2_2 + TestIdentity_4_3_4 + TestIdentity_4_2_4 + TestIdentity_4_0_4 + TestIdentity_4_1_4 + AskForSection_4_3 + AskForSection_4_2 + AskForSection_4_1 + AskForSection_4_0 + Idle_4 + CS_4 = 1
invariant :WantSection_4_T + Idle_4 = 1
invariant :WantSection_2_T + Idle_2 = 1
invariant :IsEndLoop_3_0_0 + IsEndLoop_3_1_0 + IsEndLoop_3_2_0 + IsEndLoop_3_3_0 + IsEndLoop_3_0_1 + IsEndLoop_3_1_1 + IsEndLoop_3_2_1 + IsEndLoop_3_3_1 + IsEndLoop_3_0_2 + IsEndLoop_3_1_2 + IsEndLoop_3_2_2 + IsEndLoop_3_3_2 + IsEndLoop_3_1_3 + IsEndLoop_3_0_3 + IsEndLoop_3_2_3 + IsEndLoop_3_0_4 + IsEndLoop_3_3_3 + IsEndLoop_3_1_4 + IsEndLoop_3_3_4 + IsEndLoop_3_2_4 + EndTurn_3_1 + EndTurn_3_0 + EndTurn_3_2 + BeginLoop_3_0_0 + EndTurn_3_3 + BeginLoop_3_2_0 + BeginLoop_3_3_0 + BeginLoop_3_1_0 + BeginLoop_3_2_1 + BeginLoop_3_0_1 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_3_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_1_3 + BeginLoop_3_2_2 + BeginLoop_3_3_2 + BeginLoop_3_0_4 + BeginLoop_3_3_3 + BeginLoop_3_2_3 + BeginLoop_3_3_4 + BeginLoop_3_2_4 + BeginLoop_3_1_4 + TestAlone_3_1_0 + TestAlone_3_0_0 + TestAlone_3_1_1 + TestAlone_3_0_1 + TestAlone_3_3_0 + TestAlone_3_2_0 + TestAlone_3_2_2 + TestAlone_3_3_2 + TestAlone_3_2_1 + TestAlone_3_3_1 + TestAlone_3_0_2 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_3_2_4 + TestAlone_3_3_4 + TestTurn_3_0 + TestAlone_3_0_4 + TestIdentity_3_1_0 + TestIdentity_3_0_0 + TestIdentity_3_3_0 + TestIdentity_3_2_0 + TestTurn_3_2 + TestTurn_3_1 + TestTurn_3_3 + TestIdentity_3_3_1 + TestIdentity_3_1_2 + TestIdentity_3_0_2 + TestIdentity_3_0_1 + TestIdentity_3_2_1 + TestIdentity_3_1_1 + TestIdentity_3_3_3 + TestIdentity_3_1_3 + TestIdentity_3_2_3 + TestIdentity_3_0_3 + TestIdentity_3_2_2 + TestIdentity_3_3_2 + TestIdentity_3_2_4 + TestIdentity_3_3_4 + TestIdentity_3_0_4 + TestIdentity_3_1_4 + AskForSection_3_3 + AskForSection_3_2 + AskForSection_3_1 + AskForSection_3_0 + Idle_3 + CS_3 = 1
invariant :WantSection_0_T + Idle_0 = 1
invariant :WantSection_1_T + Idle_1 = 1
invariant :Turn_2_2 + Turn_2_3 + Turn_2_0 + Turn_2_1 + Turn_2_4 = 1
invariant :IsEndLoop_2_0_0 + IsEndLoop_2_1_0 + IsEndLoop_2_2_0 + IsEndLoop_2_3_0 + IsEndLoop_2_0_1 + IsEndLoop_2_1_1 + IsEndLoop_2_2_1 + IsEndLoop_2_3_1 + IsEndLoop_2_0_2 + IsEndLoop_2_1_2 + IsEndLoop_2_2_2 + IsEndLoop_2_3_2 + IsEndLoop_2_1_3 + IsEndLoop_2_0_3 + IsEndLoop_2_2_3 + IsEndLoop_2_0_4 + IsEndLoop_2_3_3 + IsEndLoop_2_2_4 + IsEndLoop_2_1_4 + IsEndLoop_2_3_4 + EndTurn_2_1 + EndTurn_2_0 + EndTurn_2_2 + BeginLoop_2_0_0 + EndTurn_2_3 + BeginLoop_2_3_0 + BeginLoop_2_1_0 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_0_1 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_2_2 + BeginLoop_2_3_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_1_3 + BeginLoop_2_3_2 + BeginLoop_2_0_4 + BeginLoop_2_3_3 + BeginLoop_2_2_3 + BeginLoop_2_3_4 + BeginLoop_2_2_4 + BeginLoop_2_1_4 + TestAlone_2_1_0 + TestAlone_2_0_0 + TestAlone_2_1_1 + TestAlone_2_0_1 + TestAlone_2_3_0 + TestAlone_2_2_0 + TestAlone_2_0_3 + TestAlone_2_1_3 + TestAlone_2_2_1 + TestAlone_2_3_1 + TestAlone_2_2_4 + TestAlone_2_3_4 + TestTurn_2_0 + TestAlone_2_2_3 + TestAlone_2_3_3 + TestAlone_2_0_4 + TestAlone_2_1_4 + TestIdentity_2_1_0 + TestIdentity_2_3_0 + TestIdentity_2_2_0 + TestTurn_2_2 + TestTurn_2_1 + TestIdentity_2_0_0 + TestTurn_2_3 + TestIdentity_2_0_2 + TestIdentity_2_3_1 + TestIdentity_2_1_2 + TestIdentity_2_0_1 + TestIdentity_2_2_1 + TestIdentity_2_1_1 + TestIdentity_2_3_3 + TestIdentity_2_0_4 + TestIdentity_2_1_3 + TestIdentity_2_2_3 + TestIdentity_2_0_3 + TestIdentity_2_2_2 + TestIdentity_2_3_2 + TestIdentity_2_2_4 + TestIdentity_2_3_4 + TestIdentity_2_1_4 + AskForSection_2_3 + AskForSection_2_2 + AskForSection_2_1 + AskForSection_2_0 + Idle_2 + CS_2 = 1
invariant :Turn_3_1 + Turn_3_2 + Turn_3_0 + Turn_3_4 + Turn_3_3 = 1
invariant :WantSection_2_F + -1'Idle_2 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 9143 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 76 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([]((LTLAP0==true)))U([](<>((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1249 ms.
FORMULA Peterson-PT-4-LTLCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X((LTLAP2==true)))U(X((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 81 ms.
FORMULA Peterson-PT-4-LTLCardinality-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP4==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1311 ms.
FORMULA Peterson-PT-4-LTLCardinality-02 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA Peterson-PT-4-LTLCardinality-03 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(([]((LTLAP7==true)))U((LTLAP8==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1224 ms.
FORMULA Peterson-PT-4-LTLCardinality-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP9==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1206 ms.
FORMULA Peterson-PT-4-LTLCardinality-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1229 ms.
FORMULA Peterson-PT-4-LTLCardinality-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X((LTLAP11==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56 ms.
FORMULA Peterson-PT-4-LTLCardinality-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](((LTLAP12==true))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](((LTLAP12==true))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1138 ms.
FORMULA Peterson-PT-4-LTLCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1646 ms.
FORMULA Peterson-PT-4-LTLCardinality-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>(<>((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA Peterson-PT-4-LTLCardinality-11 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([]((LTLAP17==true)))U([](<>((LTLAP18==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1333 ms.
FORMULA Peterson-PT-4-LTLCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP19==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1172 ms.
FORMULA Peterson-PT-4-LTLCardinality-13 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1239 ms.
FORMULA Peterson-PT-4-LTLCardinality-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP21==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1213 ms.
FORMULA Peterson-PT-4-LTLCardinality-15 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](((LTLAP12==true))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
sparsehash FATAL ERROR: failed to allocate 33 groups
WARNING : LTSmin timed out (>1800 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](((LTLAP12==true))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
BK_STOP 1527492000496
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 6:39:48 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 6:39:48 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 6:39:49 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 215 ms
May 28, 2018 6:39:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 480 places.
May 28, 2018 6:39:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 690 transitions.
May 28, 2018 6:39:49 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 55 ms
May 28, 2018 6:39:49 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 384 ms
May 28, 2018 6:39:50 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 6 ms
May 28, 2018 6:39:50 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 24 ms
May 28, 2018 6:39:50 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 690 transitions.
May 28, 2018 6:39:51 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 19 place invariants in 178 ms
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 480 variables to be positive in 907 ms
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 690 transitions.
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/690 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 52 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 690 transitions.
May 28, 2018 6:39:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 20 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:40:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 690 transitions.
May 28, 2018 6:40:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/690) took 57 ms. Total solver calls (SAT/UNSAT): 137(0/137)
May 28, 2018 6:40:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/690) took 3985 ms. Total solver calls (SAT/UNSAT): 2709(0/2709)
May 28, 2018 6:40:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/690) took 7054 ms. Total solver calls (SAT/UNSAT): 3108(0/3108)
May 28, 2018 6:40:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/690) took 10230 ms. Total solver calls (SAT/UNSAT): 3902(0/3902)
May 28, 2018 6:40:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/690) took 14106 ms. Total solver calls (SAT/UNSAT): 8555(8/8547)
May 28, 2018 6:40:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/690) took 20022 ms. Total solver calls (SAT/UNSAT): 9041(29/9012)
May 28, 2018 6:40:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(71/690) took 23272 ms. Total solver calls (SAT/UNSAT): 9676(53/9623)
May 28, 2018 6:40:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/690) took 26810 ms. Total solver calls (SAT/UNSAT): 9987(68/9919)
May 28, 2018 6:41:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(77/690) took 31073 ms. Total solver calls (SAT/UNSAT): 10598(92/10506)
May 28, 2018 6:41:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(84/690) took 34976 ms. Total solver calls (SAT/UNSAT): 11501(101/11400)
May 28, 2018 6:41:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(91/690) took 38704 ms. Total solver calls (SAT/UNSAT): 12443(124/12319)
May 28, 2018 6:41:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/690) took 41870 ms. Total solver calls (SAT/UNSAT): 12727(137/12590)
May 28, 2018 6:41:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/690) took 44893 ms. Total solver calls (SAT/UNSAT): 15447(146/15301)
May 28, 2018 6:41:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(145/690) took 48769 ms. Total solver calls (SAT/UNSAT): 18705(178/18527)
May 28, 2018 6:41:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/690) took 54342 ms. Total solver calls (SAT/UNSAT): 18953(210/18743)
May 28, 2018 6:41:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(160/690) took 57388 ms. Total solver calls (SAT/UNSAT): 20354(226/20128)
May 28, 2018 6:41:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(228/690) took 60419 ms. Total solver calls (SAT/UNSAT): 27052(226/26826)
May 28, 2018 6:41:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(242/690) took 63952 ms. Total solver calls (SAT/UNSAT): 28330(240/28090)
May 28, 2018 6:41:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(245/690) took 68555 ms. Total solver calls (SAT/UNSAT): 28632(279/28353)
May 28, 2018 6:41:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(246/690) took 71680 ms. Total solver calls (SAT/UNSAT): 28732(292/28440)
May 28, 2018 6:41:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(249/690) took 76355 ms. Total solver calls (SAT/UNSAT): 29030(329/28701)
May 28, 2018 6:41:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(252/690) took 82578 ms. Total solver calls (SAT/UNSAT): 29327(368/28959)
May 28, 2018 6:41:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(254/690) took 88126 ms. Total solver calls (SAT/UNSAT): 29523(392/29131)
May 28, 2018 6:42:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(256/690) took 93869 ms. Total solver calls (SAT/UNSAT): 29718(418/29300)
May 28, 2018 6:42:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(259/690) took 98990 ms. Total solver calls (SAT/UNSAT): 30008(453/29555)
May 28, 2018 6:42:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(261/690) took 102955 ms. Total solver calls (SAT/UNSAT): 30200(476/29724)
May 28, 2018 6:42:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(263/690) took 106522 ms. Total solver calls (SAT/UNSAT): 30390(498/29892)
May 28, 2018 6:42:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(264/690) took 109663 ms. Total solver calls (SAT/UNSAT): 30484(508/29976)
May 28, 2018 6:42:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(267/690) took 114013 ms. Total solver calls (SAT/UNSAT): 30763(538/30225)
May 28, 2018 6:42:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(270/690) took 117043 ms. Total solver calls (SAT/UNSAT): 31039(566/30473)
May 28, 2018 6:42:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(272/690) took 120074 ms. Total solver calls (SAT/UNSAT): 31222(585/30637)
May 28, 2018 6:42:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(281/690) took 123644 ms. Total solver calls (SAT/UNSAT): 31977(604/31373)
May 28, 2018 6:42:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(283/690) took 126825 ms. Total solver calls (SAT/UNSAT): 32156(623/31533)
May 28, 2018 6:42:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(287/690) took 130832 ms. Total solver calls (SAT/UNSAT): 32504(654/31850)
May 28, 2018 6:42:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/690) took 134141 ms. Total solver calls (SAT/UNSAT): 32845(681/32164)
May 28, 2018 6:42:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(295/690) took 137704 ms. Total solver calls (SAT/UNSAT): 33182(707/32475)
May 28, 2018 6:42:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(299/690) took 141976 ms. Total solver calls (SAT/UNSAT): 33522(740/32782)
May 28, 2018 6:42:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(301/690) took 144993 ms. Total solver calls (SAT/UNSAT): 33690(755/32935)
May 28, 2018 6:42:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(305/690) took 148165 ms. Total solver calls (SAT/UNSAT): 34016(778/33238)
May 28, 2018 6:43:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(308/690) took 152278 ms. Total solver calls (SAT/UNSAT): 34281(813/33468)
May 28, 2018 6:43:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(310/690) took 155623 ms. Total solver calls (SAT/UNSAT): 34454(832/33622)
May 28, 2018 6:43:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(312/690) took 159731 ms. Total solver calls (SAT/UNSAT): 34629(855/33774)
May 28, 2018 6:43:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(315/690) took 163699 ms. Total solver calls (SAT/UNSAT): 34887(886/34001)
May 28, 2018 6:43:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(317/690) took 167399 ms. Total solver calls (SAT/UNSAT): 35058(907/34151)
May 28, 2018 6:43:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(320/690) took 171445 ms. Total solver calls (SAT/UNSAT): 35314(939/34375)
May 28, 2018 6:43:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(322/690) took 174784 ms. Total solver calls (SAT/UNSAT): 35481(958/34523)
May 28, 2018 6:43:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(324/690) took 177802 ms. Total solver calls (SAT/UNSAT): 35643(975/34668)
May 28, 2018 6:43:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(328/690) took 182093 ms. Total solver calls (SAT/UNSAT): 35965(1005/34960)
May 28, 2018 6:43:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(332/690) took 186603 ms. Total solver calls (SAT/UNSAT): 36285(1037/35248)
May 28, 2018 6:43:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(334/690) took 189887 ms. Total solver calls (SAT/UNSAT): 36448(1056/35392)
May 28, 2018 6:43:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(337/690) took 193506 ms. Total solver calls (SAT/UNSAT): 36689(1081/35608)
May 28, 2018 6:43:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(342/690) took 196654 ms. Total solver calls (SAT/UNSAT): 37052(1103/35949)
May 28, 2018 6:43:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(348/690) took 199664 ms. Total solver calls (SAT/UNSAT): 37478(1123/36355)
May 28, 2018 6:43:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(351/690) took 203970 ms. Total solver calls (SAT/UNSAT): 37693(1139/36554)
May 28, 2018 6:44:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(354/690) took 209431 ms. Total solver calls (SAT/UNSAT): 37908(1155/36753)
May 28, 2018 6:44:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(356/690) took 212697 ms. Total solver calls (SAT/UNSAT): 38057(1170/36887)
May 28, 2018 6:44:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(360/690) took 216768 ms. Total solver calls (SAT/UNSAT): 38351(1197/37154)
May 28, 2018 6:44:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(365/690) took 220057 ms. Total solver calls (SAT/UNSAT): 38698(1221/37477)
May 28, 2018 6:44:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(379/690) took 223489 ms. Total solver calls (SAT/UNSAT): 39600(1244/38356)
May 28, 2018 6:44:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(384/690) took 226802 ms. Total solver calls (SAT/UNSAT): 39926(1262/38664)
May 28, 2018 6:44:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(403/690) took 229942 ms. Total solver calls (SAT/UNSAT): 41054(1276/39778)
May 28, 2018 6:44:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(410/690) took 233498 ms. Total solver calls (SAT/UNSAT): 41476(1297/40179)
May 28, 2018 6:44:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(415/690) took 236648 ms. Total solver calls (SAT/UNSAT): 41778(1319/40459)
May 28, 2018 6:44:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(427/690) took 240072 ms. Total solver calls (SAT/UNSAT): 42449(1340/41109)
May 28, 2018 6:44:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(498/690) took 243338 ms. Total solver calls (SAT/UNSAT): 45681(1354/44327)
May 28, 2018 6:44:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(501/690) took 246644 ms. Total solver calls (SAT/UNSAT): 45908(1375/44533)
May 28, 2018 6:44:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(505/690) took 249660 ms. Total solver calls (SAT/UNSAT): 46206(1401/44805)
May 28, 2018 6:44:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(509/690) took 253297 ms. Total solver calls (SAT/UNSAT): 46488(1427/45061)
May 28, 2018 6:44:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(511/690) took 256675 ms. Total solver calls (SAT/UNSAT): 46621(1440/45181)
May 28, 2018 6:44:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(516/690) took 259811 ms. Total solver calls (SAT/UNSAT): 46966(1474/45492)
May 28, 2018 6:44:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(522/690) took 262827 ms. Total solver calls (SAT/UNSAT): 47364(1515/45849)
May 28, 2018 6:44:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(527/690) took 266147 ms. Total solver calls (SAT/UNSAT): 47668(1547/46121)
May 28, 2018 6:45:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(534/690) took 269147 ms. Total solver calls (SAT/UNSAT): 48127(1594/46533)
May 28, 2018 6:45:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(539/690) took 272618 ms. Total solver calls (SAT/UNSAT): 48447(1627/46820)
May 28, 2018 6:45:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(543/690) took 275739 ms. Total solver calls (SAT/UNSAT): 48681(1650/47031)
May 28, 2018 6:45:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(555/690) took 279290 ms. Total solver calls (SAT/UNSAT): 49096(1669/47427)
May 28, 2018 6:45:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(564/690) took 282318 ms. Total solver calls (SAT/UNSAT): 49495(1706/47789)
May 28, 2018 6:45:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(575/690) took 285374 ms. Total solver calls (SAT/UNSAT): 49916(1729/48187)
May 28, 2018 6:45:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(581/690) took 288569 ms. Total solver calls (SAT/UNSAT): 50106(1741/48365)
May 28, 2018 6:45:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(584/690) took 292155 ms. Total solver calls (SAT/UNSAT): 50244(1760/48484)
SMT solver raised 'unknown', retrying with same input.
May 28, 2018 6:45:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(590/690) took 295892 ms. Total solver calls (SAT/UNSAT): 50506(1784/48722)
May 28, 2018 6:45:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(595/690) took 298898 ms. Total solver calls (SAT/UNSAT): 50690(1804/48886)
May 28, 2018 6:45:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(605/690) took 302086 ms. Total solver calls (SAT/UNSAT): 50998(1818/49180)
May 28, 2018 6:45:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(615/690) took 305960 ms. Total solver calls (SAT/UNSAT): 51221(1834/49387)
May 28, 2018 6:45:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(620/690) took 309370 ms. Total solver calls (SAT/UNSAT): 51347(1853/49494)
May 28, 2018 6:45:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(624/690) took 312634 ms. Total solver calls (SAT/UNSAT): 51488(1873/49615)
May 28, 2018 6:45:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(626/690) took 316107 ms. Total solver calls (SAT/UNSAT): 51552(1881/49671)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 28, 2018 6:45:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 318337 ms. Total solver calls (SAT/UNSAT): 51670(1894/49776)
May 28, 2018 6:45:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 690 transitions.
May 28, 2018 6:45:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 825 ms. Total solver calls (SAT/UNSAT): 212(0/212)
May 28, 2018 6:45:51 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 360703ms conformant to PINS in folder :/home/mcc/execution
ITS-tools command line returned an error code 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-4"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-4.tgz
mv Peterson-PT-4 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is Peterson-PT-4, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585400163"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;