About the Execution of ITS-Tools for PermAdmissibility-PT-01
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15756.850 | 113723.00 | 269630.00 | 130.40 | FFTFTFFFFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
...........................................................................................
/home/mcc/execution
total 884K
-rw-r--r-- 1 mcc users 5.1K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.9K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 9.3K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 36K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 27K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 114 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 352 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 28K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 104K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 484K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is PermAdmissibility-PT-01, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585300136
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-00
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-01
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-02
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-03
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-04
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-05
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-06
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-07
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-08
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-09
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-10
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-11
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-12
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-13
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-14
FORMULA_NAME PermAdmissibility-PT-01-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1527488016208
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((("((((((((((((((((((aux8_2>=1)&&(c11>=1))&&(aux6_0>=1))||(((aux6_1>=1)&&(aux8_2>=1))&&(c11>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c11>=1)))||(((aux6_5>=1)&&(aux8_2>=1))&&(c11>=1)))||(((c11>=1)&&(aux8_3>=1))&&(aux6_0>=1)))||(((aux6_5>=1)&&(c11>=1))&&(aux8_7>=1)))||(((c11>=1)&&(aux8_7>=1))&&(aux6_4>=1)))||(((aux6_1>=1)&&(aux8_7>=1))&&(c11>=1)))||(((aux6_0>=1)&&(aux8_7>=1))&&(c11>=1)))||(((c11>=1)&&(aux8_6>=1))&&(aux6_5>=1)))||(((aux6_4>=1)&&(c11>=1))&&(aux8_6>=1)))||(((c11>=1)&&(aux8_6>=1))&&(aux6_1>=1)))||(((aux8_6>=1)&&(c11>=1))&&(aux6_0>=1)))||(((aux8_3>=1)&&(c11>=1))&&(aux6_5>=1)))||(((aux8_3>=1)&&(c11>=1))&&(aux6_4>=1)))||(((aux6_1>=1)&&(c11>=1))&&(aux8_3>=1)))")U(X(("((((((c5>=1)&&(in1_1>=1))&&(in3_4>=1))||(((c5>=1)&&(in1_0>=1))&&(in3_5>=1)))||(((c5>=1)&&(in1_1>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c5>=1))&&(in3_4>=1)))")U("((((((((((((((((((c12>=1)&&(aux8_7>=1))&&(aux6_1>=1))||(((aux8_7>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux8_7>=1)&&(c12>=1))&&(aux6_5>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_1>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(c12>=1))&&(aux8_3>=1)))||(((c12>=1)&&(aux8_6>=1))&&(aux6_0>=1)))||(((aux6_1>=1)&&(aux8_6>=1))&&(c12>=1)))||(((aux8_6>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(aux8_6>=1))&&(c12>=1)))||(((c12>=1)&&(aux8_7>=1))&&(aux6_0>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_2>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c12>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_1>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_3>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_5>=1)))")))))
Formula 0 simplified : !("((((((((((((((((((aux8_2>=1)&&(c11>=1))&&(aux6_0>=1))||(((aux6_1>=1)&&(aux8_2>=1))&&(c11>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c11>=1)))||(((aux6_5>=1)&&(aux8_2>=1))&&(c11>=1)))||(((c11>=1)&&(aux8_3>=1))&&(aux6_0>=1)))||(((aux6_5>=1)&&(c11>=1))&&(aux8_7>=1)))||(((c11>=1)&&(aux8_7>=1))&&(aux6_4>=1)))||(((aux6_1>=1)&&(aux8_7>=1))&&(c11>=1)))||(((aux6_0>=1)&&(aux8_7>=1))&&(c11>=1)))||(((c11>=1)&&(aux8_6>=1))&&(aux6_5>=1)))||(((aux6_4>=1)&&(c11>=1))&&(aux8_6>=1)))||(((c11>=1)&&(aux8_6>=1))&&(aux6_1>=1)))||(((aux8_6>=1)&&(c11>=1))&&(aux6_0>=1)))||(((aux8_3>=1)&&(c11>=1))&&(aux6_5>=1)))||(((aux8_3>=1)&&(c11>=1))&&(aux6_4>=1)))||(((aux6_1>=1)&&(c11>=1))&&(aux8_3>=1)))" U X("((((((c5>=1)&&(in1_1>=1))&&(in3_4>=1))||(((c5>=1)&&(in1_0>=1))&&(in3_5>=1)))||(((c5>=1)&&(in1_1>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c5>=1))&&(in3_4>=1)))" U "((((((((((((((((((c12>=1)&&(aux8_7>=1))&&(aux6_1>=1))||(((aux8_7>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux8_7>=1)&&(c12>=1))&&(aux6_5>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_1>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(c12>=1))&&(aux8_3>=1)))||(((c12>=1)&&(aux8_6>=1))&&(aux6_0>=1)))||(((aux6_1>=1)&&(aux8_6>=1))&&(c12>=1)))||(((aux8_6>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(aux8_6>=1))&&(c12>=1)))||(((c12>=1)&&(aux8_7>=1))&&(aux6_0>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_2>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c12>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_1>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_3>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_5>=1)))"))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant :out1_0 + out1_6 + out1_5 + -1'out2_0 + out1_7 + out1_2 + out1_1 + out1_4 + out1_3 + -1'out2_7 + -1'out2_5 + -1'out2_6 + -1'out2_3 + -1'out2_4 + -1'out2_1 + -1'out2_2 = 0
invariant :aux7_7 + aux7_6 + -1'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + aux7_3 + aux7_2 + 2'c7 + -4'c5 + 2'in1_1 + 2'in1_0 = 0
invariant :aux6_0 + -1'aux8_7 + -1'aux8_3 + -1'aux8_6 + aux6_5 + -1'aux8_2 + aux6_1 + aux6_4 + -2'c7 + -2'c8 = 0
invariant :-1'aux16_3 + -1'aux16_6 + aux14_2 + aux14_7 + -1'out7_3 + -1'out7_6 + out8_2 + out8_7 + -1'out5_6 + -1'out5_3 + out6_2 + out6_7 + -1'aux15_6 + -1'aux15_3 + aux13_2 + aux13_7 + -1'out3_6 + -1'out3_3 + out4_7 + out4_2 + -1'out1_6 + -1'out1_3 + out2_7 + out2_2 + -1'aux8_3 + -1'aux8_6 + -1'aux12_6 + -1'aux12_3 + aux11_2 + c11 + -1'aux7_6 + -1'aux10_3 + aux11_7 + aux5_1 + aux5_0 + aux5_5 + aux5_4 + -1'aux7_3 + aux9_7 + in4_7 + -1'in2_3 + -1'aux10_6 + aux9_2 + -2'c7 + -1'c8 + 4'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :c18 + out4_0 + out4_1 + out4_7 + out4_6 + out4_3 + out4_2 + out4_5 + out4_4 + -1'out2_0 + -1'out2_7 + -1'out2_5 + -1'out2_6 + -1'out2_3 + -1'out2_4 + -1'out2_1 + -1'out2_2 = 0
invariant :aux16_3 + aux14_3 + out7_3 + out8_3 + out5_3 + out6_3 + aux15_3 + aux13_3 + out3_3 + out4_3 + out1_3 + out2_3 + aux8_3 + aux12_3 + aux11_3 + aux10_3 + aux7_3 + in2_3 + aux9_3 = 1
invariant :in4_6 + in4_7 + -2'c7 + -1'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :2'c5 + c6 + -1'in1_1 + -1'in1_0 = 0
invariant :-1'aux8_7 + c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'aux5_1 + 2'aux5_0 + 2'aux5_5 + 2'aux5_4 + -2'c9 + -4'c7 + -4'c8 + 8'c5 + -4'in1_1 + -4'in1_0 = 0
invariant :in2_2 + in2_3 + -2'c7 + -1'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :out7_1 + out7_0 + out7_3 + out7_2 + out7_5 + out7_4 + out7_7 + out7_6 + -1'out8_1 + -1'out8_0 + -1'out8_3 + -1'out8_2 + -1'out8_6 + -1'out8_7 + -1'out8_4 + -1'out8_5 = 0
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + 2'c17 + out4_5 + out4_4 + out1_6 + 3'out2_0 + -1'out1_1 + 2'out2_7 + 3'out2_5 + 3'out2_6 + 2'out2_3 + 3'out2_4 + 2'out2_1 + 2'out2_2 + 4'aux8_7 + 4'aux8_3 + 5'aux8_6 + 4'aux8_2 + -1'aux6_1 + 3'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + aux12_1 + 2'aux12_0 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -5'c11 + 2'aux12_7 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -6'aux5_1 + -5'aux5_0 + -5'aux5_5 + -5'aux5_4 + -1'aux9_7 + -1'in4_7 + aux10_6 + 4'c9 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c15 + -2'c14 + 14'c7 + 13'c8 + -24'c5 + 13'in1_1 + 14'in1_0 = 2
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + out4_5 + out4_4 + out1_6 + out2_0 + -1'out1_1 + out2_5 + out2_6 + out2_4 + 2'aux8_7 + 2'aux8_3 + 3'aux8_6 + 2'aux8_2 + -1'aux6_1 + aux12_6 + -1'aux12_1 + 2'c13 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -3'c11 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -4'aux5_1 + -3'aux5_0 + -3'aux5_5 + -3'aux5_4 + -1'aux9_7 + -1'in4_7 + aux10_6 + 2'c9 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + 8'c7 + 7'c8 + -14'c5 + 7'in1_1 + 8'in1_0 = 0
invariant :c19 + out6_1 + out6_2 + out6_0 + out6_6 + out6_5 + out6_4 + out6_3 + out6_7 + -1'out4_0 + -1'out4_1 + -1'out4_7 + -1'out4_6 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 = 0
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + out4_5 + out4_4 + out1_6 + out2_0 + -1'out1_1 + out2_5 + out2_6 + out2_4 + aux8_6 + -1'aux6_1 + aux12_6 + -1'aux12_1 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -1'c11 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -2'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + aux9_4 + aux9_5 + aux9_6 + -1'in4_7 + aux10_6 + 2'c9 + aux9_0 + -1'c14 + 4'c7 + 3'c8 + -6'c5 + 3'in1_1 + 4'in1_0 = 0
invariant :c20 + out8_1 + out8_0 + out8_3 + out8_2 + out8_6 + out8_7 + out8_4 + out8_5 + -1'out6_1 + -1'out6_2 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -1'out6_3 + -1'out6_7 = 0
invariant :-1'aux16_0 + aux16_1 + -1'aux16_6 + 2'aux14_1 + 2'aux14_2 + 2'aux14_3 + aux14_4 + aux14_6 + aux14_5 + 2'aux14_7 + out7_1 + -1'out7_0 + -1'out7_6 + 2'out8_1 + 2'out8_3 + 2'out8_2 + out8_6 + 2'out8_7 + out8_4 + out8_5 + -1'out5_2 + -2'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 3'out6_1 + 3'out6_2 + -1'out5_7 + out6_0 + 2'out6_6 + 2'out6_5 + 2'out6_4 + 3'out6_3 + aux15_1 + -1'aux15_0 + 3'out6_7 + -1'aux15_6 + -2'aux13_0 + 2'out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + out3_7 + -3'out4_0 + -1'out4_1 + out3_2 + out3_3 + out3_4 + out3_5 + -1'out4_7 + -2'out4_6 + -1'out1_0 + -1'out4_3 + -1'out4_2 + -2'out4_5 + -2'out4_4 + -1'out1_6 + -2'out2_0 + out1_1 + -1'out2_5 + -1'out2_6 + -1'out2_4 + -1'aux8_7 + -1'aux8_3 + -2'aux8_6 + aux6_5 + -1'aux8_2 + 2'aux6_1 + aux6_4 + -1'aux12_6 + aux12_1 + -1'aux12_0 + aux11_3 + aux11_2 + aux11_1 + -1'aux11_0 + c11 + -1'aux7_6 + -1'aux10_0 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + -1'aux9_0 + aux9_1 + aux9_2 + aux9_3 + 2'c14 + -4'c7 + -3'c8 + 4'c5 + -1'in1_1 + -3'in1_0 = 1
invariant :-2'aux16_1 + aux16_6 + -2'aux14_1 + -2'aux14_2 + -2'aux14_3 + -1'aux14_6 + -2'aux14_7 + -2'out7_1 + out7_6 + -2'out8_1 + -2'out8_3 + -2'out8_2 + -1'out8_6 + -2'out8_7 + 2'out5_2 + 2'out5_0 + 2'out5_5 + 3'out5_6 + 2'out5_3 + 2'out5_4 + -4'out6_1 + -4'out6_2 + 2'out5_7 + -2'out6_0 + -3'out6_6 + -2'out6_5 + -2'out6_4 + -4'out6_3 + -2'aux15_1 + -4'out6_7 + aux15_6 + 2'aux13_0 + -2'out3_1 + 2'aux13_4 + 2'aux13_5 + aux13_6 + out3_6 + 2'out4_0 + out4_6 + 2'out4_5 + 2'out4_4 + out1_6 + 2'out2_0 + -2'out1_1 + 2'out2_5 + out2_6 + 2'out2_4 + aux8_6 + -2'aux6_1 + aux12_6 + -2'aux12_1 + aux11_5 + aux11_4 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + aux11_0 + aux7_6 + -2'aux10_1 + -1'aux11_7 + -2'aux5_1 + aux9_4 + aux9_5 + -1'aux9_7 + -1'in4_7 + aux10_6 + aux9_0 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c14 + 2'c7 + c8 + -2'c5 + 2'in1_0 = -1
invariant :aux16_1 + -1'aux16_6 + aux14_1 + aux14_2 + aux14_3 + aux14_7 + out7_1 + -1'out7_6 + out8_1 + out8_3 + out8_2 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_1 + 2'out6_7 + -1'aux15_6 + -1'aux13_0 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out4_0 + -1'out4_6 + 2'c17 + -1'out4_5 + -1'out4_4 + -1'out1_6 + out2_0 + out1_1 + 2'out2_7 + out2_5 + out2_6 + 2'out2_3 + out2_4 + 2'out2_1 + 2'out2_2 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -1'aux7_6 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + aux9_1 + aux9_2 + aux9_3 + 2'c16 + 2'c15 + 2'c14 + -2'c7 + -1'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 2
invariant :-1'aux16_1 + aux16_6 + aux16_7 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'out7_1 + out7_7 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + 2'out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_2 + -2'aux15_1 + -1'aux15_0 + -1'out6_7 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + aux13_0 + aux13_7 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out3_7 + -1'out4_1 + -1'out4_3 + -1'out4_2 + out1_6 + out1_7 + -1'out1_1 + -1'out2_3 + -1'out2_1 + -1'out2_2 + aux8_7 + aux8_6 + -1'aux6_1 + aux12_6 + -1'aux12_1 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -1'c11 + aux12_7 + -1'aux10_1 + -1'aux5_1 + -1'aux7_3 + -1'aux7_2 + aux10_6 + aux10_7 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c15 + -2'c14 + c8 + -1'in1_1 = -1
invariant :aux16_0 + aux16_1 + aux16_4 + -1'aux14_5 + out7_1 + out7_0 + out7_4 + -1'out8_5 + -1'out5_2 + -1'out5_5 + -1'out5_6 + -1'out5_3 + out6_1 + out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_4 + out6_3 + aux15_1 + aux15_0 + out6_7 + aux15_4 + -1'aux13_5 + -1'out3_6 + -1'out3_7 + out4_0 + out4_1 + -1'out3_2 + -1'out3_3 + -1'out3_5 + out4_7 + out4_6 + out1_0 + out4_3 + out4_2 + out4_4 + out1_1 + out1_4 + -1'out2_5 + aux8_7 + aux8_3 + aux8_6 + -1'aux6_5 + aux8_2 + aux12_4 + aux12_1 + aux12_0 + -1'aux11_5 + -1'c11 + aux10_0 + aux10_1 + aux10_4 + -1'aux5_5 + -1'aux9_5 + in3_4 + 2'c7 + 2'c8 + -2'c5 + in1_1 + in1_0 = 1
invariant :aux16_1 + -1'aux16_6 + -2'aux16_7 + aux14_1 + aux14_2 + aux14_3 + -1'aux14_7 + out7_1 + -2'out7_7 + -1'out7_6 + out8_1 + out8_3 + out8_2 + -1'out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -3'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + 2'aux15_2 + 3'aux15_1 + 2'aux15_0 + aux15_6 + 2'aux15_5 + 2'aux15_4 + 2'aux15_3 + -1'aux13_0 + -2'aux13_7 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -2'out3_7 + out4_0 + 2'out4_1 + out4_6 + 2'c17 + 2'out4_3 + 2'out4_2 + out4_5 + out4_4 + -1'out1_6 + 3'out2_0 + -2'out1_7 + out1_1 + 2'out2_7 + 3'out2_5 + 3'out2_6 + 4'out2_3 + 3'out2_4 + 4'out2_1 + 4'out2_2 + -2'aux8_7 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -2'aux12_7 + aux7_6 + 2'aux10_0 + 2'aux10_2 + 3'aux10_1 + 2'aux10_4 + 2'aux10_3 + -1'aux11_7 + 4'aux5_1 + 3'aux5_0 + 3'aux5_5 + 3'aux5_4 + 2'aux7_3 + 2'aux7_2 + -1'aux9_7 + -1'in4_7 + 2'aux10_5 + aux10_6 + -4'c9 + aux9_1 + aux9_2 + aux9_3 + 2'c15 + 2'c14 + -2'c7 + -5'c8 + 8'c5 + -1'in1_1 + -2'in1_0 = 4
invariant :out5_1 + out5_2 + out5_0 + out5_5 + out5_6 + out5_3 + out5_4 + -1'out6_1 + -1'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -1'out6_3 + -1'out6_7 = 0
invariant :aux16_1 + aux14_1 + out7_1 + out8_1 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -1'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + out6_3 + aux15_1 + out6_7 + aux13_1 + out3_1 + out4_1 + out1_1 + out2_1 + aux6_1 + aux12_1 + aux11_1 + aux10_1 + aux5_1 + aux9_1 + in1_1 = 1
invariant :aux16_0 + aux14_0 + out7_0 + out8_0 + out5_0 + out6_0 + aux15_0 + aux13_0 + -1'out3_1 + -1'out3_6 + -1'out3_7 + 2'out4_0 + out4_1 + -1'out3_2 + -1'out3_3 + -1'out3_4 + -1'out3_5 + out4_7 + out4_6 + out1_0 + out4_3 + out4_2 + out4_5 + out4_4 + out2_0 + aux8_7 + aux8_3 + aux8_6 + -1'aux6_5 + aux8_2 + -1'aux6_1 + -1'aux6_4 + aux12_0 + aux11_0 + aux10_0 + aux5_0 + aux9_0 + 2'c7 + 2'c8 + in1_0 = 1
invariant :c110 + -1'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + 2'c9 + 2'c7 + 2'c8 + -4'c5 + 2'in1_1 + 2'in1_0 = 0
invariant :out3_0 + out3_1 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + out3_2 + out3_3 + out3_4 + out3_5 + -1'out4_7 + -1'out4_6 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 = 0
invariant :aux16_1 + aux14_1 + aux14_2 + aux14_3 + aux14_6 + aux14_7 + out7_1 + out8_1 + out8_3 + out8_2 + out8_6 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -1'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + 2'out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_1 + 2'out6_7 + -1'aux13_0 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'out4_0 + -1'out4_5 + -1'out4_4 + -1'out2_0 + out1_1 + -1'out2_5 + -1'out2_4 + aux6_1 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + aux10_1 + aux11_7 + aux11_6 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + -1'aux9_4 + -1'aux9_5 + -2'c9 + -1'aux9_0 + c14 + -2'c7 + -2'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 1
invariant :aux16_2 + aux16_3 + aux16_6 + aux16_7 + out7_3 + out7_2 + out7_7 + out7_6 + out5_2 + out5_6 + out5_3 + out5_7 + -1'aux15_1 + -1'aux15_0 + -1'aux15_5 + -1'aux15_4 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + out3_2 + out3_3 + -1'out4_7 + -1'out4_6 + -2'c17 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 + out1_6 + -3'out2_0 + out1_7 + out1_2 + out1_3 + -3'out2_7 + -3'out2_5 + -3'out2_6 + -3'out2_3 + -3'out2_4 + -3'out2_1 + -3'out2_2 + -1'aux8_7 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + -1'aux12_5 + -1'aux12_4 + -1'aux12_1 + -1'aux12_0 + c11 + -1'aux10_0 + -1'aux10_1 + -1'aux10_4 + -1'aux10_5 + -2'c7 + -2'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = -2
invariant :aux16_1 + -1'aux16_6 + aux14_1 + aux14_2 + aux14_3 + aux14_7 + out7_1 + -1'out7_6 + out8_1 + out8_3 + out8_2 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_2 + 2'aux15_1 + aux15_0 + 2'out6_7 + aux15_5 + aux15_4 + aux15_3 + -1'aux13_0 + aux15_7 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + out4_1 + out4_7 + out4_3 + out4_2 + -1'out1_6 + out1_1 + out2_7 + out2_3 + out2_1 + out2_2 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -1'aux7_6 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + aux9_1 + aux9_2 + aux9_3 + 2'c15 + 2'c14 + -2'c7 + -1'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 2
invariant :in3_5 + in3_4 + -1'in1_1 + -1'in1_0 = 0
invariant :aux16_5 + aux14_5 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_4 + -1'out7_7 + -1'out7_6 + out8_1 + out8_0 + out8_3 + out8_2 + out8_6 + out8_7 + out8_4 + 2'out8_5 + out5_5 + out6_5 + aux15_5 + aux13_5 + out3_5 + -1'out1_0 + out4_5 + -1'out1_6 + out2_0 + -1'out1_7 + -1'out1_2 + -1'out1_1 + -1'out1_4 + -1'out1_3 + out2_7 + 2'out2_5 + out2_6 + out2_3 + out2_4 + out2_1 + out2_2 + aux6_5 + aux12_5 + aux11_5 + aux5_5 + aux9_5 + aux10_5 + -1'in3_4 + in1_1 + in1_0 = 1
Reverse transition relation is NOT exact ! Due to transitions switch9_2_0, switch9_3_0, switch9_4_0, switch9_3_5, switch9_1_5, switch9_2_5, switch9_7_4, switch9_0_5, switch9_6_4, switch9_3_6, switch9_4_6, switch9_1_6, switch9_2_6, switch9_7_5, switch9_0_6, switch9_6_5, switch9_4_7, switch9_3_7, switch9_2_7, switch9_1_7, switch9_0_7, switch9_5_6, switch10_4_0, switch10_3_0, switch10_2_0, switch9_5_7, switch9_2_1, switch9_3_1, switch9_4_1, switch9_5_0, switch9_6_0, switch9_7_0, switch9_1_2, switch9_4_2, switch9_5_1, switch9_6_1, switch9_7_1, switch9_0_2, switch9_1_3, switch9_4_3, switch9_6_2, switch9_5_2, switch9_0_3, switch9_7_2, switch9_2_4, switch9_1_4, switch9_3_4, switch9_6_3, switch9_5_3, switch9_0_4, switch9_7_3, switch10_7_4, switch10_0_5, switch10_6_4, switch10_3_5, switch10_1_5, switch10_2_5, switch10_7_5, switch10_0_6, switch10_6_5, switch10_3_6, switch10_4_6, switch10_1_6, switch10_2_6, switch10_0_7, switch10_5_6, switch10_4_7, switch10_3_7, switch10_2_7, switch10_1_7, switch10_5_7, switch11_4_0, switch11_3_0, switch11_2_0, switch10_5_0, switch10_6_0, switch10_7_0, switch10_2_1, switch10_3_1, switch10_4_1, switch10_5_1, switch10_6_1, switch10_7_1, switch10_0_2, switch10_1_2, switch10_4_2, switch10_6_2, switch10_5_2, switch10_0_3, switch10_7_2, switch10_1_3, switch10_4_3, switch10_6_3, switch10_5_3, switch10_0_4, switch10_7_3, switch10_2_4, switch10_1_4, switch10_3_4, switch11_4_6, switch11_3_6, switch11_2_6, switch11_1_6, switch11_0_6, switch11_7_5, switch11_6_5, switch11_3_5, switch11_2_5, switch11_1_5, switch11_0_5, switch11_7_4, switch11_6_4, switch11_5_7, switch11_3_7, switch11_4_7, switch11_1_7, switch11_2_7, switch11_0_7, switch11_5_6, switch11_1_2, switch11_4_2, switch11_6_1, switch11_5_1, switch11_0_2, switch11_7_1, switch11_2_1, switch11_4_1, switch11_3_1, switch11_6_0, switch11_5_0, switch11_7_0, switch11_1_4, switch11_2_4, switch11_3_4, switch11_5_3, switch11_6_3, switch11_7_3, switch11_0_4, switch11_1_3, switch11_4_3, switch11_5_2, switch11_6_2, switch11_7_2, switch11_0_3, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :64/384/144/592
Computing Next relation with stutter on 18688 deadlock states
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
8532 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,85.4407,1755248,1,0,1172,3.66222e+06,1157,556,18595,1.07899e+06,1196
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !((G("((((((in4_7>=1)&&(c8>=1))&&(in2_2>=1))||(((in4_6>=1)&&(in2_3>=1))&&(c8>=1)))||(((in4_7>=1)&&(c8>=1))&&(in2_3>=1)))||(((in4_6>=1)&&(in2_2>=1))&&(c8>=1)))")))
Formula 1 simplified : !G"((((((in4_7>=1)&&(c8>=1))&&(in2_2>=1))||(((in4_6>=1)&&(in2_3>=1))&&(c8>=1)))||(((in4_7>=1)&&(c8>=1))&&(in2_3>=1)))||(((in4_6>=1)&&(in2_2>=1))&&(c8>=1)))"
Computing Next relation with stutter on 18688 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
4 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,85.4824,1756348,1,0,1173,3.6625e+06,1163,558,18616,1.07921e+06,1209
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 2 : !((F("((((((c5>=1)&&(in1_1>=1))&&(in3_4>=1))||(((c5>=1)&&(in1_0>=1))&&(in3_5>=1)))||(((c5>=1)&&(in1_1>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c5>=1))&&(in3_4>=1)))")))
Formula 2 simplified : !F"((((((c5>=1)&&(in1_1>=1))&&(in3_4>=1))||(((c5>=1)&&(in1_0>=1))&&(in3_5>=1)))||(((c5>=1)&&(in1_1>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c5>=1))&&(in3_4>=1)))"
Computing Next relation with stutter on 18688 deadlock states
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,85.4845,1756348,1,0,1173,3.6625e+06,1170,558,18616,1.07921e+06,1213
no accepting run found
Formula 2 is TRUE no accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 3 : !((F(F(G(("((((((in1_1>=1)&&(c6>=1))&&(in3_4>=1))||(((in3_5>=1)&&(in1_0>=1))&&(c6>=1)))||(((in1_1>=1)&&(c6>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c6>=1))&&(in3_4>=1)))")U("((((((((((((((((((aux5_5>=1)&&(aux7_7>=1))&&(c110>=1))||(((aux5_1>=1)&&(c110>=1))&&(aux7_7>=1)))||(((aux5_4>=1)&&(aux7_7>=1))&&(c110>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_5>=1)))||(((c110>=1)&&(aux7_7>=1))&&(aux5_0>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_1>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_4>=1)))||(((c110>=1)&&(aux7_3>=1))&&(aux5_5>=1)))||(((c110>=1)&&(aux7_6>=1))&&(aux5_0>=1)))||(((aux5_1>=1)&&(aux7_3>=1))&&(c110>=1)))||(((aux5_4>=1)&&(c110>=1))&&(aux7_3>=1)))||(((aux5_0>=1)&&(aux7_3>=1))&&(c110>=1)))||(((aux5_5>=1)&&(c110>=1))&&(aux7_2>=1)))||(((c110>=1)&&(aux7_2>=1))&&(aux5_4>=1)))||(((aux5_1>=1)&&(c110>=1))&&(aux7_2>=1)))||(((aux5_0>=1)&&(aux7_2>=1))&&(c110>=1)))"))))))
Formula 3 simplified : !FG("((((((in1_1>=1)&&(c6>=1))&&(in3_4>=1))||(((in3_5>=1)&&(in1_0>=1))&&(c6>=1)))||(((in1_1>=1)&&(c6>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c6>=1))&&(in3_4>=1)))" U "((((((((((((((((((aux5_5>=1)&&(aux7_7>=1))&&(c110>=1))||(((aux5_1>=1)&&(c110>=1))&&(aux7_7>=1)))||(((aux5_4>=1)&&(aux7_7>=1))&&(c110>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_5>=1)))||(((c110>=1)&&(aux7_7>=1))&&(aux5_0>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_1>=1)))||(((aux7_6>=1)&&(c110>=1))&&(aux5_4>=1)))||(((c110>=1)&&(aux7_3>=1))&&(aux5_5>=1)))||(((c110>=1)&&(aux7_6>=1))&&(aux5_0>=1)))||(((aux5_1>=1)&&(aux7_3>=1))&&(c110>=1)))||(((aux5_4>=1)&&(c110>=1))&&(aux7_3>=1)))||(((aux5_0>=1)&&(aux7_3>=1))&&(c110>=1)))||(((aux5_5>=1)&&(c110>=1))&&(aux7_2>=1)))||(((c110>=1)&&(aux7_2>=1))&&(aux5_4>=1)))||(((aux5_1>=1)&&(c110>=1))&&(aux7_2>=1)))||(((aux5_0>=1)&&(aux7_2>=1))&&(c110>=1)))")
Computing Next relation with stutter on 18688 deadlock states
15 unique states visited
15 strongly connected components in search stack
15 transitions explored
15 items max in DFS search stack
71 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,86.189,1770252,1,0,1183,3.66362e+06,1186,566,18702,1.08016e+06,1356
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 4 : !((F((G("((((((c7>=1)&&(in2_3>=1))&&(in4_6>=1))||(((in4_7>=1)&&(c7>=1))&&(in2_2>=1)))||(((c7>=1)&&(in2_3>=1))&&(in4_7>=1)))||(((in4_6>=1)&&(in2_2>=1))&&(c7>=1)))"))U(X(F("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c13>=1)&&(aux11_1>=1))&&(aux9_0>=1))||(((aux9_0>=1)&&(c13>=1))&&(aux11_2>=1)))||(((aux11_3>=1)&&(c13>=1))&&(aux9_0>=1)))||(((aux11_4>=1)&&(c13>=1))&&(aux9_0>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_0>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_3>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_5>=1)))||(((aux11_1>=1)&&(c13>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_7>=1))&&(aux9_4>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_0>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux9_4>=1)&&(c13>=1))&&(aux11_6>=1)))||(((aux11_3>=1)&&(aux9_6>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_6>=1)))||(((c13>=1)&&(aux9_6>=1))&&(aux11_1>=1)))||(((c13>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((c13>=1)&&(aux9_5>=1))&&(aux11_7>=1)))||(((aux9_6>=1)&&(aux11_0>=1))&&(c13>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_5>=1)))||(((aux9_5>=1)&&(aux11_6>=1))&&(c13>=1)))||(((aux11_4>=1)&&(c13>=1))&&(aux9_7>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(c13>=1))&&(aux11_2>=1)))||(((c13>=1)&&(aux11_1>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c13>=1)))||(((aux9_6>=1)&&(aux11_7>=1))&&(c13>=1)))||(((aux9_6>=1)&&(aux11_6>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_5>=1))&&(aux9_6>=1)))||(((aux9_7>=1)&&(c13>=1))&&(aux11_7>=1)))||(((c13>=1)&&(aux11_6>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux9_1>=1)&&(c13>=1))&&(aux11_1>=1)))||(((aux11_2>=1)&&(aux9_1>=1))&&(c13>=1)))||(((aux9_1>=1)&&(aux11_3>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((aux9_0>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux11_6>=1)&&(c13>=1))&&(aux9_0>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c13>=1)))||(((aux9_1>=1)&&(c13>=1))&&(aux11_0>=1)))||(((c13>=1)&&(aux9_2>=1))&&(aux11_1>=1)))||(((aux9_2>=1)&&(aux11_2>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(c13>=1))&&(aux11_4>=1)))||(((aux11_5>=1)&&(aux9_1>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_6>=1))&&(aux9_1>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c13>=1)))||(((aux9_2>=1)&&(aux11_0>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_2>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_1>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_3>=1)))||(((aux11_6>=1)&&(c13>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(c13>=1))&&(aux11_5>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_3>=1)))||(((aux11_7>=1)&&(c13>=1))&&(aux9_2>=1)))||(((c13>=1)&&(aux11_2>=1))&&(aux9_4>=1)))||(((aux11_1>=1)&&(aux9_4>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(aux11_3>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_3>=1))&&(aux11_6>=1)))||(((c13>=1)&&(aux11_5>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_4>=1)))||(((c13>=1)&&(aux9_3>=1))&&(aux11_7>=1)))"))))))
Formula 4 simplified : !F(G"((((((c7>=1)&&(in2_3>=1))&&(in4_6>=1))||(((in4_7>=1)&&(c7>=1))&&(in2_2>=1)))||(((c7>=1)&&(in2_3>=1))&&(in4_7>=1)))||(((in4_6>=1)&&(in2_2>=1))&&(c7>=1)))" U XF"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c13>=1)&&(aux11_1>=1))&&(aux9_0>=1))||(((aux9_0>=1)&&(c13>=1))&&(aux11_2>=1)))||(((aux11_3>=1)&&(c13>=1))&&(aux9_0>=1)))||(((aux11_4>=1)&&(c13>=1))&&(aux9_0>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_0>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_3>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_5>=1)))||(((aux11_1>=1)&&(c13>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_7>=1))&&(aux9_4>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_0>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux9_4>=1)&&(c13>=1))&&(aux11_6>=1)))||(((aux11_3>=1)&&(aux9_6>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_6>=1)))||(((c13>=1)&&(aux9_6>=1))&&(aux11_1>=1)))||(((c13>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((c13>=1)&&(aux9_5>=1))&&(aux11_7>=1)))||(((aux9_6>=1)&&(aux11_0>=1))&&(c13>=1)))||(((aux9_5>=1)&&(c13>=1))&&(aux11_5>=1)))||(((aux9_5>=1)&&(aux11_6>=1))&&(c13>=1)))||(((aux11_4>=1)&&(c13>=1))&&(aux9_7>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(c13>=1))&&(aux11_2>=1)))||(((c13>=1)&&(aux11_1>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c13>=1)))||(((aux9_6>=1)&&(aux11_7>=1))&&(c13>=1)))||(((aux9_6>=1)&&(aux11_6>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_5>=1))&&(aux9_6>=1)))||(((aux9_7>=1)&&(c13>=1))&&(aux11_7>=1)))||(((c13>=1)&&(aux11_6>=1))&&(aux9_7>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux9_1>=1)&&(c13>=1))&&(aux11_1>=1)))||(((aux11_2>=1)&&(aux9_1>=1))&&(c13>=1)))||(((aux9_1>=1)&&(aux11_3>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((aux9_0>=1)&&(aux11_5>=1))&&(c13>=1)))||(((aux11_6>=1)&&(c13>=1))&&(aux9_0>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c13>=1)))||(((aux9_1>=1)&&(c13>=1))&&(aux11_0>=1)))||(((c13>=1)&&(aux9_2>=1))&&(aux11_1>=1)))||(((aux9_2>=1)&&(aux11_2>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(c13>=1))&&(aux11_4>=1)))||(((aux11_5>=1)&&(aux9_1>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_6>=1))&&(aux9_1>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c13>=1)))||(((aux9_2>=1)&&(aux11_0>=1))&&(c13>=1)))||(((c13>=1)&&(aux11_2>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_1>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_4>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_3>=1))&&(aux9_3>=1)))||(((aux11_6>=1)&&(c13>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(c13>=1))&&(aux11_5>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_3>=1)))||(((aux11_7>=1)&&(c13>=1))&&(aux9_2>=1)))||(((c13>=1)&&(aux11_2>=1))&&(aux9_4>=1)))||(((aux11_1>=1)&&(aux9_4>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(aux11_3>=1))&&(c13>=1)))||(((c13>=1)&&(aux9_3>=1))&&(aux11_6>=1)))||(((c13>=1)&&(aux11_5>=1))&&(aux9_3>=1)))||(((c13>=1)&&(aux11_0>=1))&&(aux9_4>=1)))||(((c13>=1)&&(aux9_3>=1))&&(aux11_7>=1)))")
Computing Next relation with stutter on 18688 deadlock states
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
61 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,86.7984,1785208,1,0,1207,3.67097e+06,1195,586,18849,1.09564e+06,1424
no accepting run found
Formula 4 is TRUE no accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 5 : !((G(F(X(G(F("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c14>=1)&&(aux11_4>=1))&&(aux9_0>=1))||(((aux11_3>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_2>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_0>=1))&&(aux11_0>=1)))||(((aux11_7>=1)&&(aux9_4>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_6>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_5>=1))&&(aux11_3>=1)))||(((aux9_5>=1)&&(aux11_4>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux11_7>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(c14>=1))&&(aux11_6>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_4>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_7>=1))&&(aux9_6>=1)))||(((aux11_6>=1)&&(aux9_6>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_6>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux11_5>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_6>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_1>=1))&&(aux9_1>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_2>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_6>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_2>=1))&&(c14>=1)))||(((aux11_1>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux11_2>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(aux11_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_6>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_0>=1)))||(((aux9_2>=1)&&(aux11_7>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_1>=1))&&(c14>=1)))||(((aux11_4>=1)&&(aux9_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_3>=1)))||(((aux9_3>=1)&&(c14>=1))&&(aux11_6>=1)))||(((aux11_5>=1)&&(aux9_3>=1))&&(c14>=1)))||(((aux11_0>=1)&&(c14>=1))&&(aux9_4>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_7>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_2>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_3>=1)))")))))))
Formula 5 simplified : !GFXGF"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c14>=1)&&(aux11_4>=1))&&(aux9_0>=1))||(((aux11_3>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_2>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_0>=1))&&(aux11_0>=1)))||(((aux11_7>=1)&&(aux9_4>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_6>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_5>=1))&&(aux11_3>=1)))||(((aux9_5>=1)&&(aux11_4>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux11_7>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(c14>=1))&&(aux11_6>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_4>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_7>=1))&&(aux9_6>=1)))||(((aux11_6>=1)&&(aux9_6>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_6>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux11_5>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_6>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_1>=1))&&(aux9_1>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_2>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_6>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_2>=1))&&(c14>=1)))||(((aux11_1>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux11_2>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(aux11_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_6>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_0>=1)))||(((aux9_2>=1)&&(aux11_7>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_1>=1))&&(c14>=1)))||(((aux11_4>=1)&&(aux9_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_3>=1)))||(((aux9_3>=1)&&(c14>=1))&&(aux11_6>=1)))||(((aux11_5>=1)&&(aux9_3>=1))&&(c14>=1)))||(((aux11_0>=1)&&(c14>=1))&&(aux9_4>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_7>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_2>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_3>=1)))"
Computing Next relation with stutter on 18688 deadlock states
19 unique states visited
19 strongly connected components in search stack
20 transitions explored
19 items max in DFS search stack
62 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,87.4274,1792600,1,0,1223,3.67216e+06,1204,602,18916,1.09742e+06,1490
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 6 : !((((F("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c16>=1)&&(aux12_3>=1))&&(aux10_0>=1))||(((c16>=1)&&(aux10_0>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_0>=1)))||(((aux12_2>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(c16>=1))&&(aux10_6>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_5>=1)))||(((aux12_6>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_5>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_3>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_2>=1)))||(((aux12_1>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_5>=1))&&(aux12_0>=1)))||(((aux10_4>=1)&&(aux12_7>=1))&&(c16>=1)))||(((aux12_6>=1)&&(aux10_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_4>=1)))||(((aux12_4>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_2>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_5>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux12_7>=1)&&(aux10_7>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux12_6>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_7>=1)))||(((aux12_0>=1)&&(aux10_7>=1))&&(c16>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_7>=1))&&(aux12_3>=1)))||(((aux10_7>=1)&&(aux12_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_7>=1)))||(((aux10_7>=1)&&(aux12_2>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_6>=1)))||(((aux12_5>=1)&&(aux10_1>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_0>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux12_2>=1)&&(aux10_2>=1))&&(c16>=1)))||(((aux10_2>=1)&&(c16>=1))&&(aux12_1>=1)))||(((aux10_2>=1)&&(aux12_4>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_2>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_5>=1)))||(((c16>=1)&&(aux12_0>=1))&&(aux10_1>=1)))||(((aux12_7>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux10_1>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux10_1>=1))&&(aux12_3>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_6>=1)))||(((aux12_7>=1)&&(aux10_3>=1))&&(c16>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_0>=1)))||(((aux12_1>=1)&&(aux10_4>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_4>=1)))||(((c16>=1)&&(aux10_4>=1))&&(aux12_3>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_2>=1)&&(aux12_5>=1))&&(c16>=1)))||(((aux10_2>=1)&&(aux12_6>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_7>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_0>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_1>=1)))||(((c16>=1)&&(aux12_2>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux12_3>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_4>=1)))"))U(F("((((((((((((((((((aux7_2>=1)&&(c9>=1))&&(aux5_5>=1))||(((c9>=1)&&(aux7_3>=1))&&(aux5_0>=1)))||(((aux7_2>=1)&&(c9>=1))&&(aux5_1>=1)))||(((aux5_4>=1)&&(aux7_2>=1))&&(c9>=1)))||(((aux5_0>=1)&&(c9>=1))&&(aux7_2>=1)))||(((aux5_4>=1)&&(aux7_7>=1))&&(c9>=1)))||(((c9>=1)&&(aux7_7>=1))&&(aux5_1>=1)))||(((aux7_7>=1)&&(c9>=1))&&(aux5_5>=1)))||(((aux5_4>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_1>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_0>=1)&&(c9>=1))&&(aux7_7>=1)))||(((aux5_5>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_4>=1)&&(aux7_3>=1))&&(c9>=1)))||(((c9>=1)&&(aux7_3>=1))&&(aux5_1>=1)))||(((aux7_6>=1)&&(c9>=1))&&(aux5_0>=1)))||(((aux5_5>=1)&&(aux7_3>=1))&&(c9>=1)))")))U(F(X(G("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c16>=1)&&(aux12_3>=1))&&(aux10_0>=1))||(((c16>=1)&&(aux10_0>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_0>=1)))||(((aux12_2>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(c16>=1))&&(aux10_6>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_5>=1)))||(((aux12_6>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_5>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_3>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_2>=1)))||(((aux12_1>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_5>=1))&&(aux12_0>=1)))||(((aux10_4>=1)&&(aux12_7>=1))&&(c16>=1)))||(((aux12_6>=1)&&(aux10_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_4>=1)))||(((aux12_4>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_2>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_5>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux12_7>=1)&&(aux10_7>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux12_6>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_7>=1)))||(((aux12_0>=1)&&(aux10_7>=1))&&(c16>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_7>=1))&&(aux12_3>=1)))||(((aux10_7>=1)&&(aux12_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_7>=1)))||(((aux10_7>=1)&&(aux12_2>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_6>=1)))||(((aux12_5>=1)&&(aux10_1>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_0>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux12_2>=1)&&(aux10_2>=1))&&(c16>=1)))||(((aux10_2>=1)&&(c16>=1))&&(aux12_1>=1)))||(((aux10_2>=1)&&(aux12_4>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_2>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_5>=1)))||(((c16>=1)&&(aux12_0>=1))&&(aux10_1>=1)))||(((aux12_7>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux10_1>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux10_1>=1))&&(aux12_3>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_6>=1)))||(((aux12_7>=1)&&(aux10_3>=1))&&(c16>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_0>=1)))||(((aux12_1>=1)&&(aux10_4>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_4>=1)))||(((c16>=1)&&(aux10_4>=1))&&(aux12_3>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_2>=1)&&(aux12_5>=1))&&(c16>=1)))||(((aux10_2>=1)&&(aux12_6>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_7>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_0>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_1>=1)))||(((c16>=1)&&(aux12_2>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux12_3>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_4>=1)))"))))))
Formula 6 simplified : !((F"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c16>=1)&&(aux12_3>=1))&&(aux10_0>=1))||(((c16>=1)&&(aux10_0>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_0>=1)))||(((aux12_2>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(c16>=1))&&(aux10_6>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_5>=1)))||(((aux12_6>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_5>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_3>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_2>=1)))||(((aux12_1>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_5>=1))&&(aux12_0>=1)))||(((aux10_4>=1)&&(aux12_7>=1))&&(c16>=1)))||(((aux12_6>=1)&&(aux10_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_4>=1)))||(((aux12_4>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_2>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_5>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux12_7>=1)&&(aux10_7>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux12_6>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_7>=1)))||(((aux12_0>=1)&&(aux10_7>=1))&&(c16>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_7>=1))&&(aux12_3>=1)))||(((aux10_7>=1)&&(aux12_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_7>=1)))||(((aux10_7>=1)&&(aux12_2>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_6>=1)))||(((aux12_5>=1)&&(aux10_1>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_0>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux12_2>=1)&&(aux10_2>=1))&&(c16>=1)))||(((aux10_2>=1)&&(c16>=1))&&(aux12_1>=1)))||(((aux10_2>=1)&&(aux12_4>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_2>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_5>=1)))||(((c16>=1)&&(aux12_0>=1))&&(aux10_1>=1)))||(((aux12_7>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux10_1>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux10_1>=1))&&(aux12_3>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_6>=1)))||(((aux12_7>=1)&&(aux10_3>=1))&&(c16>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_0>=1)))||(((aux12_1>=1)&&(aux10_4>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_4>=1)))||(((c16>=1)&&(aux10_4>=1))&&(aux12_3>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_2>=1)&&(aux12_5>=1))&&(c16>=1)))||(((aux10_2>=1)&&(aux12_6>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_7>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_0>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_1>=1)))||(((c16>=1)&&(aux12_2>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux12_3>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_4>=1)))" U F"((((((((((((((((((aux7_2>=1)&&(c9>=1))&&(aux5_5>=1))||(((c9>=1)&&(aux7_3>=1))&&(aux5_0>=1)))||(((aux7_2>=1)&&(c9>=1))&&(aux5_1>=1)))||(((aux5_4>=1)&&(aux7_2>=1))&&(c9>=1)))||(((aux5_0>=1)&&(c9>=1))&&(aux7_2>=1)))||(((aux5_4>=1)&&(aux7_7>=1))&&(c9>=1)))||(((c9>=1)&&(aux7_7>=1))&&(aux5_1>=1)))||(((aux7_7>=1)&&(c9>=1))&&(aux5_5>=1)))||(((aux5_4>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_1>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_0>=1)&&(c9>=1))&&(aux7_7>=1)))||(((aux5_5>=1)&&(c9>=1))&&(aux7_6>=1)))||(((aux5_4>=1)&&(aux7_3>=1))&&(c9>=1)))||(((c9>=1)&&(aux7_3>=1))&&(aux5_1>=1)))||(((aux7_6>=1)&&(c9>=1))&&(aux5_0>=1)))||(((aux5_5>=1)&&(aux7_3>=1))&&(c9>=1)))") U FXG"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c16>=1)&&(aux12_3>=1))&&(aux10_0>=1))||(((c16>=1)&&(aux10_0>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_0>=1)))||(((aux12_2>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_0>=1)&&(c16>=1))&&(aux10_6>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_5>=1)))||(((aux12_6>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_5>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_3>=1)))||(((aux10_6>=1)&&(c16>=1))&&(aux12_2>=1)))||(((aux12_1>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_5>=1))&&(aux12_0>=1)))||(((aux10_4>=1)&&(aux12_7>=1))&&(c16>=1)))||(((aux12_6>=1)&&(aux10_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_4>=1)))||(((aux12_4>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux12_2>=1)&&(aux10_5>=1))&&(c16>=1)))||(((aux10_5>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux12_7>=1)&&(aux10_7>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_5>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux12_6>=1))&&(aux10_7>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_7>=1)))||(((aux12_0>=1)&&(aux10_7>=1))&&(c16>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_6>=1)))||(((c16>=1)&&(aux10_6>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_7>=1))&&(aux12_3>=1)))||(((aux10_7>=1)&&(aux12_4>=1))&&(c16>=1)))||(((c16>=1)&&(aux12_1>=1))&&(aux10_7>=1)))||(((aux10_7>=1)&&(aux12_2>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_6>=1)))||(((aux12_5>=1)&&(aux10_1>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_0>=1)))||(((aux12_7>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux12_2>=1)&&(aux10_2>=1))&&(c16>=1)))||(((aux10_2>=1)&&(c16>=1))&&(aux12_1>=1)))||(((aux10_2>=1)&&(aux12_4>=1))&&(c16>=1)))||(((aux12_3>=1)&&(aux10_2>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_6>=1)))||(((c16>=1)&&(aux10_0>=1))&&(aux12_5>=1)))||(((c16>=1)&&(aux12_0>=1))&&(aux10_1>=1)))||(((aux12_7>=1)&&(aux10_0>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_1>=1)))||(((aux10_1>=1)&&(aux12_1>=1))&&(c16>=1)))||(((aux10_1>=1)&&(c16>=1))&&(aux12_4>=1)))||(((c16>=1)&&(aux10_1>=1))&&(aux12_3>=1)))||(((aux12_5>=1)&&(c16>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_6>=1)))||(((aux12_7>=1)&&(aux10_3>=1))&&(c16>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_0>=1)))||(((aux12_1>=1)&&(aux10_4>=1))&&(c16>=1)))||(((aux12_2>=1)&&(c16>=1))&&(aux10_4>=1)))||(((c16>=1)&&(aux10_4>=1))&&(aux12_3>=1)))||(((aux10_4>=1)&&(c16>=1))&&(aux12_4>=1)))||(((aux10_2>=1)&&(aux12_5>=1))&&(c16>=1)))||(((aux10_2>=1)&&(aux12_6>=1))&&(c16>=1)))||(((c16>=1)&&(aux10_2>=1))&&(aux12_7>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_0>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_1>=1)))||(((c16>=1)&&(aux12_2>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux12_3>=1))&&(aux10_3>=1)))||(((c16>=1)&&(aux10_3>=1))&&(aux12_4>=1)))")
Computing Next relation with stutter on 18688 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1159 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,99.0165,1860432,1,0,1262,3.75271e+06,1217,654,19127,1.22806e+06,1687
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 7 : !(((("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c20>=1)&&(aux14_0>=1))&&(aux16_0>=1))||(((aux16_4>=1)&&(c20>=1))&&(aux14_0>=1)))||(((aux16_3>=1)&&(aux14_0>=1))&&(c20>=1)))||(((aux14_0>=1)&&(c20>=1))&&(aux16_2>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_0>=1)))||(((aux14_1>=1)&&(aux16_7>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_2>=1))&&(aux16_0>=1)))||(((aux14_1>=1)&&(aux16_5>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_1>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux16_3>=1))&&(aux14_2>=1)))||(((c20>=1)&&(aux14_2>=1))&&(aux16_4>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_2>=1)))||(((aux14_2>=1)&&(c20>=1))&&(aux16_2>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_7>=1)))||(((aux16_0>=1)&&(aux14_1>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_5>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_6>=1)))||(((aux14_1>=1)&&(aux16_3>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_1>=1))&&(aux16_4>=1)))||(((aux16_1>=1)&&(aux14_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(aux14_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(c20>=1))&&(aux14_4>=1)))||(((aux14_4>=1)&&(aux16_1>=1))&&(c20>=1)))||(((aux16_4>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux14_4>=1)&&(aux16_3>=1))&&(c20>=1)))||(((aux14_3>=1)&&(c20>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux14_3>=1))&&(aux16_5>=1)))||(((aux16_0>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_7>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_2>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_1>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_3>=1)))||(((aux14_3>=1)&&(aux16_3>=1))&&(c20>=1)))||(((aux16_6>=1)&&(c20>=1))&&(aux14_2>=1)))||(((aux14_2>=1)&&(aux16_5>=1))&&(c20>=1)))||(((aux14_3>=1)&&(c20>=1))&&(aux16_0>=1)))||(((aux14_2>=1)&&(aux16_7>=1))&&(c20>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_6>=1)))||(((aux14_6>=1)&&(c20>=1))&&(aux16_2>=1)))||(((aux16_3>=1)&&(aux14_6>=1))&&(c20>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux16_5>=1)&&(aux14_5>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_5>=1))&&(aux16_6>=1)))||(((aux14_5>=1)&&(aux16_7>=1))&&(c20>=1)))||(((aux16_0>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux14_5>=1)&&(aux16_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(c20>=1))&&(aux14_5>=1)))||(((aux16_3>=1)&&(aux14_5>=1))&&(c20>=1)))||(((aux16_4>=1)&&(aux14_5>=1))&&(c20>=1)))||(((aux16_5>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_6>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_7>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_0>=1)&&(c20>=1))&&(aux14_5>=1)))||(((aux16_7>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux14_7>=1)&&(c20>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux14_7>=1))&&(aux16_5>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_7>=1)))||(((c20>=1)&&(aux14_7>=1))&&(aux16_3>=1)))||(((aux16_2>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux16_1>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux14_7>=1)&&(c20>=1))&&(aux16_0>=1)))||(((aux14_6>=1)&&(aux16_7>=1))&&(c20>=1)))||(((aux16_6>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux14_6>=1)&&(aux16_5>=1))&&(c20>=1)))")U("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((aux13_1>=1)&&(c17>=1))&&(aux15_2>=1))||(((aux13_1>=1)&&(c17>=1))&&(aux15_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_4>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_6>=1)))||(((aux15_5>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_1>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_7>=1)))||(((aux15_2>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_1>=1)&&(aux13_2>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_4>=1)))||(((aux15_3>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_0>=1)))||(((c17>=1)&&(aux13_1>=1))&&(aux15_7>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_0>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_2>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_0>=1)))||(((aux15_4>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux13_0>=1)&&(c17>=1))&&(aux15_0>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_0>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_5>=1)))||(((aux15_6>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_6>=1)))||(((aux15_4>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_6>=1)))||(((c17>=1)&&(aux13_6>=1))&&(aux15_2>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_4>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_0>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_6>=1)))||(((aux15_3>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_4>=1)&&(c17>=1))&&(aux13_5>=1)))||(((aux15_1>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_2>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_4>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_5>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_4>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_2>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_1>=1)))||(((aux15_0>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_2>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_5>=1)&&(c17>=1))&&(aux13_2>=1)))||(((aux15_4>=1)&&(aux13_3>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_3>=1)))||(((aux15_2>=1)&&(c17>=1))&&(aux13_3>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_1>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_6>=1)))||(((aux13_7>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_5>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_0>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_7>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_2>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_7>=1)))||(((aux15_4>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_7>=1)))"))U("((((((((((((((((((c12>=1)&&(aux8_7>=1))&&(aux6_1>=1))||(((aux8_7>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux8_7>=1)&&(c12>=1))&&(aux6_5>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_1>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(c12>=1))&&(aux8_3>=1)))||(((c12>=1)&&(aux8_6>=1))&&(aux6_0>=1)))||(((aux6_1>=1)&&(aux8_6>=1))&&(c12>=1)))||(((aux8_6>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(aux8_6>=1))&&(c12>=1)))||(((c12>=1)&&(aux8_7>=1))&&(aux6_0>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_2>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c12>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_1>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_3>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_5>=1)))")))
Formula 7 simplified : !(("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c20>=1)&&(aux14_0>=1))&&(aux16_0>=1))||(((aux16_4>=1)&&(c20>=1))&&(aux14_0>=1)))||(((aux16_3>=1)&&(aux14_0>=1))&&(c20>=1)))||(((aux14_0>=1)&&(c20>=1))&&(aux16_2>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_0>=1)))||(((aux14_1>=1)&&(aux16_7>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_2>=1))&&(aux16_0>=1)))||(((aux14_1>=1)&&(aux16_5>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_1>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux16_3>=1))&&(aux14_2>=1)))||(((c20>=1)&&(aux14_2>=1))&&(aux16_4>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_2>=1)))||(((aux14_2>=1)&&(c20>=1))&&(aux16_2>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_7>=1)))||(((aux16_0>=1)&&(aux14_1>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_5>=1)))||(((c20>=1)&&(aux14_0>=1))&&(aux16_6>=1)))||(((aux14_1>=1)&&(aux16_3>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_1>=1))&&(aux16_4>=1)))||(((aux16_1>=1)&&(aux14_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(aux14_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(c20>=1))&&(aux14_4>=1)))||(((aux14_4>=1)&&(aux16_1>=1))&&(c20>=1)))||(((aux16_4>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux14_4>=1)&&(aux16_3>=1))&&(c20>=1)))||(((aux14_3>=1)&&(c20>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux14_3>=1))&&(aux16_5>=1)))||(((aux16_0>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_7>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_2>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_1>=1)&&(aux14_3>=1))&&(c20>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_3>=1)))||(((aux14_3>=1)&&(aux16_3>=1))&&(c20>=1)))||(((aux16_6>=1)&&(c20>=1))&&(aux14_2>=1)))||(((aux14_2>=1)&&(aux16_5>=1))&&(c20>=1)))||(((aux14_3>=1)&&(c20>=1))&&(aux16_0>=1)))||(((aux14_2>=1)&&(aux16_7>=1))&&(c20>=1)))||(((c20>=1)&&(aux16_1>=1))&&(aux14_6>=1)))||(((aux14_6>=1)&&(c20>=1))&&(aux16_2>=1)))||(((aux16_3>=1)&&(aux14_6>=1))&&(c20>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux16_5>=1)&&(aux14_5>=1))&&(c20>=1)))||(((c20>=1)&&(aux14_5>=1))&&(aux16_6>=1)))||(((aux14_5>=1)&&(aux16_7>=1))&&(c20>=1)))||(((aux16_0>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux14_5>=1)&&(aux16_1>=1))&&(c20>=1)))||(((aux16_2>=1)&&(c20>=1))&&(aux14_5>=1)))||(((aux16_3>=1)&&(aux14_5>=1))&&(c20>=1)))||(((aux16_4>=1)&&(aux14_5>=1))&&(c20>=1)))||(((aux16_5>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_6>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_7>=1)&&(aux14_4>=1))&&(c20>=1)))||(((aux16_0>=1)&&(c20>=1))&&(aux14_5>=1)))||(((aux16_7>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux14_7>=1)&&(c20>=1))&&(aux16_6>=1)))||(((c20>=1)&&(aux14_7>=1))&&(aux16_5>=1)))||(((aux16_4>=1)&&(c20>=1))&&(aux14_7>=1)))||(((c20>=1)&&(aux14_7>=1))&&(aux16_3>=1)))||(((aux16_2>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux16_1>=1)&&(aux14_7>=1))&&(c20>=1)))||(((aux14_7>=1)&&(c20>=1))&&(aux16_0>=1)))||(((aux14_6>=1)&&(aux16_7>=1))&&(c20>=1)))||(((aux16_6>=1)&&(c20>=1))&&(aux14_6>=1)))||(((aux14_6>=1)&&(aux16_5>=1))&&(c20>=1)))" U "((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((aux13_1>=1)&&(c17>=1))&&(aux15_2>=1))||(((aux13_1>=1)&&(c17>=1))&&(aux15_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_4>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_6>=1)))||(((aux15_5>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_1>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_7>=1)))||(((aux15_2>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_1>=1)&&(aux13_2>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_4>=1)))||(((aux15_3>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_0>=1)))||(((c17>=1)&&(aux13_1>=1))&&(aux15_7>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_0>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_2>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_0>=1)))||(((aux15_4>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux13_0>=1)&&(c17>=1))&&(aux15_0>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_0>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_5>=1)))||(((aux15_6>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_6>=1)))||(((aux15_4>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_6>=1)))||(((c17>=1)&&(aux13_6>=1))&&(aux15_2>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_4>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_0>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_6>=1)))||(((aux15_3>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_4>=1)&&(c17>=1))&&(aux13_5>=1)))||(((aux15_1>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_2>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_4>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_5>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_4>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_2>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_1>=1)))||(((aux15_0>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_2>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_5>=1)&&(c17>=1))&&(aux13_2>=1)))||(((aux15_4>=1)&&(aux13_3>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_3>=1)))||(((aux15_2>=1)&&(c17>=1))&&(aux13_3>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_1>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_6>=1)))||(((aux13_7>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_5>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_0>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_7>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_2>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_7>=1)))||(((aux15_4>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_7>=1)))") U "((((((((((((((((((c12>=1)&&(aux8_7>=1))&&(aux6_1>=1))||(((aux8_7>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux8_7>=1)&&(c12>=1))&&(aux6_5>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_1>=1)))||(((c12>=1)&&(aux8_3>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(c12>=1))&&(aux8_3>=1)))||(((c12>=1)&&(aux8_6>=1))&&(aux6_0>=1)))||(((aux6_1>=1)&&(aux8_6>=1))&&(c12>=1)))||(((aux8_6>=1)&&(c12>=1))&&(aux6_4>=1)))||(((aux6_5>=1)&&(aux8_6>=1))&&(c12>=1)))||(((c12>=1)&&(aux8_7>=1))&&(aux6_0>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_2>=1)))||(((aux6_4>=1)&&(aux8_2>=1))&&(c12>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_1>=1)))||(((aux6_0>=1)&&(c12>=1))&&(aux8_3>=1)))||(((aux8_2>=1)&&(c12>=1))&&(aux6_5>=1)))")
Computing Next relation with stutter on 18688 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
13 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,99.1456,1860984,1,0,1262,3.75271e+06,1237,654,19390,1.2281e+06,1694
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 8 : !((F(F("(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1))"))))
Formula 8 simplified : !F"(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1))"
Computing Next relation with stutter on 18688 deadlock states
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
62 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,99.7744,1861248,1,0,1312,3.75753e+06,1246,709,19390,1.2366e+06,1847
an accepting run exists (use option '-e' to print it)
Formula 8 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 9 : !(("(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1))"))
Formula 9 simplified : !"(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1))"
Computing Next relation with stutter on 18688 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,99.7754,1861248,1,0,1312,3.75753e+06,1249,709,19390,1.2366e+06,1849
an accepting run exists (use option '-e' to print it)
Formula 9 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 10 : !((F(X(X(X("(((aux10_0>=1)&&(aux12_4>=1))&&(c15>=1))"))))))
Formula 10 simplified : !FXXX"(((aux10_0>=1)&&(aux12_4>=1))&&(c15>=1))"
Computing Next relation with stutter on 18688 deadlock states
5 unique states visited
5 strongly connected components in search stack
5 transitions explored
5 items max in DFS search stack
108 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,100.849,1882364,1,0,1356,3.76368e+06,1258,753,19393,1.24434e+06,1975
an accepting run exists (use option '-e' to print it)
Formula 10 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 11 : !((F((F(X("(((aux16_0>=1)&&(aux14_3>=1))&&(c19>=1))")))U("(((c13>=1)&&(aux11_0>=1))&&(aux9_3>=1))"))))
Formula 11 simplified : !F(FX"(((aux16_0>=1)&&(aux14_3>=1))&&(c19>=1))" U "(((c13>=1)&&(aux11_0>=1))&&(aux9_3>=1))")
Computing Next relation with stutter on 18688 deadlock states
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
104 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,101.897,1912724,1,0,1399,3.77084e+06,1267,793,19393,1.25215e+06,2107
an accepting run exists (use option '-e' to print it)
Formula 11 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 12 : !(("(((aux9_2>=1)&&(c13>=1))&&(aux11_5>=1))"))
Formula 12 simplified : !"(((aux9_2>=1)&&(c13>=1))&&(aux11_5>=1))"
Computing Next relation with stutter on 18688 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,101.898,1912724,1,0,1399,3.77084e+06,1270,793,19393,1.25215e+06,2109
an accepting run exists (use option '-e' to print it)
Formula 12 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 13 : !((X(G(F(X("(((aux14_6>=1)&&(aux16_7>=1))&&(c20>=1))"))))))
Formula 13 simplified : !XGFX"(((aux14_6>=1)&&(aux16_7>=1))&&(c20>=1))"
Computing Next relation with stutter on 18688 deadlock states
19 unique states visited
19 strongly connected components in search stack
20 transitions explored
19 items max in DFS search stack
4 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,101.931,1913244,1,0,1399,3.77084e+06,1279,793,19393,1.25224e+06,2115
an accepting run exists (use option '-e' to print it)
Formula 13 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 14 : !((F((X("(((c110>=1)&&(aux7_7>=1))&&(aux5_0>=1))"))U("(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1))"))))
Formula 14 simplified : !F(X"(((c110>=1)&&(aux7_7>=1))&&(aux5_0>=1))" U "(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1))")
Computing Next relation with stutter on 18688 deadlock states
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
63 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,102.56,1926444,1,0,1440,3.77486e+06,1288,831,19393,1.25612e+06,2244
an accepting run exists (use option '-e' to print it)
Formula 14 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 15 : !((G(F(G(("(((aux11_4>=1)&&(c13>=1))&&(aux9_7>=1))")U("(((aux14_2>=1)&&(c19>=1))&&(aux16_6>=1))"))))))
Formula 15 simplified : !GFG("(((aux11_4>=1)&&(c13>=1))&&(aux9_7>=1))" U "(((aux14_2>=1)&&(c19>=1))&&(aux16_6>=1))")
Computing Next relation with stutter on 18688 deadlock states
17 unique states visited
17 strongly connected components in search stack
17 transitions explored
17 items max in DFS search stack
209 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,104.664,1984484,1,0,1475,3.79802e+06,1304,869,19406,1.29106e+06,2414
an accepting run exists (use option '-e' to print it)
Formula 15 is FALSE accepting run found.
FORMULA PermAdmissibility-PT-01-LTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527488129931
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 6:13:38 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 6:13:38 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 6:13:38 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 146 ms
May 28, 2018 6:13:38 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
May 28, 2018 6:13:38 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
May 28, 2018 6:13:38 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 37 ms
May 28, 2018 6:13:38 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 184 ms
May 28, 2018 6:13:38 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 10 ms
May 28, 2018 6:13:38 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 10 ms
May 28, 2018 6:13:39 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 592 transitions.
May 28, 2018 6:13:39 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 32 place invariants in 107 ms
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 1426 ms
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 592 transitions.
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/592 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 102 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 592 transitions.
May 28, 2018 6:13:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 39 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:14:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 592 transitions.
May 28, 2018 6:14:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/592) took 2026 ms. Total solver calls (SAT/UNSAT): 523(523/0)
May 28, 2018 6:14:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/592) took 6347 ms. Total solver calls (SAT/UNSAT): 1414(1288/126)
May 28, 2018 6:14:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/592) took 22749 ms. Total solver calls (SAT/UNSAT): 2386(1936/450)
SMT solver raised 'unknown', retrying with same input.
May 28, 2018 6:14:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/592) took 45118 ms. Total solver calls (SAT/UNSAT): 2970(2488/482)
May 28, 2018 6:14:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/592) took 51229 ms. Total solver calls (SAT/UNSAT): 3555(2755/800)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 28, 2018 6:15:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/592) took 60635 ms. Total solver calls (SAT/UNSAT): 3810(3010/800)
May 28, 2018 6:15:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 60661 ms. Total solver calls (SAT/UNSAT): 3810(3010/800)
May 28, 2018 6:15:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 592 transitions.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 28, 2018 6:15:29 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 110586ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-01"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-01.tgz
mv PermAdmissibility-PT-01 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-PT-01, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585300136"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;