About the Execution of ITS-Tools for ParamProductionCell-PT-5
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15755.770 | 239700.00 | 611024.00 | 240.90 | TFFFFFTFFTTTFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
..............................................
/home/mcc/execution
total 348K
-rw-r--r-- 1 mcc users 5.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.8K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.6K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 115 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 353 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 167K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ParamProductionCell-PT-5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585300110
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-00
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-01
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-02
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-03
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-04
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-05
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-06
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-07
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-08
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-09
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-10
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-11
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-12
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-13
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-14
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1527487389712
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F((("((crane_stop_v>=1)&&(CL_loaded>=1))")U("(((A1L_rot1_run>=1)&&(arm1_release_angle>=1))&&(robot_left>=1))"))U("(((A2L_ext_run>=1)&&(arm2_retract_ext>=1))&&(arm2_forward>=1))"))))
Formula 0 simplified : !F(("((crane_stop_v>=1)&&(CL_loaded>=1))" U "(((A1L_rot1_run>=1)&&(arm1_release_angle>=1))&&(robot_left>=1))") U "(((A2L_ext_run>=1)&&(arm2_retract_ext>=1))&&(arm2_forward>=1))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 202 rows 231 cols
invariant :table_bottom_pos + table_top_pos = 1
invariant :arm1_storing + arm1_having_swivel_1 + arm1_waiting_for_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_ext_rs + A1U_ext_run = 1
invariant :ch_A1P_full + ch_A1P_free + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run + -1'arm1_storing + -1'arm1_having_swivel_1 + -1'A1L_out + -1'A1L_loaded + -1'arm1_magnet_off + -1'A1L_ret_rs + -1'A1L_ret_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :table_upward + -1'TL_lower_rs + -1'TL_lower_run + -1'TU_lift_rs + -1'TU_lift_run = 0
invariant :table_stop_v + TL_lower_rs + TL_lower_run + TU_lift_rs + TU_lift_run = 1
invariant :arm2_release_ext + arm2_retract_ext + arm2_pick_up_ext = 1
invariant :crane_store_free + crane_mag_on + CU_unloaded + CU_ready_to_transport + CU_out + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CL_in + CL_ready_to_grasp + CL_lower_rs + CL_lower_run = 1
invariant :crane_transport_height + crane_release_height + crane_pick_up_height = 1
invariant :press_at_upper_pos + press_at_lower_pos + press_at_middle_pos = 1
invariant :crane_mag_off + crane_mag_on = 1
invariant :belt1_stop + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm2_stop + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run = 1
invariant :belt2_stop + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :robot_right + -1'A2U_rot1_rs + -1'A2U_rot1_run + -1'A2U_rot3_rs + -1'A2U_rot3_run + -1'A1U_rot1_rs + -1'A1U_rot1_run + -1'A1U_rot2_rs + -1'A1U_rot2_run = 0
invariant :arm2_store_free + arm2_waiting_for_swivel_1 + arm2_having_swivel_2 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + A2L_rotated + A2L_in + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_ext_rs + A2L_ext_run = 1
invariant :arm1_magnet_on + arm1_magnet_off = 1
invariant :deposit_belt_idle + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :ch_CF_free + ch_CF_full + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run + CU_unloaded + CU_ready_to_transport + CU_out + CU_ready_to_ungrasp + CU_in + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CU_lower_rs + CU_lower_run = 1
invariant :press_up + -1'PL_lower_rs + -1'PL_lower_run = 0
invariant :ch_A2D_full + ch_A2D_free + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run + -1'arm2_storing + -1'arm2_having_swivel_1 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + -1'A2L_out + -1'A2L_loaded + -1'A2L_ret_rs + -1'A2L_ret_run = 1
invariant :belt2_start + -1'DB_trans_rs + -1'DB_trans_run + -1'DB_deliver_rs + -1'DB_deliver_run = 0
invariant :ch_DC_full + ch_CF_full + -1'ch_A1P_free + -1'ch_TA1_free + -1'ch_A2D_free + ch_FT_full + ch_PA2_full + -1'press_ready_for_unloading + -1'PL_in + -1'PL_out + -1'PL_lower_rs + -1'PL_lower_run + table_ready_for_unloading + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run + -1'deposit_belt_empty + feed_belt_occupied + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run + -1'arm2_store_free + arm2_storing + -1'arm2_having_swivel_2 + arm2_having_swivel_1 + -1'A2U_out + -1'A2U_unloaded + -1'arm2_magnet_on + -1'A2U_ret_rs + -1'A2U_ret_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run + arm1_storing + arm1_having_swivel_1 + crane_mag_on + CU_unloaded + CU_ready_to_transport + CU_out + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CL_in + CL_ready_to_grasp + CL_lower_rs + CL_lower_run = 2
invariant :arm1_forward + -1'A1L_ext_rs + -1'A1L_ext_run + -1'A1U_ext_rs + -1'A1U_ext_run = 0
invariant :arm2_forward + -1'A2U_ext_rs + -1'A2U_ext_run + -1'A2L_ext_rs + -1'A2L_ext_run = 0
invariant :press_stop + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_lower_rs + PL_lower_run = 1
invariant :table_right + -1'TL_rot_rs + -1'TL_rot_run + -1'TU_rot_rs + -1'TU_rot_run = 0
invariant :robot_stop + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run = 1
invariant :press_ready_for_loading + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run = 1
invariant :ch_TA1_full + ch_TA1_free + -1'table_ready_for_unloading + -1'arm1_store_free + -1'arm1_having_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + -1'A1U_out + -1'A1U_unloadet + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :crane_to_belt2 + -1'CU_trans_rs + -1'CU_trans_run = 0
invariant :press_down + -1'PU_lower_rs + -1'PU_lower_run = 0
invariant :belt1_start + -1'FB_trans_rs + -1'FB_trans_run + -1'FB_deliver_rs + -1'FB_deliver_run = 0
invariant :arm1_store_free + arm1_waiting_for_swivel_1 + arm1_having_swivel_2 + A1L_rotated + A1L_in + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended + -1'arm1_magnet_off + A1L_ext_rs + A1L_ext_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :table_ready_for_loading + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run = 1
invariant :crane_to_belt1 + -1'CL_trans_rs + -1'CL_trans_run = 0
invariant :crane_stop_h + CU_trans_rs + CU_trans_run + CL_trans_rs + CL_trans_run = 1
invariant :crane_lift + -1'CU_lift_rs + -1'CU_lift_run + -1'CL_lift_rs + -1'CL_lift_run = 0
invariant :robot_left + -1'A2U_rot2_rs + -1'A2U_rot2_run + -1'A2L_rot1_rs + -1'A2L_rot1_run + -1'A2L_rot2_rs + -1'A2L_rot2_run + -1'A2L_rot3_rs + -1'A2L_rot3_run + -1'A1L_rot1_rs + -1'A1L_rot1_run + -1'A1L_rot2_rs + -1'A1L_rot2_run + -1'A1L_rot3_rs + -1'A1L_rot3_run + -1'A1U_rot3_rs + -1'A1U_rot3_run = 0
invariant :arm1_stop + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
invariant :table_stop_h + TL_rot_rs + TL_rot_run + TU_rot_rs + TU_rot_run = 1
invariant :feed_belt_idle + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm2_magnet_off + arm2_magnet_on = 1
invariant :arm2_backward + -1'A2U_ret_rs + -1'A2U_ret_run + -1'A2L_ret_rs + -1'A2L_ret_run = 0
invariant :crane_above_deposit_belt + crane_above_feed_belt = 1
invariant :crane_storing + -1'crane_mag_on + CU_ready_to_ungrasp + CU_in + CU_lower_rs + CU_lower_run + CL_out + CL_ready_to_transport + CL_loaded + CL_trans_rs + CL_trans_run + CL_lift_rs + CL_lift_run = 0
invariant :crane_lower + -1'CU_lower_rs + -1'CU_lower_run + -1'CL_lower_rs + -1'CL_lower_run = 0
invariant :crane_stop_v + CU_lift_rs + CU_lift_run + CU_lower_rs + CU_lower_run + CL_lower_rs + CL_lower_run + CL_lift_rs + CL_lift_run = 1
invariant :swivel + -1'arm2_store_free + -1'arm2_waiting_for_swivel_1 + -1'arm2_storing + -1'arm2_waiting_for_swivel_2 + -1'arm1_store_free + -1'arm1_waiting_for_swivel_1 + -1'arm1_storing + -1'arm1_waiting_for_swivel_2 = -1
invariant :belt2_light_barrier_true + belt2_light_barrier_false = 1
invariant :arm2_storing + arm2_having_swivel_1 + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended + -1'arm2_magnet_on + A2U_ext_rs + A2U_ext_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = 0
invariant :arm2_release_angle + arm1_pick_up_angle + arm1_release_angle + arm2_pick_up_angle = 1
invariant :ch_DC_free + -1'ch_CF_full + ch_A1P_free + ch_TA1_free + ch_A2D_free + -1'ch_FT_full + -1'ch_PA2_full + press_ready_for_unloading + PL_in + PL_out + PL_lower_rs + PL_lower_run + -1'table_ready_for_unloading + -1'TU_in + -1'TU_out + -1'table_at_unload_angle + -1'TU_lift_rs + -1'TU_lift_run + -1'TU_rot_rs + -1'TU_rot_run + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run + -1'feed_belt_occupied + -1'FB_in + -1'FB_at_end + -1'FB_out + -1'FB_trans_rs + -1'FB_trans_run + -1'FB_deliver_rs + -1'FB_deliver_run + arm2_store_free + -1'arm2_storing + arm2_having_swivel_2 + -1'arm2_having_swivel_1 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + -1'A2L_out + -1'A2L_loaded + -1'A2L_ret_rs + -1'A2L_ret_run + -1'arm1_storing + -1'arm1_having_swivel_1 + -1'crane_mag_on + -1'CU_unloaded + -1'CU_ready_to_transport + -1'CU_out + -1'CU_lift_rs + -1'CU_lift_run + -1'CU_trans_rs + -1'CU_trans_run + CL_out + CL_ready_to_transport + CL_loaded + CL_trans_rs + CL_trans_run + CL_lift_rs + CL_lift_run = -1
invariant :ch_FT_free + ch_FT_full + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :ch_PA2_free + ch_PA2_full + -1'press_ready_for_unloading + -1'arm2_store_free + -1'arm2_having_swivel_2 + -1'A2U_out + -1'A2U_unloaded + -1'arm2_magnet_on + -1'A2U_ret_rs + -1'A2U_ret_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = -1
invariant :table_load_angle + table_unload_angle = 1
invariant :arm1_pick_up_ext + arm1_retract_ext + arm1_release_ext = 1
invariant :arm1_backward + -1'A1L_ret_rs + -1'A1L_ret_run + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :belt1_light_barrier_true + belt1_light_barrier_false = 1
invariant :press_upward + -1'forge_rs + -1'forge_run = 0
Reverse transition relation is NOT exact ! Due to transitions PU_lower_Pstart, forge_Pstart, PL_lower_Pstart, TL_rot_Pstart, TL_lower_Pstart, TU_lift_Pstart, TU_rot_Pstart, DB_trans_Pstart, DB_deliver_Pstart, FB_trans_Pstart, FB_deliver_Pstart, arm2_unlock_swivel_1, arm2_unlock_swivel_2, A2U_rot1_Pstop, A2U_rot1_Pstart, A2U_rot2_Pstop, A2U_rot2_Pstart, A2U_rot3_Pstop, A2U_rot3_Pstart, A2U_ext_Pstart, A2U_ret_Pstart, A2L_rot1_Pstop, A2L_rot1_Pstart, A2L_rot2_Pstop, A2L_rot2_Pstart, A2L_rot3_Pstart, A2L_ext_Pstart, A2L_ret_Pstart, arm1_unlock_swivel_1, arm1_unlock_swivel_2, A1L_rot1_Pstop, A1L_rot1_Pstart, A1L_rot2_Pstop, A1L_rot2_Pstart, A1L_rot3_Pstop, A1L_rot3_Pstart, A1L_ext_Pstart, A1L_ret_Pstart, A1U_rot1_Pstart, A1U_rot2_Pstop, A1U_rot2_Pstart, A1U_rot3_Pstop, A1U_rot3_Pstart, A1U_ext_Pstart, A1U_ret_Pstart, CU_lift_Pstart, CU_trans_Pstart, CU_lower_Pstart, CL_lower_Pstart, CL_trans_Pstart, CL_lift_Pstart, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/151/51/202
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
2115 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,21.1812,584424,1,0,1006,2.63689e+06,430,342,7055,2.01559e+06,1771
no accepting run found
Formula 0 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !(((F(X(X("((A1U_rot3_rs>=1)&&(robot_left>=1))"))))U(("(((A1L_rot1_run>=1)&&(arm1_release_angle>=1))&&(robot_left>=1))")U("((A1L_ext_rs>=1)&&(arm1_forward>=1))"))))
Formula 1 simplified : !(FXX"((A1U_rot3_rs>=1)&&(robot_left>=1))" U ("(((A1L_rot1_run>=1)&&(arm1_release_angle>=1))&&(robot_left>=1))" U "((A1L_ext_rs>=1)&&(arm1_forward>=1))"))
105 unique states visited
104 strongly connected components in search stack
105 transitions explored
104 items max in DFS search stack
5027 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,71.4722,1682532,1,0,2305,8.56225e+06,446,966,7067,8.95854e+06,5208
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 2 : !((F(X(G(X(G("((A1L_rot1_in>=1)&&(robot_stop>=1))")))))))
Formula 2 simplified : !FXGXG"((A1L_rot1_in>=1)&&(robot_stop>=1))"
4 unique states visited
3 strongly connected components in search stack
5 transitions explored
4 items max in DFS search stack
345 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,74.927,1741952,1,0,2307,8.60811e+06,453,966,7349,9.027e+06,5223
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 3 : !((X(G("(((A1U_ret_run>=1)&&(arm1_release_ext>=1))&&(arm1_backward>=1))"))))
Formula 3 simplified : !XG"(((A1U_ret_run>=1)&&(arm1_release_ext>=1))&&(arm1_backward>=1))"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,74.9292,1741952,1,0,2307,8.60811e+06,461,966,7355,9.027e+06,5230
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 4 : !((("(((A1U_ext_run>=1)&&(arm1_retract_ext>=1))&&(arm1_forward>=1))")U(X(G(X("((A2U_rot1_rs>=1)&&(robot_right>=1))"))))))
Formula 4 simplified : !("(((A1U_ext_run>=1)&&(arm1_retract_ext>=1))&&(arm1_forward>=1))" U XGX"((A2U_rot1_rs>=1)&&(robot_right>=1))")
5 unique states visited
5 strongly connected components in search stack
5 transitions explored
5 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,74.9442,1742660,1,0,2308,8.60891e+06,470,966,7363,9.02828e+06,5244
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 5 : !(("(((A2L_ret_run>=1)&&(arm2_pick_up_ext>=1))&&(arm2_backward>=1))"))
Formula 5 simplified : !"(((A2L_ret_run>=1)&&(arm2_pick_up_ext>=1))&&(arm2_backward>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,74.9451,1742660,1,0,2308,8.60891e+06,473,966,7368,9.02828e+06,5246
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 6 : !((X(X(F(F("((CU_lift_run>=1)&&(crane_transport_height>=1))"))))))
Formula 6 simplified : !XXF"((CU_lift_run>=1)&&(crane_transport_height>=1))"
3 unique states visited
0 strongly connected components in search stack
2 transitions explored
3 items max in DFS search stack
4101 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,115.954,2212020,1,0,3233,1.13176e+07,17,1221,3384,1.17322e+07,638
no accepting run found
Formula 6 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 7 : !(("((arm1_storing>=1)&&(ch_A1P_free>=1))"))
Formula 7 simplified : !"((arm1_storing>=1)&&(ch_A1P_free>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
105 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,117.004,2212020,1,0,3233,1.13176e+07,28,1221,4421,1.17322e+07,657
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 8 : !(("((CU_trans_rs>=1)&&(crane_to_belt2>=1))"))
Formula 8 simplified : !"((CU_trans_rs>=1)&&(crane_to_belt2>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,117.005,2212020,1,0,3233,1.13176e+07,31,1221,4425,1.17322e+07,659
an accepting run exists (use option '-e' to print it)
Formula 8 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 9 : !((X(X(F(("((arm1_release_angle>=1)&&(A2L_in>=1))")U("((arm2_store_free>=1)&&(ch_PA2_full>=1))"))))))
Formula 9 simplified : !XXF("((arm1_release_angle>=1)&&(A2L_in>=1))" U "((arm2_store_free>=1)&&(ch_PA2_full>=1))")
3 unique states visited
0 strongly connected components in search stack
2 transitions explored
3 items max in DFS search stack
390 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,120.902,2212020,1,0,3233,1.13176e+07,40,1221,4429,1.17322e+07,1923
no accepting run found
Formula 9 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 10 : !((((F("((A1L_rot2_run>=1)&&(arm1_pick_up_angle>=1))"))U(G("((FB_deliver_rs>=1)&&(belt1_start>=1))")))U(F("((DB_trans_rs>=1)&&(belt2_start>=1))"))))
Formula 10 simplified : !((F"((A1L_rot2_run>=1)&&(arm1_pick_up_angle>=1))" U G"((FB_deliver_rs>=1)&&(belt1_start>=1))") U F"((DB_trans_rs>=1)&&(belt2_start>=1))")
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 3212 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 108 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP15==true)))U([]((LTLAP16==true))))U(<>((LTLAP17==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 343 ms.
FORMULA ParamProductionCell-PT-5-LTLFireability-10 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X((<>((LTLAP18==true)))U(<>((LTLAP19==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
1222 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,133.202,2212504,1,0,3233,1.13176e+07,49,1221,4433,1.17322e+07,3991
no accepting run found
Formula 10 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 11 : !((X(X((F("((DB_deliver_rs>=1)&&(belt2_start>=1))"))U(F("((A2L_ret_run>=1)&&(arm2_retract_ext>=1))"))))))
Formula 11 simplified : !XX(F"((DB_deliver_rs>=1)&&(belt2_start>=1))" U F"((A2L_ret_run>=1)&&(arm2_retract_ext>=1))")
LTSmin run took 8670 ms.
FORMULA ParamProductionCell-PT-5-LTLFireability-11 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>(X((LTLAP20==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 61 ms.
FORMULA ParamProductionCell-PT-5-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(((LTLAP17==true))U((LTLAP21==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 59 ms.
FORMULA ParamProductionCell-PT-5-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((LTLAP22==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
3 unique states visited
0 strongly connected components in search stack
2 transitions explored
3 items max in DFS search stack
360 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,136.851,2212504,1,0,3233,1.13176e+07,58,1221,4437,1.17322e+07,5368
no accepting run found
Formula 11 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 12 : !((F(X(F(X("((arm2_pick_up_angle>=1)&&(A2U_in>=1))"))))))
Formula 12 simplified : !FXFX"((arm2_pick_up_angle>=1)&&(A2U_in>=1))"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
2206 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,158.933,2212504,1,0,3233,1.13176e+07,67,1221,4441,1.17322e+07,6782
an accepting run exists (use option '-e' to print it)
Formula 12 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 13 : !((X(("((DB_trans_rs>=1)&&(belt2_start>=1))")U("(((A1L_rot2_run>=1)&&(arm2_pick_up_angle>=1))&&(robot_left>=1))"))))
Formula 13 simplified : !X("((DB_trans_rs>=1)&&(belt2_start>=1))" U "(((A1L_rot2_run>=1)&&(arm2_pick_up_angle>=1))&&(robot_left>=1))")
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,158.941,2212504,1,0,3233,1.13176e+07,75,1221,4451,1.17322e+07,6788
an accepting run exists (use option '-e' to print it)
Formula 13 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 14 : !((F(X("((A2U_ret_run>=1)&&(arm2_retract_ext>=1))"))))
Formula 14 simplified : !FX"((A2U_ret_run>=1)&&(arm2_retract_ext>=1))"
LTSmin run took 41001 ms.
FORMULA ParamProductionCell-PT-5-LTLFireability-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP16==true))U((LTLAP23==true)))U([](<>((LTLAP24==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
2842 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,187.373,2339920,1,0,4355,1.28547e+07,84,1221,4454,1.2303e+07,9366
no accepting run found
Formula 14 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 15 : !((X((("((FB_deliver_rs>=1)&&(belt1_start>=1))")U("((blank_forged>=1)&&(press_stop>=1))"))U(G(F("((A1U_unloadet>=1)&&(arm1_stop>=1))"))))))
Formula 15 simplified : !X(("((FB_deliver_rs>=1)&&(belt1_start>=1))" U "((blank_forged>=1)&&(press_stop>=1))") U GF"((A1U_unloadet>=1)&&(arm1_stop>=1))")
3 unique states visited
0 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
4349 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,230.871,2431120,1,0,4489,1.33916e+07,17,1221,3396,1.27023e+07,1153
no accepting run found
Formula 15 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-LTLFireability-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
ITS tools runner thread asked to quit. Dying gracefully.
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527487629412
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 6:03:11 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 6:03:11 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 6:03:12 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 132 ms
May 28, 2018 6:03:12 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 231 places.
May 28, 2018 6:03:12 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 202 transitions.
May 28, 2018 6:03:12 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 21 ms
May 28, 2018 6:03:12 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 98 ms
May 28, 2018 6:03:12 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 18 ms
May 28, 2018 6:03:12 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
May 28, 2018 6:03:13 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 202 transitions.
May 28, 2018 6:03:13 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 59 place invariants in 85 ms
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 231 variables to be positive in 782 ms
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 202 transitions.
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/202 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 30 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 202 transitions.
May 28, 2018 6:03:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 23 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:03:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 202 transitions.
May 28, 2018 6:03:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/202) took 245 ms. Total solver calls (SAT/UNSAT): 28(13/15)
May 28, 2018 6:03:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/202) took 3726 ms. Total solver calls (SAT/UNSAT): 276(211/65)
May 28, 2018 6:03:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/202) took 6816 ms. Total solver calls (SAT/UNSAT): 416(302/114)
May 28, 2018 6:03:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/202) took 11603 ms. Total solver calls (SAT/UNSAT): 593(474/119)
May 28, 2018 6:03:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/202) took 16244 ms. Total solver calls (SAT/UNSAT): 766(646/120)
May 28, 2018 6:03:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/202) took 19267 ms. Total solver calls (SAT/UNSAT): 1145(821/324)
May 28, 2018 6:03:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/202) took 22934 ms. Total solver calls (SAT/UNSAT): 1294(875/419)
May 28, 2018 6:03:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/202) took 26683 ms. Total solver calls (SAT/UNSAT): 1568(1091/477)
May 28, 2018 6:03:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/202) took 29909 ms. Total solver calls (SAT/UNSAT): 1763(1253/510)
May 28, 2018 6:03:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/202) took 32986 ms. Total solver calls (SAT/UNSAT): 1961(1413/548)
May 28, 2018 6:03:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/202) took 36737 ms. Total solver calls (SAT/UNSAT): 2120(1554/566)
May 28, 2018 6:04:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(46/202) took 40251 ms. Total solver calls (SAT/UNSAT): 2318(1742/576)
May 28, 2018 6:04:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(50/202) took 43467 ms. Total solver calls (SAT/UNSAT): 2536(1885/651)
May 28, 2018 6:04:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(54/202) took 47574 ms. Total solver calls (SAT/UNSAT): 2718(1981/737)
May 28, 2018 6:04:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(58/202) took 50612 ms. Total solver calls (SAT/UNSAT): 2916(2109/807)
May 28, 2018 6:04:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/202) took 54038 ms. Total solver calls (SAT/UNSAT): 3062(2185/877)
May 28, 2018 6:04:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/202) took 57905 ms. Total solver calls (SAT/UNSAT): 3242(2313/929)
May 28, 2018 6:04:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(74/202) took 61527 ms. Total solver calls (SAT/UNSAT): 3766(2550/1216)
May 28, 2018 6:04:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(77/202) took 64580 ms. Total solver calls (SAT/UNSAT): 3928(2590/1338)
May 28, 2018 6:04:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/202) took 68703 ms. Total solver calls (SAT/UNSAT): 4136(2640/1496)
May 28, 2018 6:04:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/202) took 71885 ms. Total solver calls (SAT/UNSAT): 4410(2735/1675)
May 28, 2018 6:04:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(92/202) took 75023 ms. Total solver calls (SAT/UNSAT): 4550(2795/1755)
May 28, 2018 6:04:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(97/202) took 78632 ms. Total solver calls (SAT/UNSAT): 4744(2812/1932)
May 28, 2018 6:04:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(105/202) took 82453 ms. Total solver calls (SAT/UNSAT): 5036(2830/2206)
May 28, 2018 6:04:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(114/202) took 86038 ms. Total solver calls (SAT/UNSAT): 5184(2914/2270)
May 28, 2018 6:04:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(118/202) took 91060 ms. Total solver calls (SAT/UNSAT): 5331(3033/2298)
May 28, 2018 6:04:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(128/202) took 94244 ms. Total solver calls (SAT/UNSAT): 5661(3195/2466)
May 28, 2018 6:04:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/202) took 97508 ms. Total solver calls (SAT/UNSAT): 5807(3250/2557)
May 28, 2018 6:05:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(138/202) took 100583 ms. Total solver calls (SAT/UNSAT): 5931(3301/2630)
May 28, 2018 6:05:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(144/202) took 103828 ms. Total solver calls (SAT/UNSAT): 6044(3304/2740)
May 28, 2018 6:05:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(151/202) took 106936 ms. Total solver calls (SAT/UNSAT): 6189(3305/2884)
May 28, 2018 6:05:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(163/202) took 110012 ms. Total solver calls (SAT/UNSAT): 6303(3305/2998)
May 28, 2018 6:05:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(185/202) took 113099 ms. Total solver calls (SAT/UNSAT): 6621(3383/3238)
May 28, 2018 6:05:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 114923 ms. Total solver calls (SAT/UNSAT): 6714(3414/3300)
May 28, 2018 6:05:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 202 transitions.
May 28, 2018 6:05:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 731 ms. Total solver calls (SAT/UNSAT): 61(0/61)
May 28, 2018 6:05:16 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 123287ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-5.tgz
mv ParamProductionCell-PT-5 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ParamProductionCell-PT-5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585300110"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;