Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 204K
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.1K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 42K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-COL-6, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585200026
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-6-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527484359635

05:12:42.039 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
05:12:42.042 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((("(((((((((((((((((((((((((((((((((((((((((((pid0.P_ifyi_15_0>=1)&&(pid1.y_1>=1))||((pid0.P_ifyi_15_0>=1)&&(pid2.y_2>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid3.y_3>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid4.y_4>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid5.y_5>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid6.y_6>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid0.y_0>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid2.y_2>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid3.y_3>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid4.y_4>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid5.y_5>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid6.y_6>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid0.y_0>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid1.y_1>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid3.y_3>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid4.y_4>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid5.y_5>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid6.y_6>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid0.y_0>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid1.y_1>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid2.y_2>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid4.y_4>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid5.y_5>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid6.y_6>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid0.y_0>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid1.y_1>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid2.y_2>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid3.y_3>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid5.y_5>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid6.y_6>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid0.y_0>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid1.y_1>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid2.y_2>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid3.y_3>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid4.y_4>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid6.y_6>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid0.y_0>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid1.y_1>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid2.y_2>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid3.y_3>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid4.y_4>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid5.y_5>=1)))")U(X(X(F("(((((((((((((((((((((((((((((((((((((((((((pid0.P_ifyi_15_0>=1)&&(pid1.y_1>=1))||((pid0.P_ifyi_15_0>=1)&&(pid2.y_2>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid3.y_3>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid4.y_4>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid5.y_5>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid6.y_6>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid0.y_0>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid2.y_2>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid3.y_3>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid4.y_4>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid5.y_5>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid6.y_6>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid0.y_0>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid1.y_1>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid3.y_3>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid4.y_4>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid5.y_5>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid6.y_6>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid0.y_0>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid1.y_1>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid2.y_2>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid4.y_4>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid5.y_5>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid6.y_6>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid0.y_0>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid1.y_1>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid2.y_2>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid3.y_3>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid5.y_5>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid6.y_6>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid0.y_0>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid1.y_1>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid2.y_2>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid3.y_3>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid4.y_4>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid6.y_6>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid0.y_0>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid1.y_1>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid2.y_2>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid3.y_3>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid4.y_4>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid5.y_5>=1)))"))))))
Formula 0 simplified : !("(((((((((((((((((((((((((((((((((((((((((((pid0.P_ifyi_15_0>=1)&&(pid1.y_1>=1))||((pid0.P_ifyi_15_0>=1)&&(pid2.y_2>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid3.y_3>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid4.y_4>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid5.y_5>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid6.y_6>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid0.y_0>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid2.y_2>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid3.y_3>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid4.y_4>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid5.y_5>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid6.y_6>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid0.y_0>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid1.y_1>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid3.y_3>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid4.y_4>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid5.y_5>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid6.y_6>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid0.y_0>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid1.y_1>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid2.y_2>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid4.y_4>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid5.y_5>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid6.y_6>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid0.y_0>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid1.y_1>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid2.y_2>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid3.y_3>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid5.y_5>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid6.y_6>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid0.y_0>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid1.y_1>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid2.y_2>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid3.y_3>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid4.y_4>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid6.y_6>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid0.y_0>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid1.y_1>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid2.y_2>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid3.y_3>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid4.y_4>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid5.y_5>=1)))" U XXF"(((((((((((((((((((((((((((((((((((((((((((pid0.P_ifyi_15_0>=1)&&(pid1.y_1>=1))||((pid0.P_ifyi_15_0>=1)&&(pid2.y_2>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid3.y_3>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid4.y_4>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid5.y_5>=1)))||((pid0.P_ifyi_15_0>=1)&&(pid6.y_6>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid0.y_0>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid2.y_2>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid3.y_3>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid4.y_4>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid5.y_5>=1)))||((pid1.P_ifyi_15_1>=1)&&(pid6.y_6>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid0.y_0>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid1.y_1>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid3.y_3>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid4.y_4>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid5.y_5>=1)))||((pid2.P_ifyi_15_2>=1)&&(pid6.y_6>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid0.y_0>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid1.y_1>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid2.y_2>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid4.y_4>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid5.y_5>=1)))||((pid3.P_ifyi_15_3>=1)&&(pid6.y_6>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid0.y_0>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid1.y_1>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid2.y_2>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid3.y_3>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid5.y_5>=1)))||((pid4.P_ifyi_15_4>=1)&&(pid6.y_6>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid0.y_0>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid1.y_1>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid2.y_2>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid3.y_3>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid4.y_4>=1)))||((pid5.P_ifyi_15_5>=1)&&(pid6.y_6>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid0.y_0>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid1.y_1>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid2.y_2>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid3.y_3>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid4.y_4>=1)))||((pid6.P_ifyi_15_6>=1)&&(pid5.y_5>=1)))")
built 113 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 315
// Phase 1: matrix 315 rows 217 cols
invariant :pid_x_pid46:wait_46 + pid_x_pid46:done_46 + -1'pid6:P_await_13_6 = 0
invariant :pid_x_pid8:wait_8 + pid_x_pid8:done_8 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_bool12:b_12 + pid_x_bool13:b_13 = 1
invariant :pid_x_pid25:wait_25 + pid_x_pid25:done_25 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid17:wait_17 + pid_x_pid17:done_17 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_bool6:b_6 + pid_x_bool7:b_7 = 1
invariant :pid_x_pid34:wait_34 + pid_x_pid34:done_34 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid33:wait_33 + pid_x_pid33:done_33 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid11:wait_11 + pid_x_pid11:done_11 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_pid26:wait_26 + pid_x_pid26:done_26 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid32:wait_32 + pid_x_pid32:done_32 + -1'pid4:P_await_13_4 = 0
invariant :pid4:P_start_1_4 + pid4:P_setx_3_4 + pid4:P_setbi_5_4 + pid4:P_ify0_4_4 + pid4:P_sety_9_4 + pid4:P_ifxi_10_4 + pid4:P_setbi_11_4 + pid4:P_fordo_12_4 + pid4:P_await_13_4 + pid4:P_ifyi_15_4 + pid4:P_awaity_4 + pid4:P_CS_21_4 + pid4:P_setbi_24_4 = 1
invariant :pid5:P_start_1_5 + pid5:P_setx_3_5 + pid5:P_setbi_5_5 + pid5:P_ify0_4_5 + pid5:P_sety_9_5 + pid5:P_ifxi_10_5 + pid5:P_setbi_11_5 + pid5:P_fordo_12_5 + pid5:P_await_13_5 + pid5:P_ifyi_15_5 + pid5:P_awaity_5 + pid5:P_CS_21_5 + pid5:P_setbi_24_5 = 1
invariant :pid_x_pid42:wait_42 + pid_x_pid42:done_42 = 0
invariant :pid_x_pid16:wait_16 + pid_x_pid16:done_16 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid48:wait_48 + pid_x_pid48:done_48 + -1'pid6:P_await_13_6 = 0
invariant :pid_x_pid30:wait_30 + pid_x_pid30:done_30 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid24:wait_24 + pid_x_pid24:done_24 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid28:wait_28 + pid_x_pid28:done_28 = 0
invariant :pid_x_pid13:wait_13 + pid_x_pid13:done_13 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_bool8:b_8 + pid_x_bool9:b_9 = 1
invariant :pid_x_pid22:wait_22 + pid_x_pid22:done_22 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid19:wait_19 + pid_x_pid19:done_19 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid43:wait_43 + pid_x_pid43:done_43 + -1'pid6:P_await_13_6 = 0
invariant :pid0:x_0 + pid1:x_1 + pid2:x_2 + pid3:x_3 + pid4:x_4 + pid5:x_5 + pid6:x_6 = 1
invariant :pid_x_pid4:wait_4 + pid_x_pid4:done_4 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_bool10:b_10 + pid_x_bool11:b_11 = 1
invariant :pid_x_pid39:wait_39 + pid_x_pid39:done_39 + -1'pid5:P_await_13_5 = 0
invariant :pid_x_pid27:wait_27 + pid_x_pid27:done_27 + -1'pid3:P_await_13_3 = 0
invariant :pid1:P_start_1_1 + pid1:P_setx_3_1 + pid1:P_setbi_5_1 + pid1:P_ify0_4_1 + pid1:P_sety_9_1 + pid1:P_ifxi_10_1 + pid1:P_setbi_11_1 + pid1:P_fordo_12_1 + pid1:P_await_13_1 + pid1:P_ifyi_15_1 + pid1:P_awaity_1 + pid1:P_CS_21_1 + pid1:P_setbi_24_1 = 1
invariant :pid_x_pid9:wait_9 + pid_x_pid9:done_9 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_bool4:b_4 + pid_x_bool5:b_5 = 1
invariant :pid_x_pid35:wait_35 + pid_x_pid35:done_35 = 0
invariant :pid3:P_start_1_3 + pid3:P_setx_3_3 + pid3:P_setbi_5_3 + pid3:P_ify0_4_3 + pid3:P_sety_9_3 + pid3:P_ifxi_10_3 + pid3:P_setbi_11_3 + pid3:P_fordo_12_3 + pid3:P_await_13_3 + pid3:P_ifyi_15_3 + pid3:P_awaity_3 + pid3:P_CS_21_3 + pid3:P_setbi_24_3 = 1
invariant :pid_x_pid3:wait_3 + pid_x_pid3:done_3 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_pid5:wait_5 + pid_x_pid5:done_5 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_pid41:wait_41 + pid_x_pid41:done_41 + -1'pid5:P_await_13_5 = 0
invariant :pid_x_pid47:wait_47 + pid_x_pid47:done_47 + -1'pid6:P_await_13_6 = 0
invariant :pid_x_pid1:wait_1 + pid_x_pid1:done_1 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_pid7:wait_7 + pid_x_pid7:done_7 = 0
invariant :pid_x_pid20:wait_20 + pid_x_pid20:done_20 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid31:wait_31 + pid_x_pid31:done_31 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid10:wait_10 + pid_x_pid10:done_10 + -1'pid1:P_await_13_1 = 0
invariant :pid0:y_0 + pid1:y_1 + pid2:y_2 + pid3:y_3 + pid4:y_4 + pid5:y_5 + pid6:y_6 = 1
invariant :pid_x_bool0:b_0 + pid_x_bool1:b_1 = 0
invariant :pid_x_pid29:wait_29 + pid_x_pid29:done_29 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid14:wait_14 + pid_x_pid14:done_14 = 0
invariant :pid6:P_start_1_6 + pid6:P_setx_3_6 + pid6:P_setbi_5_6 + pid6:P_ify0_4_6 + pid6:P_sety_9_6 + pid6:P_ifxi_10_6 + pid6:P_setbi_11_6 + pid6:P_fordo_12_6 + pid6:P_await_13_6 + pid6:P_ifyi_15_6 + pid6:P_awaity_6 + pid6:P_CS_21_6 + pid6:P_setbi_24_6 = 1
invariant :pid_x_pid21:wait_21 + pid_x_pid21:done_21 = 0
invariant :pid_x_pid12:wait_12 + pid_x_pid12:done_12 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_pid2:wait_2 + pid_x_pid2:done_2 + -1'pid0:P_await_13_0 = 0
invariant :pid2:P_start_1_2 + pid2:P_setx_3_2 + pid2:P_setbi_5_2 + pid2:P_ify0_4_2 + pid2:P_sety_9_2 + pid2:P_ifxi_10_2 + pid2:P_setbi_11_2 + pid2:P_fordo_12_2 + pid2:P_await_13_2 + pid2:P_ifyi_15_2 + pid2:P_awaity_2 + pid2:P_CS_21_2 + pid2:P_setbi_24_2 = 1
invariant :pid_x_pid0:wait_0 + pid_x_pid0:done_0 = 0
invariant :pid_x_pid15:wait_15 + pid_x_pid15:done_15 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_bool2:b_2 + pid_x_bool3:b_3 = 1
invariant :pid_x_pid44:wait_44 + pid_x_pid44:done_44 + -1'pid6:P_await_13_6 = 0
invariant :pid_x_pid23:wait_23 + pid_x_pid23:done_23 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid6:wait_6 + pid_x_pid6:done_6 + -1'pid0:P_await_13_0 = 0
invariant :pid0:P_start_1_0 + pid0:P_setx_3_0 + pid0:P_setbi_5_0 + pid0:P_ify0_4_0 + pid0:P_sety_9_0 + pid0:P_ifxi_10_0 + pid0:P_setbi_11_0 + pid0:P_fordo_12_0 + pid0:P_await_13_0 + pid0:P_ifyi_15_0 + pid0:P_awaity_0 + pid0:P_CS_21_0 + pid0:P_setbi_24_0 = 0
invariant :pid_x_pid40:wait_40 + pid_x_pid40:done_40 + -1'pid5:P_await_13_5 = 0
invariant :pid_x_pid18:wait_18 + pid_x_pid18:done_18 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid45:wait_45 + pid_x_pid45:done_45 + -1'pid6:P_await_13_6 = 0
invariant :pid_x_pid38:wait_38 + pid_x_pid38:done_38 + -1'pid5:P_await_13_5 = 0
invariant :pid_x_pid37:wait_37 + pid_x_pid37:done_37 + -1'pid5:P_await_13_5 = 0
invariant :pid_x_pid36:wait_36 + pid_x_pid36:done_36 + -1'pid5:P_await_13_5 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6137 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 58 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP0==true))U(X(X(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 77 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](<>(X([]((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 46 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP2==true))))U(<>((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP1==true))U((LTLAP4==true)))U((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 93 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](<>(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](<>(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 574 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 301 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP8==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 253 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP9==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 236 ms.
FORMULA LamportFastMutEx-COL-6-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
255

BK_STOP 1527485163933

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 5:12:41 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 5:12:41 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 5:12:41 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 895 ms
May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 28, 2018 5:12:42 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 28, 2018 5:12:42 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 10 ms
May 28, 2018 5:12:42 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 5:12:42 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 5:12:42 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 28, 2018 5:12:42 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 28, 2018 5:12:42 AM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 15.0 instantiations of transitions. Total transitions/syncs built is 423
May 28, 2018 5:12:42 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 148 ms
May 28, 2018 5:12:44 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays P_start_1, x, y, b, P_setx_3, P_setbi_5, P_ify0_4, P_sety_9, P_ifxi_10, P_setbi_11, P_fordo_12, wait, P_await_13, done, P_ifyi_15, P_awaity, P_CS_21, P_setbi_24 to variables to allow decomposition.
May 28, 2018 5:12:44 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 321 redundant transitions.
May 28, 2018 5:12:44 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 9 ms
May 28, 2018 5:12:44 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 8 ms
May 28, 2018 5:12:44 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 95 transitions. Expanding to a total of 514 deterministic transitions.
May 28, 2018 5:12:44 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 5 ms.
May 28, 2018 5:12:44 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 65 place invariants in 119 ms
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 217 variables to be positive in 875 ms
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 420 transitions.
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/420 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 46 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 420 transitions.
May 28, 2018 5:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 16 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 420 transitions.
May 28, 2018 5:12:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/420) took 36 ms. Total solver calls (SAT/UNSAT): 65(0/65)
May 28, 2018 5:12:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(56/420) took 3073 ms. Total solver calls (SAT/UNSAT): 6063(342/5721)
May 28, 2018 5:12:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/420) took 6175 ms. Total solver calls (SAT/UNSAT): 12530(885/11645)
May 28, 2018 5:13:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/420) took 9267 ms. Total solver calls (SAT/UNSAT): 16413(1224/15189)
May 28, 2018 5:13:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(134/420) took 12670 ms. Total solver calls (SAT/UNSAT): 18636(1466/17170)
May 28, 2018 5:13:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(160/420) took 15687 ms. Total solver calls (SAT/UNSAT): 22575(1797/20778)
May 28, 2018 5:13:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(242/420) took 18699 ms. Total solver calls (SAT/UNSAT): 28132(2205/25927)
May 28, 2018 5:13:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(335/420) took 21722 ms. Total solver calls (SAT/UNSAT): 32466(2690/29776)
May 28, 2018 5:13:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 23571 ms. Total solver calls (SAT/UNSAT): 34650(2883/31767)
May 28, 2018 5:13:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 420 transitions.
May 28, 2018 5:13:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 29 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:13:15 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 31164ms conformant to PINS in folder :/home/mcc/execution
pins2lts-mc, 0.000: Registering PINS so language module
pins2lts-mc, 0.001, ** error **: out of memory trying to get 4294967296
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
255
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:167)
at fr.lip6.move.gal.application.LTSminRunner.access$9(LTSminRunner.java:122)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:91)
at java.lang.Thread.run(Thread.java:748)
ITS-tools command line returned an error code 139

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-6"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-6.tgz
mv LamportFastMutEx-COL-6 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-6, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585200026"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;