Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........................................
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.3K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 40K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-COL-4, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585200022
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-4-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527484356268

05:12:38.901 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
05:12:38.903 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("((((((((((((((((((((((((((pid0.y_0>=1)&&(pid0.P_CS_21_0>=1))||((pid1.y_1>=1)&&(pid0.P_CS_21_0>=1)))||((pid2.y_2>=1)&&(pid0.P_CS_21_0>=1)))||((pid3.y_3>=1)&&(pid0.P_CS_21_0>=1)))||((pid4.y_4>=1)&&(pid0.P_CS_21_0>=1)))||((pid0.y_0>=1)&&(pid1.P_CS_21_1>=1)))||((pid1.y_1>=1)&&(pid1.P_CS_21_1>=1)))||((pid2.y_2>=1)&&(pid1.P_CS_21_1>=1)))||((pid3.y_3>=1)&&(pid1.P_CS_21_1>=1)))||((pid4.y_4>=1)&&(pid1.P_CS_21_1>=1)))||((pid0.y_0>=1)&&(pid2.P_CS_21_2>=1)))||((pid1.y_1>=1)&&(pid2.P_CS_21_2>=1)))||((pid2.y_2>=1)&&(pid2.P_CS_21_2>=1)))||((pid3.y_3>=1)&&(pid2.P_CS_21_2>=1)))||((pid4.y_4>=1)&&(pid2.P_CS_21_2>=1)))||((pid0.y_0>=1)&&(pid3.P_CS_21_3>=1)))||((pid1.y_1>=1)&&(pid3.P_CS_21_3>=1)))||((pid2.y_2>=1)&&(pid3.P_CS_21_3>=1)))||((pid3.y_3>=1)&&(pid3.P_CS_21_3>=1)))||((pid4.y_4>=1)&&(pid3.P_CS_21_3>=1)))||((pid0.y_0>=1)&&(pid4.P_CS_21_4>=1)))||((pid1.y_1>=1)&&(pid4.P_CS_21_4>=1)))||((pid2.y_2>=1)&&(pid4.P_CS_21_4>=1)))||((pid3.y_3>=1)&&(pid4.P_CS_21_4>=1)))||((pid4.y_4>=1)&&(pid4.P_CS_21_4>=1)))"))
Formula 0 simplified : !"((((((((((((((((((((((((((pid0.y_0>=1)&&(pid0.P_CS_21_0>=1))||((pid1.y_1>=1)&&(pid0.P_CS_21_0>=1)))||((pid2.y_2>=1)&&(pid0.P_CS_21_0>=1)))||((pid3.y_3>=1)&&(pid0.P_CS_21_0>=1)))||((pid4.y_4>=1)&&(pid0.P_CS_21_0>=1)))||((pid0.y_0>=1)&&(pid1.P_CS_21_1>=1)))||((pid1.y_1>=1)&&(pid1.P_CS_21_1>=1)))||((pid2.y_2>=1)&&(pid1.P_CS_21_1>=1)))||((pid3.y_3>=1)&&(pid1.P_CS_21_1>=1)))||((pid4.y_4>=1)&&(pid1.P_CS_21_1>=1)))||((pid0.y_0>=1)&&(pid2.P_CS_21_2>=1)))||((pid1.y_1>=1)&&(pid2.P_CS_21_2>=1)))||((pid2.y_2>=1)&&(pid2.P_CS_21_2>=1)))||((pid3.y_3>=1)&&(pid2.P_CS_21_2>=1)))||((pid4.y_4>=1)&&(pid2.P_CS_21_2>=1)))||((pid0.y_0>=1)&&(pid3.P_CS_21_3>=1)))||((pid1.y_1>=1)&&(pid3.P_CS_21_3>=1)))||((pid2.y_2>=1)&&(pid3.P_CS_21_3>=1)))||((pid3.y_3>=1)&&(pid3.P_CS_21_3>=1)))||((pid4.y_4>=1)&&(pid3.P_CS_21_3>=1)))||((pid0.y_0>=1)&&(pid4.P_CS_21_4>=1)))||((pid1.y_1>=1)&&(pid4.P_CS_21_4>=1)))||((pid2.y_2>=1)&&(pid4.P_CS_21_4>=1)))||((pid3.y_3>=1)&&(pid4.P_CS_21_4>=1)))||((pid4.y_4>=1)&&(pid4.P_CS_21_4>=1)))"
built 61 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 185
// Phase 1: matrix 185 rows 135 cols
invariant :pid_x_pid12:wait_12 + pid_x_pid12:done_12 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid21:wait_21 + pid_x_pid21:done_21 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid17:wait_17 + pid_x_pid17:done_17 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid8:wait_8 + pid_x_pid8:done_8 + -1'pid1:P_await_13_1 = 0
invariant :pid0:x_0 + pid1:x_1 + pid2:x_2 + pid3:x_3 + pid4:x_4 = 1
invariant :pid_x_pid1:wait_1 + pid_x_pid1:done_1 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_bool2:b_2 + pid_x_bool3:b_3 = 1
invariant :pid4:P_start_1_4 + pid4:P_setx_3_4 + pid4:P_setbi_5_4 + pid4:P_ify0_4_4 + pid4:P_sety_9_4 + pid4:P_ifxi_10_4 + pid4:P_setbi_11_4 + pid4:P_fordo_12_4 + pid4:P_await_13_4 + pid4:P_ifyi_15_4 + pid4:P_awaity_4 + pid4:P_CS_21_4 + pid4:P_setbi_24_4 = 1
invariant :pid_x_pid5:wait_5 + pid_x_pid5:done_5 = 0
invariant :pid_x_bool6:b_6 + pid_x_bool7:b_7 = 1
invariant :pid0:y_0 + pid1:y_1 + pid2:y_2 + pid3:y_3 + pid4:y_4 = 1
invariant :pid_x_pid10:wait_10 + pid_x_pid10:done_10 = 0
invariant :pid_x_pid13:wait_13 + pid_x_pid13:done_13 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid2:wait_2 + pid_x_pid2:done_2 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_pid9:wait_9 + pid_x_pid9:done_9 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_pid24:wait_24 + pid_x_pid24:done_24 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid3:wait_3 + pid_x_pid3:done_3 + -1'pid0:P_await_13_0 = 0
invariant :pid1:P_start_1_1 + pid1:P_setx_3_1 + pid1:P_setbi_5_1 + pid1:P_ify0_4_1 + pid1:P_sety_9_1 + pid1:P_ifxi_10_1 + pid1:P_setbi_11_1 + pid1:P_fordo_12_1 + pid1:P_await_13_1 + pid1:P_ifyi_15_1 + pid1:P_awaity_1 + pid1:P_CS_21_1 + pid1:P_setbi_24_1 = 1
invariant :pid_x_pid22:wait_22 + pid_x_pid22:done_22 + -1'pid4:P_await_13_4 = 0
invariant :pid_x_pid20:wait_20 + pid_x_pid20:done_20 = 0
invariant :pid_x_pid4:wait_4 + pid_x_pid4:done_4 + -1'pid0:P_await_13_0 = 0
invariant :pid_x_pid14:wait_14 + pid_x_pid14:done_14 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_pid0:wait_0 + pid_x_pid0:done_0 = 0
invariant :pid3:P_start_1_3 + pid3:P_setx_3_3 + pid3:P_setbi_5_3 + pid3:P_ify0_4_3 + pid3:P_sety_9_3 + pid3:P_ifxi_10_3 + pid3:P_setbi_11_3 + pid3:P_fordo_12_3 + pid3:P_await_13_3 + pid3:P_ifyi_15_3 + pid3:P_awaity_3 + pid3:P_CS_21_3 + pid3:P_setbi_24_3 = 1
invariant :pid_x_pid18:wait_18 + pid_x_pid18:done_18 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid15:wait_15 + pid_x_pid15:done_15 = 0
invariant :pid_x_pid11:wait_11 + pid_x_pid11:done_11 + -1'pid2:P_await_13_2 = 0
invariant :pid_x_bool0:b_0 + pid_x_bool1:b_1 = 0
invariant :pid_x_bool4:b_4 + pid_x_bool5:b_5 = 1
invariant :pid_x_pid7:wait_7 + pid_x_pid7:done_7 + -1'pid1:P_await_13_1 = 0
invariant :pid_x_bool8:b_8 + pid_x_bool9:b_9 = 1
invariant :pid_x_pid19:wait_19 + pid_x_pid19:done_19 + -1'pid3:P_await_13_3 = 0
invariant :pid0:P_start_1_0 + pid0:P_setx_3_0 + pid0:P_setbi_5_0 + pid0:P_ify0_4_0 + pid0:P_sety_9_0 + pid0:P_ifxi_10_0 + pid0:P_setbi_11_0 + pid0:P_fordo_12_0 + pid0:P_await_13_0 + pid0:P_ifyi_15_0 + pid0:P_awaity_0 + pid0:P_CS_21_0 + pid0:P_setbi_24_0 = 0
invariant :pid_x_pid16:wait_16 + pid_x_pid16:done_16 + -1'pid3:P_await_13_3 = 0
invariant :pid_x_pid23:wait_23 + pid_x_pid23:done_23 + -1'pid4:P_await_13_4 = 0
invariant :pid2:P_start_1_2 + pid2:P_setx_3_2 + pid2:P_setbi_5_2 + pid2:P_ify0_4_2 + pid2:P_sety_9_2 + pid2:P_ifxi_10_2 + pid2:P_setbi_11_2 + pid2:P_fordo_12_2 + pid2:P_await_13_2 + pid2:P_ifyi_15_2 + pid2:P_awaity_2 + pid2:P_CS_21_2 + pid2:P_setbi_24_2 = 1
invariant :pid_x_pid6:wait_6 + pid_x_pid6:done_6 + -1'pid1:P_await_13_1 = 0
Reverse transition relation is NOT exact ! Due to transitions T_setbi_2_1, T_setbi_2_2, T_setbi_2_3, T_setbi_2_4, T_setx_3_1, T_setx_3_2, T_setx_3_3, T_setx_3_4, T_setbi_5_1, T_setbi_5_2, T_setbi_5_3, T_setbi_5_4, T_awaity, T_sety_9_0, T_sety_9_1, T_sety_9_2, T_sety_9_3, T_sety_9_4, T_setbi_11_1, T_setbi_11_2, T_setbi_11_3, T_setbi_11_4, T_ynei_15_0, T_ynei_15_1, T_ynei_15_2, T_ynei_15_3, T_ynei_15_4, T_sety0_23, T_setbi_24_1, T_setbi_24_2, T_setbi_24_3, T_setbi_24_4, pid1.T_yeqi_15_1, pid2.T_yeqi_15_2, pid3.T_yeqi_15_3, pid4.T_yeqi_15_4, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :11/22/36/69
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1681 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,16.8645,339436,1,0,673669,9804,2010,950751,340,85885,1894800
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA LamportFastMutEx-COL-4-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((X(G(G(G(F("(((((((((((((((((((((((((((pid_x_bool0.b_0>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid0.wait_0>=1))||(((pid_x_bool0.b_0>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid5.wait_5>=1)))||(((pid_x_bool0.b_0>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid10.wait_10>=1)))||(((pid_x_bool0.b_0>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid15.wait_15>=1)))||(((pid_x_bool0.b_0>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid20.wait_20>=1)))||(((pid_x_bool2.b_2>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid1.wait_1>=1)))||(((pid_x_bool2.b_2>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid6.wait_6>=1)))||(((pid_x_bool2.b_2>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid11.wait_11>=1)))||(((pid_x_bool2.b_2>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid16.wait_16>=1)))||(((pid_x_bool2.b_2>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid21.wait_21>=1)))||(((pid_x_bool4.b_4>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid2.wait_2>=1)))||(((pid_x_bool4.b_4>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid7.wait_7>=1)))||(((pid_x_bool4.b_4>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid12.wait_12>=1)))||(((pid_x_bool4.b_4>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid17.wait_17>=1)))||(((pid_x_bool4.b_4>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid22.wait_22>=1)))||(((pid_x_bool6.b_6>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid3.wait_3>=1)))||(((pid_x_bool6.b_6>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid8.wait_8>=1)))||(((pid_x_bool6.b_6>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid13.wait_13>=1)))||(((pid_x_bool6.b_6>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid18.wait_18>=1)))||(((pid_x_bool6.b_6>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid23.wait_23>=1)))||(((pid_x_bool8.b_8>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid4.wait_4>=1)))||(((pid_x_bool8.b_8>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid9.wait_9>=1)))||(((pid_x_bool8.b_8>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid14.wait_14>=1)))||(((pid_x_bool8.b_8>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid19.wait_19>=1)))||(((pid_x_bool8.b_8>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid24.wait_24>=1)))")))))))
Formula 1 simplified : !XGF"(((((((((((((((((((((((((((pid_x_bool0.b_0>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid0.wait_0>=1))||(((pid_x_bool0.b_0>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid5.wait_5>=1)))||(((pid_x_bool0.b_0>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid10.wait_10>=1)))||(((pid_x_bool0.b_0>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid15.wait_15>=1)))||(((pid_x_bool0.b_0>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid20.wait_20>=1)))||(((pid_x_bool2.b_2>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid1.wait_1>=1)))||(((pid_x_bool2.b_2>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid6.wait_6>=1)))||(((pid_x_bool2.b_2>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid11.wait_11>=1)))||(((pid_x_bool2.b_2>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid16.wait_16>=1)))||(((pid_x_bool2.b_2>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid21.wait_21>=1)))||(((pid_x_bool4.b_4>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid2.wait_2>=1)))||(((pid_x_bool4.b_4>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid7.wait_7>=1)))||(((pid_x_bool4.b_4>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid12.wait_12>=1)))||(((pid_x_bool4.b_4>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid17.wait_17>=1)))||(((pid_x_bool4.b_4>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid22.wait_22>=1)))||(((pid_x_bool6.b_6>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid3.wait_3>=1)))||(((pid_x_bool6.b_6>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid8.wait_8>=1)))||(((pid_x_bool6.b_6>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid13.wait_13>=1)))||(((pid_x_bool6.b_6>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid18.wait_18>=1)))||(((pid_x_bool6.b_6>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid23.wait_23>=1)))||(((pid_x_bool8.b_8>=1)&&(pid0.P_await_13_0>=1))&&(pid_x_pid4.wait_4>=1)))||(((pid_x_bool8.b_8>=1)&&(pid1.P_await_13_1>=1))&&(pid_x_pid9.wait_9>=1)))||(((pid_x_bool8.b_8>=1)&&(pid2.P_await_13_2>=1))&&(pid_x_pid14.wait_14>=1)))||(((pid_x_bool8.b_8>=1)&&(pid3.P_await_13_3>=1))&&(pid_x_pid19.wait_19>=1)))||(((pid_x_bool8.b_8>=1)&&(pid4.P_await_13_4>=1))&&(pid_x_pid24.wait_24>=1)))"
Compilation finished in 3907 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 94 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([]([](<>((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 332 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>([]([](X((LTLAP0==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 67 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP2==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 104 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP3==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 84 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(((LTLAP5==true))U((LTLAP5==true))))U((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([]([](X([]((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP7==true))U(((LTLAP8==true))U(<>((LTLAP9==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 116 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>((LTLAP5==true)))U(X([]([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 58 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 129 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 164 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 82 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 74 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP2==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 112 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X(X((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 70 ms.
FORMULA LamportFastMutEx-COL-4-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527484382013

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 5:12:38 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 5:12:38 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 5:12:38 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 871 ms
May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 28, 2018 5:12:39 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 28, 2018 5:12:39 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 6 ms
May 28, 2018 5:12:39 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 5:12:39 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 5:12:39 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 28, 2018 5:12:39 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 28, 2018 5:12:39 AM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 11.0 instantiations of transitions. Total transitions/syncs built is 253
May 28, 2018 5:12:39 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 138 ms
May 28, 2018 5:12:40 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays P_start_1, x, y, b, P_setx_3, P_setbi_5, P_ify0_4, P_sety_9, P_ifxi_10, P_setbi_11, P_fordo_12, wait, P_await_13, done, P_ifyi_15, P_awaity, P_CS_21, P_setbi_24 to variables to allow decomposition.
May 28, 2018 5:12:40 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 164 redundant transitions.
May 28, 2018 5:12:40 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 8 ms
May 28, 2018 5:12:40 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 5 ms
May 28, 2018 5:12:41 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 69 transitions. Expanding to a total of 298 deterministic transitions.
May 28, 2018 5:12:41 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 14 ms.
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 37 place invariants in 38 ms
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 135 variables to be positive in 375 ms
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 230 transitions.
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/230 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 15 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 230 transitions.
May 28, 2018 5:12:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 14 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 230 transitions.
May 28, 2018 5:12:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/230) took 32 ms. Total solver calls (SAT/UNSAT): 49(0/49)
May 28, 2018 5:12:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/230) took 3096 ms. Total solver calls (SAT/UNSAT): 5084(377/4707)
May 28, 2018 5:12:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(162/230) took 6112 ms. Total solver calls (SAT/UNSAT): 9369(782/8587)
May 28, 2018 5:12:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(208/230) took 9125 ms. Total solver calls (SAT/UNSAT): 10737(926/9811)
May 28, 2018 5:12:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 9325 ms. Total solver calls (SAT/UNSAT): 10795(926/9869)
May 28, 2018 5:12:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 230 transitions.
May 28, 2018 5:12:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:12:55 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 14711ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-4"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-4.tgz
mv LamportFastMutEx-COL-4 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-4, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585200022"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;