Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 9.2M
-rw-r--r-- 1 mcc users 6.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 415K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.2M May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 67K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 193K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 36K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 312K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 873K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 6.0M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is BridgeAndVehicles-PT-V50P50N50, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-ebro-152732379600100
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527618232785

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph7088054696295417585.txt, -o, /tmp/graph7088054696295417585.bin, -w, /tmp/graph7088054696295417585.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph7088054696295417585.bin, -l, -1, -v, -w, /tmp/graph7088054696295417585.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Checking formula 0 : !((G(G((X("(((((((((((((((((((((((((((((((((((((((((((((((((((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_1>=1))&&(i1.u2.ATTENTE_B>=1))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_2>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_3>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_4>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_5>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_6>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_7>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_8>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_9>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_10>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_11>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_12>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_13>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_14>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_15>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_16>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_17>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_18>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_19>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_20>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_21>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_22>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_23>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_24>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_25>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_26>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_27>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_28>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_29>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_30>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_31>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_32>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_33>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_34>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_35>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_36>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_37>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_38>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_39>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_40>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_41>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_42>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_43>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_44>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_45>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_46>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_47>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_48>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_49>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_50>=1))&&(i1.u2.ATTENTE_B>=1)))"))U("(((i0.u1.CAPACITE>=50)&&(i2.u3.VIDANGE_1>=1))||((i0.u1.CAPACITE>=50)&&(i1.u4.VIDANGE_2>=1)))")))))
Formula 0 simplified : !G(X"(((((((((((((((((((((((((((((((((((((((((((((((((((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_1>=1))&&(i1.u2.ATTENTE_B>=1))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_2>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_3>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_4>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_5>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_6>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_7>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_8>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_9>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_10>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_11>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_12>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_13>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_14>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_15>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_16>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_17>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_18>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_19>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_20>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_21>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_22>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_23>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_24>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_25>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_26>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_27>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_28>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_29>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_30>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_31>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_32>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_33>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_34>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_35>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_36>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_37>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_38>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_39>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_40>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_41>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_42>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_43>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_44>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_45>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_46>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_47>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_48>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_49>=1))&&(i1.u2.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i2.u3.CONTROLEUR_2>=1))&&(i1.u4.NB_ATTENTE_B_50>=1))&&(i1.u2.ATTENTE_B>=1)))" U "(((i0.u1.CAPACITE>=50)&&(i2.u3.VIDANGE_1>=1))||((i0.u1.CAPACITE>=50)&&(i1.u4.VIDANGE_2>=1)))")
built 6 ordering constraints for composite.
built 255 ordering constraints for composite.
built 2755 ordering constraints for composite.
built 5356 ordering constraints for composite.
Compilation finished in 115597 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 188 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([]((X((LTLAP0==true)))U((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 699 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP2==true)))U(X(<>([]((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 603 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X(((LTLAP4==true))U((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 712 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP3==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 103083 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 75921 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(([]((LTLAP2==true)))U(((LTLAP1==true))U((LTLAP5==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1269 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>(((LTLAP1==true))U((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1134 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 94923 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 94731 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 89679 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>(<>([]((LTLAP9==true)))))U((<>((LTLAP10==true)))U([]((LTLAP11==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 83408 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 659 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP13==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 70273 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 77647 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](<>(<>((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 659 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((<>((LTLAP16==true)))U(((LTLAP17==true))U((LTLAP18==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 73170 ms.
FORMULA BridgeAndVehicles-PT-V50P50N50-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527619169686

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 6:23:55 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 29, 2018 6:23:55 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 6:23:56 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 607 ms
May 29, 2018 6:23:56 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
May 29, 2018 6:23:57 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 5408 transitions.
May 29, 2018 6:23:58 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 29, 2018 6:24:00 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1993 ms
May 29, 2018 6:24:01 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1263 ms
Begin: Tue May 29 18:24:03 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Tue May 29 18:24:03 2018
network size: 168 nodes, 2670 links, 10816 weight
quality increased from -0.098855 to 0.176828
end computation: Tue May 29 18:24:03 2018
level 1:
start computation: Tue May 29 18:24:03 2018
network size: 6 nodes, 30 links, 10816 weight
quality increased from 0.176828 to 0.194981
end computation: Tue May 29 18:24:03 2018
level 2:
start computation: Tue May 29 18:24:03 2018
network size: 3 nodes, 9 links, 10816 weight
quality increased from 0.194981 to 0.194981
end computation: Tue May 29 18:24:03 2018
End: Tue May 29 18:24:03 2018
Total duration: 0 sec
0.194981
May 29, 2018 6:24:03 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 29, 2018 6:24:05 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1295 ms
May 29, 2018 6:24:05 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 29, 2018 6:24:40 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 10691 redundant transitions.
May 29, 2018 6:24:41 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 257 ms
May 29, 2018 6:24:41 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 399 ms
May 29, 2018 6:24:42 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 5408 transitions.
May 29, 2018 6:24:42 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (5408) to apply POR reductions. Disabling POR matrices.
May 29, 2018 6:24:44 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 3336ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N50"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N50.tgz
mv BridgeAndVehicles-PT-V50P50N50 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is BridgeAndVehicles-PT-V50P50N50, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-ebro-152732379600100"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;