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Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r225-ebro-152732379600098
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for BridgeAndVehicles-PT-V50P50N20

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15747.970 3600000.00 7229161.00 631.40 FFTF?F?FFFFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 4.2M
-rw-r--r-- 1 mcc users 13K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 47K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 110K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 319K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 58K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 166K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 30K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 208K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 589K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 2.6M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is BridgeAndVehicles-PT-V50P50N20, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-ebro-152732379600098
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N20-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527617856803

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph8397756393835043829.txt, -o, /tmp/graph8397756393835043829.bin, -w, /tmp/graph8397756393835043829.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph8397756393835043829.bin, -l, -1, -v, -w, /tmp/graph8397756393835043829.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Checking formula 0 : !((G(("(((((((((((((((((((((((((((((((((((((((((((((((((((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_1>=1))&&(i2.u4.ATTENTE_B>=1))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_2>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_3>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_4>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_5>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_6>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_7>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_8>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_9>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_10>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_11>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_12>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_13>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_14>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_15>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_16>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_17>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_18>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_19>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_20>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_21>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_22>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_23>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_24>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_25>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_26>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_27>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_28>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_29>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_30>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_31>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_32>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_33>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_34>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_35>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_36>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_37>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_38>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_39>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_40>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_41>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_42>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_43>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_44>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_45>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_46>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_47>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_48>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_49>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_50>=1))&&(i2.u4.ATTENTE_B>=1)))")U(X("(((i0.u1.CHOIX_1>=1)&&(i1.u5.COMPTEUR_20>=1))||((i0.u1.CHOIX_2>=1)&&(i1.u5.COMPTEUR_20>=1)))")))))
Formula 0 simplified : !G("(((((((((((((((((((((((((((((((((((((((((((((((((((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_1>=1))&&(i2.u4.ATTENTE_B>=1))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_2>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_3>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_4>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_5>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_6>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_7>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_8>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_9>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_10>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_11>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_12>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_13>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_14>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_15>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_16>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_17>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_18>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_19>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_20>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_21>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_22>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_23>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_24>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_25>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_26>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_27>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_28>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_29>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_30>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_31>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_32>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_33>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_34>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_35>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_36>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_37>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_38>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_39>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_40>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_41>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_42>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_43>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_44>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_45>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_46>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_47>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_48>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_49>=1))&&(i2.u4.ATTENTE_B>=1)))||((((i0.u1.CAPACITE>=1)&&(i1.u2.CONTROLEUR_2>=1))&&(i2.u3.NB_ATTENTE_B_50>=1))&&(i2.u4.ATTENTE_B>=1)))" U X"(((i0.u1.CHOIX_1>=1)&&(i1.u5.COMPTEUR_20>=1))||((i0.u1.CHOIX_2>=1)&&(i1.u5.COMPTEUR_20>=1)))")
built 6 ordering constraints for composite.
built 195 ordering constraints for composite.
built 2296 ordering constraints for composite.
built 1225 ordering constraints for composite.
Compilation finished in 38193 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 82 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](((LTLAP0==true))U(X((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 324 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](((LTLAP2==true))U((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 12166 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(X(<>((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 121 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-02 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>((X((LTLAP5==true)))U([]((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 300 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP5==true))U(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP5==true))U(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP0==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 16370 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](([](<>((LTLAP4==true))))U(((LTLAP4==true))U((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 12750 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(([]([]((LTLAP8==true))))U(X(X((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 350 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](<>([]([]((LTLAP10==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 17586 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(X(<>([]((LTLAP11==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 346 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>((<>((LTLAP12==true)))U(X((LTLAP13==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 332 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP14==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 16364 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 13007 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 15249 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](<>([]((LTLAP17==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 12604 ms.
FORMULA BridgeAndVehicles-PT-V50P50N20-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP5==true))U(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>1800 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP5==true))U(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 6:17:40 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 29, 2018 6:17:40 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 6:17:40 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 402 ms
May 29, 2018 6:17:40 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 138 places.
May 29, 2018 6:17:41 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2348 transitions.
May 29, 2018 6:17:41 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 29, 2018 6:17:42 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 968 ms
May 29, 2018 6:17:43 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 653 ms
Begin: Tue May 29 18:17:44 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Tue May 29 18:17:44 2018
network size: 138 nodes, 2190 links, 4696 weight
quality increased from -0.090238 to 0.194799
end computation: Tue May 29 18:17:44 2018
level 1:
start computation: Tue May 29 18:17:44 2018
network size: 6 nodes, 30 links, 4696 weight
quality increased from 0.194799 to 0.21744
end computation: Tue May 29 18:17:44 2018
level 2:
start computation: Tue May 29 18:17:44 2018
network size: 3 nodes, 9 links, 4696 weight
quality increased from 0.21744 to 0.21744
end computation: Tue May 29 18:17:44 2018
End: Tue May 29 18:17:44 2018
Total duration: 0 sec
0.21744
May 29, 2018 6:17:44 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 29, 2018 6:17:45 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 560 ms
May 29, 2018 6:17:45 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 29, 2018 6:17:55 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 4571 redundant transitions.
May 29, 2018 6:17:56 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 69 ms
May 29, 2018 6:17:56 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 148 ms
May 29, 2018 6:17:56 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2348 transitions.
May 29, 2018 6:17:56 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (2348) to apply POR reductions. Disabling POR matrices.
May 29, 2018 6:17:57 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1161ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N20"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N20.tgz
mv BridgeAndVehicles-PT-V50P50N20 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is BridgeAndVehicles-PT-V50P50N20, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-ebro-152732379600098"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;