Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 55K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 167K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 14K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 39K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 102K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 598K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is BridgeAndVehicles-PT-V20P10N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-ebro-152732379600078
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527611474917

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph5415902998142307960.txt, -o, /tmp/graph5415902998142307960.bin, -w, /tmp/graph5415902998142307960.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph5415902998142307960.bin, -l, -1, -v, -w, /tmp/graph5415902998142307960.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(((X("(((i0.u1.CAPACITE>=10)&&(i1.u4.VIDANGE_1>=1))||((i0.u1.CAPACITE>=10)&&(i2.u5.VIDANGE_2>=1)))"))U(X(F(F("(((((((((((((((((((((((i1.u4.NB_ATTENTE_A_1>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1))||((((i1.u4.NB_ATTENTE_A_2>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_3>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_4>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_5>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_6>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_7>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_8>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_9>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_10>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_11>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_12>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_13>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_14>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_15>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_16>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_17>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_18>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_19>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_20>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))"))))))
Formula 0 simplified : !(X"(((i0.u1.CAPACITE>=10)&&(i1.u4.VIDANGE_1>=1))||((i0.u1.CAPACITE>=10)&&(i2.u5.VIDANGE_2>=1)))" U XF"(((((((((((((((((((((((i1.u4.NB_ATTENTE_A_1>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1))||((((i1.u4.NB_ATTENTE_A_2>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_3>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_4>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_5>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_6>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_7>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_8>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_9>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_10>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_11>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_12>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_13>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_14>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_15>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_16>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_17>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_18>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_19>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))||((((i1.u4.NB_ATTENTE_A_20>=1)&&(i0.u0.ATTENTE_A>=1))&&(i0.u1.CAPACITE>=1))&&(i2.u5.CONTROLEUR_1>=1)))")
built 6 ordering constraints for composite.
built 85 ordering constraints for composite.
built 526 ordering constraints for composite.
built 295 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 130
// Phase 1: matrix 130 rows 68 cols
invariant :i0:u1:CHOIX_1 + i0:u1:CHOIX_2 + i1:u4:CONTROLEUR_2 + i1:u4:VIDANGE_1 + i2:u5:CONTROLEUR_1 + i2:u5:VIDANGE_2 = 1
invariant :i0:u0:ROUTE_A + i0:u0:ATTENTE_A + i0:u1:SUR_PONT_A + i0:u1:SORTI_A = 20
invariant :i1:u2:COMPTEUR_0 + i1:u2:COMPTEUR_1 + i1:u2:COMPTEUR_2 + i1:u2:COMPTEUR_3 + i1:u2:COMPTEUR_4 + i1:u2:COMPTEUR_5 + i1:u2:COMPTEUR_6 + i1:u2:COMPTEUR_7 + i1:u2:COMPTEUR_8 + i1:u2:COMPTEUR_9 + i1:u2:COMPTEUR_10 = 1
invariant :i1:u4:NB_ATTENTE_B_0 + i2:u5:NB_ATTENTE_B_1 + i2:u5:NB_ATTENTE_B_2 + i2:u5:NB_ATTENTE_B_3 + i2:u5:NB_ATTENTE_B_4 + i2:u5:NB_ATTENTE_B_5 + i2:u5:NB_ATTENTE_B_6 + i2:u5:NB_ATTENTE_B_7 + i2:u5:NB_ATTENTE_B_8 + i2:u5:NB_ATTENTE_B_9 + i2:u5:NB_ATTENTE_B_10 + i2:u5:NB_ATTENTE_B_11 + i2:u5:NB_ATTENTE_B_12 + i2:u5:NB_ATTENTE_B_13 + i2:u5:NB_ATTENTE_B_14 + i2:u5:NB_ATTENTE_B_15 + i2:u5:NB_ATTENTE_B_16 + i2:u5:NB_ATTENTE_B_17 + i2:u5:NB_ATTENTE_B_18 + i2:u5:NB_ATTENTE_B_19 + i2:u5:NB_ATTENTE_B_20 = 1
invariant :i1:u4:NB_ATTENTE_A_1 + i1:u4:NB_ATTENTE_A_2 + i1:u4:NB_ATTENTE_A_3 + i1:u4:NB_ATTENTE_A_4 + i1:u4:NB_ATTENTE_A_5 + i1:u4:NB_ATTENTE_A_6 + i1:u4:NB_ATTENTE_A_7 + i1:u4:NB_ATTENTE_A_8 + i1:u4:NB_ATTENTE_A_9 + i1:u4:NB_ATTENTE_A_10 + i1:u4:NB_ATTENTE_A_11 + i1:u4:NB_ATTENTE_A_12 + i1:u4:NB_ATTENTE_A_13 + i1:u4:NB_ATTENTE_A_14 + i1:u4:NB_ATTENTE_A_15 + i1:u4:NB_ATTENTE_A_16 + i1:u4:NB_ATTENTE_A_17 + i1:u4:NB_ATTENTE_A_18 + i1:u4:NB_ATTENTE_A_19 + i1:u4:NB_ATTENTE_A_20 + i2:u5:NB_ATTENTE_A_0 = 1
invariant :i0:u1:SUR_PONT_A + i0:u1:CAPACITE + -1'i0:u1:SORTI_B + -1'i2:u3:ATTENTE_B + -1'i2:u3:ROUTE_B = -10
invariant :i0:u1:SUR_PONT_B + i0:u1:SORTI_B + i2:u3:ATTENTE_B + i2:u3:ROUTE_B = 20
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12618 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 98 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP0==true)))U(X(<>(<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7809 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56593 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-01 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 87 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 340 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>((LTLAP3==true)))U((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 366 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](([]((LTLAP5==true)))U(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 69130 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 65 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(<>([](<>((LTLAP7==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 82 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 325 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>([]([]((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 324 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](X([]((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 61 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 323 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>(<>(<>((LTLAP12==true)))))U((<>((LTLAP13==true)))U((LTLAP14==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 351 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10905 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 378 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527611753940

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 4:31:18 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 29, 2018 4:31:18 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 4:31:18 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 225 ms
May 29, 2018 4:31:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 68 places.
May 29, 2018 4:31:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 548 transitions.
May 29, 2018 4:31:18 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 89 ms
May 29, 2018 4:31:19 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 29, 2018 4:31:19 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 357 ms
May 29, 2018 4:31:19 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 207 ms
Begin: Tue May 29 16:31:20 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Tue May 29 16:31:20 2018
network size: 68 nodes, 950 links, 1096 weight
quality increased from -0.0770205 to 0.214736
end computation: Tue May 29 16:31:20 2018
level 1:
start computation: Tue May 29 16:31:20 2018
network size: 6 nodes, 30 links, 1096 weight
quality increased from 0.214736 to 0.240308
end computation: Tue May 29 16:31:20 2018
level 2:
start computation: Tue May 29 16:31:20 2018
network size: 3 nodes, 9 links, 1096 weight
quality increased from 0.240308 to 0.240308
end computation: Tue May 29 16:31:20 2018
End: Tue May 29 16:31:20 2018
Total duration: 0 sec
0.240308
May 29, 2018 4:31:20 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 29, 2018 4:31:20 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 205 ms
May 29, 2018 4:31:20 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 29, 2018 4:31:22 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 1031 redundant transitions.
May 29, 2018 4:31:22 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 27 ms
May 29, 2018 4:31:22 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 22 ms
May 29, 2018 4:31:22 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 548 transitions.
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 53 ms
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 467 ms
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/548 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 118 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 29, 2018 4:31:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 69 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 4:31:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 548 transitions.
May 29, 2018 4:31:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/548) took 514 ms. Total solver calls (SAT/UNSAT): 481(221/260)
May 29, 2018 4:31:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/548) took 3677 ms. Total solver calls (SAT/UNSAT): 5236(351/4885)
May 29, 2018 4:31:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/548) took 6919 ms. Total solver calls (SAT/UNSAT): 10417(484/9933)
May 29, 2018 4:31:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/548) took 10205 ms. Total solver calls (SAT/UNSAT): 16137(517/15620)
May 29, 2018 4:31:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/548) took 14085 ms. Total solver calls (SAT/UNSAT): 21712(827/20885)
May 29, 2018 4:32:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/548) took 17227 ms. Total solver calls (SAT/UNSAT): 26005(1124/24881)
May 29, 2018 4:32:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/548) took 20487 ms. Total solver calls (SAT/UNSAT): 30217(1421/28796)
May 29, 2018 4:32:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(71/548) took 23502 ms. Total solver calls (SAT/UNSAT): 34962(1487/33475)
May 29, 2018 4:32:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/548) took 26709 ms. Total solver calls (SAT/UNSAT): 40572(1487/39085)
May 29, 2018 4:32:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(96/548) took 29929 ms. Total solver calls (SAT/UNSAT): 46487(1487/45000)
May 29, 2018 4:32:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(109/548) took 32975 ms. Total solver calls (SAT/UNSAT): 52233(1487/50746)
May 29, 2018 4:32:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/548) took 36095 ms. Total solver calls (SAT/UNSAT): 58232(1487/56745)
May 29, 2018 4:32:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/548) took 39163 ms. Total solver calls (SAT/UNSAT): 64035(1487/62548)
May 29, 2018 4:32:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/548) took 42367 ms. Total solver calls (SAT/UNSAT): 70427(1487/68940)
May 29, 2018 4:32:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(169/548) took 45456 ms. Total solver calls (SAT/UNSAT): 76563(1487/75076)
May 29, 2018 4:32:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(186/548) took 48571 ms. Total solver calls (SAT/UNSAT): 82802(1487/81315)
May 29, 2018 4:32:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(202/548) took 51652 ms. Total solver calls (SAT/UNSAT): 88410(1487/86923)
May 29, 2018 4:32:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(220/548) took 54696 ms. Total solver calls (SAT/UNSAT): 94413(1487/92926)
May 29, 2018 4:32:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(238/548) took 57758 ms. Total solver calls (SAT/UNSAT): 100092(1487/98605)
May 29, 2018 4:32:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(256/548) took 60768 ms. Total solver calls (SAT/UNSAT): 105447(1487/103960)
May 29, 2018 4:32:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(276/548) took 63917 ms. Total solver calls (SAT/UNSAT): 111017(1487/109530)
May 29, 2018 4:32:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(297/548) took 66985 ms. Total solver calls (SAT/UNSAT): 116435(1487/114948)
May 29, 2018 4:32:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(320/548) took 70076 ms. Total solver calls (SAT/UNSAT): 121863(1487/120376)
May 29, 2018 4:32:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(345/548) took 73096 ms. Total solver calls (SAT/UNSAT): 127163(1487/125676)
May 29, 2018 4:33:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(374/548) took 76187 ms. Total solver calls (SAT/UNSAT): 132528(1487/131041)
May 29, 2018 4:33:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(407/548) took 79222 ms. Total solver calls (SAT/UNSAT): 137610(1487/136123)
May 29, 2018 4:33:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(447/548) took 82254 ms. Total solver calls (SAT/UNSAT): 142310(1487/140823)
May 29, 2018 4:33:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(504/548) took 85256 ms. Total solver calls (SAT/UNSAT): 146243(1487/144756)
May 29, 2018 4:33:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 86585 ms. Total solver calls (SAT/UNSAT): 147083(1507/145576)
May 29, 2018 4:33:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 548 transitions.
May 29, 2018 4:33:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1503 ms. Total solver calls (SAT/UNSAT): 85(0/85)
May 29, 2018 4:33:13 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 111088ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V20P10N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V20P10N10.tgz
mv BridgeAndVehicles-PT-V20P10N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is BridgeAndVehicles-PT-V20P10N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-ebro-152732379600078"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;