Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 33K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.9K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 44K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 107K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.1K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 598K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-PT-V20P20N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r224-ebro-152732378700084
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527565880996

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F(F((F("(((CAPACITE>=20)&&(VIDANGE_1>=1))||((CAPACITE>=20)&&(VIDANGE_2>=1)))"))U(X("(((((((((((((((((((((((NB_ATTENTE_A_1>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1))||((((NB_ATTENTE_A_2>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_3>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_4>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_5>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_6>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_7>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_8>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_9>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_10>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_11>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_12>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_13>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_14>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_15>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_16>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_17>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_18>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_19>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_20>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))"))))))
Formula 0 simplified : !F(F"(((CAPACITE>=20)&&(VIDANGE_1>=1))||((CAPACITE>=20)&&(VIDANGE_2>=1)))" U X"(((((((((((((((((((((((NB_ATTENTE_A_1>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1))||((((NB_ATTENTE_A_2>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_3>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_4>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_5>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_6>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_7>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_8>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_9>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_10>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_11>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_12>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_13>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_14>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_15>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_16>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_17>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_18>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_19>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_20>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 130
// Phase 1: matrix 130 rows 68 cols
invariant :ATTENTE_B + SUR_PONT_B + SORTI_B + ROUTE_B = 20
invariant :SUR_PONT_A + CAPACITE + -1'ATTENTE_B + -1'SORTI_B + -1'ROUTE_B = 0
invariant :CONTROLEUR_1 + CONTROLEUR_2 + CHOIX_1 + CHOIX_2 + VIDANGE_1 + VIDANGE_2 = 1
invariant :COMPTEUR_0 + COMPTEUR_1 + COMPTEUR_2 + COMPTEUR_3 + COMPTEUR_4 + COMPTEUR_5 + COMPTEUR_6 + COMPTEUR_7 + COMPTEUR_8 + COMPTEUR_9 + COMPTEUR_10 = 1
invariant :ROUTE_A + ATTENTE_A + SORTI_A + -1'CAPACITE + ATTENTE_B + SORTI_B + ROUTE_B = 20
invariant :NB_ATTENTE_A_0 + NB_ATTENTE_A_1 + NB_ATTENTE_A_2 + NB_ATTENTE_A_3 + NB_ATTENTE_A_4 + NB_ATTENTE_A_5 + NB_ATTENTE_A_6 + NB_ATTENTE_A_7 + NB_ATTENTE_A_8 + NB_ATTENTE_A_9 + NB_ATTENTE_A_10 + NB_ATTENTE_A_11 + NB_ATTENTE_A_12 + NB_ATTENTE_A_13 + NB_ATTENTE_A_14 + NB_ATTENTE_A_15 + NB_ATTENTE_A_16 + NB_ATTENTE_A_17 + NB_ATTENTE_A_18 + NB_ATTENTE_A_19 + NB_ATTENTE_A_20 = 1
invariant :NB_ATTENTE_B_0 + NB_ATTENTE_B_1 + NB_ATTENTE_B_2 + NB_ATTENTE_B_3 + NB_ATTENTE_B_4 + NB_ATTENTE_B_5 + NB_ATTENTE_B_6 + NB_ATTENTE_B_7 + NB_ATTENTE_B_8 + NB_ATTENTE_B_9 + NB_ATTENTE_B_10 + NB_ATTENTE_B_11 + NB_ATTENTE_B_12 + NB_ATTENTE_B_13 + NB_ATTENTE_B_14 + NB_ATTENTE_B_15 + NB_ATTENTE_B_16 + NB_ATTENTE_B_17 + NB_ATTENTE_B_18 + NB_ATTENTE_B_19 + NB_ATTENTE_B_20 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12464 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 108 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(<>((<>((LTLAP0==true)))U(X((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7726 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP2==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 463 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP3==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 51 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-02 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](((LTLAP4==true))U(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 88195 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP0==true)))U((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7248 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-04 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](([](<>((LTLAP4==true))))U(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 482 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(X(<>((LTLAP7==true)))))U((X((LTLAP4==true)))U((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 9105 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 423 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(X([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 76 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (((LTLAP9==true))U(<>((LTLAP10==true))))U(<>(X([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []((X(X((LTLAP12==true))))U((LTLAP13==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 81 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP14==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 67 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 62 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X(<>((LTLAP16==true))))U([]((LTLAP17==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 73 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP18==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP19==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA BridgeAndVehicles-PT-V20P20N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527566142872

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 3:51:24 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 29, 2018 3:51:24 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 3:51:24 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 186 ms
May 29, 2018 3:51:24 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 68 places.
May 29, 2018 3:51:24 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 548 transitions.
May 29, 2018 3:51:25 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 69 ms
May 29, 2018 3:51:25 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 350 ms
May 29, 2018 3:51:25 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 9 ms
May 29, 2018 3:51:25 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 23 ms
May 29, 2018 3:51:26 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 548 transitions.
May 29, 2018 3:51:26 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 69 ms
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 508 ms
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/548 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 99 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 29, 2018 3:51:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 55 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:51:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 548 transitions.
May 29, 2018 3:51:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/548) took 577 ms. Total solver calls (SAT/UNSAT): 523(263/260)
May 29, 2018 3:51:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/548) took 3819 ms. Total solver calls (SAT/UNSAT): 5185(758/4427)
May 29, 2018 3:51:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/548) took 6960 ms. Total solver calls (SAT/UNSAT): 9261(1198/8063)
May 29, 2018 3:52:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/548) took 10159 ms. Total solver calls (SAT/UNSAT): 13451(1436/12015)
May 29, 2018 3:52:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/548) took 13355 ms. Total solver calls (SAT/UNSAT): 19116(1458/17658)
May 29, 2018 3:52:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/548) took 16559 ms. Total solver calls (SAT/UNSAT): 23611(1831/21780)
May 29, 2018 3:52:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/548) took 19868 ms. Total solver calls (SAT/UNSAT): 28336(2141/26195)
May 29, 2018 3:52:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/548) took 22938 ms. Total solver calls (SAT/UNSAT): 33005(2389/30616)
May 29, 2018 3:52:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(78/548) took 26203 ms. Total solver calls (SAT/UNSAT): 38219(2389/35830)
May 29, 2018 3:52:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/548) took 29358 ms. Total solver calls (SAT/UNSAT): 43769(2389/41380)
May 29, 2018 3:52:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(103/548) took 32489 ms. Total solver calls (SAT/UNSAT): 49619(2389/47230)
May 29, 2018 3:52:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/548) took 35581 ms. Total solver calls (SAT/UNSAT): 55300(2389/52911)
May 29, 2018 3:52:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/548) took 39076 ms. Total solver calls (SAT/UNSAT): 59975(2389/57586)
May 29, 2018 3:52:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(131/548) took 42195 ms. Total solver calls (SAT/UNSAT): 61645(2389/59256)
May 29, 2018 3:52:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/548) took 45204 ms. Total solver calls (SAT/UNSAT): 62474(2389/60085)
May 29, 2018 3:52:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(140/548) took 48715 ms. Total solver calls (SAT/UNSAT): 65344(2389/62955)
May 29, 2018 3:52:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(152/548) took 51825 ms. Total solver calls (SAT/UNSAT): 70150(2389/67761)
May 29, 2018 3:52:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(167/548) took 54951 ms. Total solver calls (SAT/UNSAT): 75955(2389/73566)
May 29, 2018 3:52:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(183/548) took 58051 ms. Total solver calls (SAT/UNSAT): 81899(2389/79510)
May 29, 2018 3:52:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(198/548) took 61064 ms. Total solver calls (SAT/UNSAT): 87239(2389/84850)
May 29, 2018 3:52:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(214/548) took 64148 ms. Total solver calls (SAT/UNSAT): 92687(2389/90298)
May 29, 2018 3:52:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/548) took 67280 ms. Total solver calls (SAT/UNSAT): 98195(2389/95806)
May 29, 2018 3:53:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(243/548) took 70499 ms. Total solver calls (SAT/UNSAT): 101909(2389/99520)
May 29, 2018 3:53:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(260/548) took 73594 ms. Total solver calls (SAT/UNSAT): 106924(2389/104535)
May 29, 2018 3:53:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(279/548) took 76671 ms. Total solver calls (SAT/UNSAT): 112187(2389/109798)
May 29, 2018 3:53:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(299/548) took 79695 ms. Total solver calls (SAT/UNSAT): 117337(2389/114948)
May 29, 2018 3:53:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(320/548) took 82777 ms. Total solver calls (SAT/UNSAT): 122314(2389/119925)
May 29, 2018 3:53:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(333/548) took 85855 ms. Total solver calls (SAT/UNSAT): 125174(2389/122785)
May 29, 2018 3:53:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(359/548) took 88913 ms. Total solver calls (SAT/UNSAT): 130387(2389/127998)
May 29, 2018 3:53:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(389/548) took 91926 ms. Total solver calls (SAT/UNSAT): 135562(2389/133173)
May 29, 2018 3:53:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(424/548) took 94988 ms. Total solver calls (SAT/UNSAT): 140462(2389/138073)
May 29, 2018 3:53:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(466/548) took 98013 ms. Total solver calls (SAT/UNSAT): 144725(2389/142336)
May 29, 2018 3:53:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(495/548) took 101024 ms. Total solver calls (SAT/UNSAT): 146639(2389/144250)
May 29, 2018 3:53:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 103004 ms. Total solver calls (SAT/UNSAT): 147965(2389/145576)
May 29, 2018 3:53:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 548 transitions.
May 29, 2018 3:53:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 2016 ms. Total solver calls (SAT/UNSAT): 85(0/85)
May 29, 2018 3:53:35 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 129344ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V20P20N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V20P20N10.tgz
mv BridgeAndVehicles-PT-V20P20N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-PT-V20P20N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r224-ebro-152732378700084"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;