fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r224-ebro-152732378700076
Last Updated
June 26, 2018

About the Execution of ITS-Tools for BridgeAndVehicles-PT-V10P10N10

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15753.920 85785.00 188932.00 243.90 FFFFFTFTFFFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.................
/home/mcc/execution
total 668K
-rw-r--r-- 1 mcc users 5.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 8.4K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 27K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 311K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-PT-V10P10N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r224-ebro-152732378700076
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527564656908

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G(X(X(F("((((((((((((ROUTE_A>=1)&&(NB_ATTENTE_A_0>=1))||((ROUTE_A>=1)&&(NB_ATTENTE_A_1>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_2>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_3>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_4>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_5>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_6>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_7>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_8>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_9>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_10>=1)))"))))))
Formula 0 simplified : !GXXF"((((((((((((ROUTE_A>=1)&&(NB_ATTENTE_A_0>=1))||((ROUTE_A>=1)&&(NB_ATTENTE_A_1>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_2>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_3>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_4>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_5>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_6>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_7>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_8>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_9>=1)))||((ROUTE_A>=1)&&(NB_ATTENTE_A_10>=1)))"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 90
// Phase 1: matrix 90 rows 48 cols
invariant :ROUTE_A + ATTENTE_A + SORTI_A + -1'CAPACITE + ATTENTE_B + SORTI_B + ROUTE_B = 10
invariant :COMPTEUR_0 + COMPTEUR_1 + COMPTEUR_2 + COMPTEUR_3 + COMPTEUR_4 + COMPTEUR_5 + COMPTEUR_6 + COMPTEUR_7 + COMPTEUR_8 + COMPTEUR_9 + COMPTEUR_10 = 1
invariant :NB_ATTENTE_B_0 + NB_ATTENTE_B_1 + NB_ATTENTE_B_2 + NB_ATTENTE_B_3 + NB_ATTENTE_B_4 + NB_ATTENTE_B_5 + NB_ATTENTE_B_6 + NB_ATTENTE_B_7 + NB_ATTENTE_B_8 + NB_ATTENTE_B_9 + NB_ATTENTE_B_10 = 1
invariant :CONTROLEUR_1 + CONTROLEUR_2 + CHOIX_1 + CHOIX_2 + VIDANGE_1 + VIDANGE_2 = 1
invariant :SUR_PONT_A + CAPACITE + -1'ATTENTE_B + -1'SORTI_B + -1'ROUTE_B = 0
invariant :NB_ATTENTE_A_0 + NB_ATTENTE_A_1 + NB_ATTENTE_A_2 + NB_ATTENTE_A_3 + NB_ATTENTE_A_4 + NB_ATTENTE_A_5 + NB_ATTENTE_A_6 + NB_ATTENTE_A_7 + NB_ATTENTE_A_8 + NB_ATTENTE_A_9 + NB_ATTENTE_A_10 = 1
invariant :ATTENTE_B + SUR_PONT_B + SORTI_B + ROUTE_B = 10
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 7154 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 65 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(X(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 78 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP0==true))U((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 164 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X([](X((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 41 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](<>([](X((LTLAP3==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 40 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](((LTLAP4==true))U(X(X((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 41 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(<>(X(((LTLAP1==true))U((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 511 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(X((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 19831 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 477 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 36 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X([](<>(X((LTLAP8==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 35 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](<>((LTLAP9==true))))U((LTLAP10==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 115 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 103 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (([]((LTLAP12==true)))U((LTLAP5==true)))U((LTLAP13==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 115 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(((LTLAP14==true))U((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 292 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP16==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 37 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 105 ms.
FORMULA BridgeAndVehicles-PT-V10P10N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527564742693

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 3:31:00 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 29, 2018 3:31:00 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 3:31:00 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 184 ms
May 29, 2018 3:31:00 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 48 places.
May 29, 2018 3:31:01 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 288 transitions.
May 29, 2018 3:31:01 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 62 ms
May 29, 2018 3:31:01 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 192 ms
May 29, 2018 3:31:01 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 32 ms
May 29, 2018 3:31:01 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 16 ms
May 29, 2018 3:31:02 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 288 transitions.
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 43 ms
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 48 variables to be positive in 363 ms
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 288 transitions.
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/288 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 97 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 288 transitions.
May 29, 2018 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 20 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:31:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 288 transitions.
May 29, 2018 3:31:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/288) took 258 ms. Total solver calls (SAT/UNSAT): 263(133/130)
May 29, 2018 3:31:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/288) took 3381 ms. Total solver calls (SAT/UNSAT): 4506(528/3978)
May 29, 2018 3:31:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/288) took 6455 ms. Total solver calls (SAT/UNSAT): 9200(899/8301)
May 29, 2018 3:31:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/288) took 9536 ms. Total solver calls (SAT/UNSAT): 12830(899/11931)
May 29, 2018 3:31:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/288) took 12749 ms. Total solver calls (SAT/UNSAT): 14900(899/14001)
May 29, 2018 3:31:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/288) took 15902 ms. Total solver calls (SAT/UNSAT): 16015(899/15116)
May 29, 2018 3:31:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(76/288) took 19264 ms. Total solver calls (SAT/UNSAT): 18170(899/17271)
May 29, 2018 3:31:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(85/288) took 22298 ms. Total solver calls (SAT/UNSAT): 20024(899/19125)
May 29, 2018 3:31:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/288) took 25556 ms. Total solver calls (SAT/UNSAT): 22559(899/21660)
May 29, 2018 3:31:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/288) took 28595 ms. Total solver calls (SAT/UNSAT): 27605(899/26706)
May 29, 2018 3:31:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(161/288) took 31644 ms. Total solver calls (SAT/UNSAT): 32450(899/31551)
May 29, 2018 3:31:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(205/288) took 34660 ms. Total solver calls (SAT/UNSAT): 37004(899/36105)
May 29, 2018 3:31:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(274/288) took 37683 ms. Total solver calls (SAT/UNSAT): 40247(899/39348)
May 29, 2018 3:31:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 38029 ms. Total solver calls (SAT/UNSAT): 40325(899/39426)
May 29, 2018 3:31:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 288 transitions.
May 29, 2018 3:31:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 597 ms. Total solver calls (SAT/UNSAT): 45(0/45)
May 29, 2018 3:31:52 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 51030ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V10P10N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V10P10N10.tgz
mv BridgeAndVehicles-PT-V10P10N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-PT-V10P10N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r224-ebro-152732378700076"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;