Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.8K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 122 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 360 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_pt
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 5 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 39K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-COL-V20P10N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r224-ebro-152732378700038
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-COL-V20P10N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527549547796

23:19:11.347 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
23:19:11.351 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(((X("(((CAPACITE.CAPACITE_0>=10)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=10)&&(sens1.VIDANGE_1>=1)))"))U(X(F(F("(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))"))))))
Formula 0 simplified : !(X"(((CAPACITE.CAPACITE_0>=10)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=10)&&(sens1.VIDANGE_1>=1)))" U XF"(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))")
built 159 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 130
// Phase 1: matrix 130 rows 68 cols
invariant :sens0:CONTROLEUR_0 + sens0:CHOIX_0 + sens0:VIDANGE_0 + sens1:CONTROLEUR_1 + sens1:CHOIX_1 + sens1:VIDANGE_1 = 1
invariant :SUR_PONT_B:SUR_PONT_B_0 + ATTENTE_B:ATTENTE_B_0 + ROUTE_B:ROUTE_B_0 + SORTI_B:SORTI_B_0 = 20
invariant :SORTI_A:SORTI_A_0 + ROUTE_A:ROUTE_A_0 + ATTENTE_A:ATTENTE_A_0 + SUR_PONT_A:SUR_PONT_A_0 = 20
invariant :compteur0:COMPTEUR_0 + compteur1:COMPTEUR_1 + compteur2:COMPTEUR_2 + compteur3:COMPTEUR_3 + compteur4:COMPTEUR_4 + compteur5:COMPTEUR_5 + compteur6:COMPTEUR_6 + compteur7:COMPTEUR_7 + compteur8:COMPTEUR_8 + compteur9:COMPTEUR_9 + compteur10:COMPTEUR_10 = 1
invariant :voitureA0:NB_ATTENTE_A_0 + voitureA1:NB_ATTENTE_A_1 + voitureA2:NB_ATTENTE_A_2 + voitureA3:NB_ATTENTE_A_3 + voitureA4:NB_ATTENTE_A_4 + voitureA5:NB_ATTENTE_A_5 + voitureA6:NB_ATTENTE_A_6 + voitureA7:NB_ATTENTE_A_7 + voitureA8:NB_ATTENTE_A_8 + voitureA9:NB_ATTENTE_A_9 + voitureA10:NB_ATTENTE_A_10 + voitureA11:NB_ATTENTE_A_11 + voitureA12:NB_ATTENTE_A_12 + voitureA13:NB_ATTENTE_A_13 + voitureA14:NB_ATTENTE_A_14 + voitureA15:NB_ATTENTE_A_15 + voitureA16:NB_ATTENTE_A_16 + voitureA17:NB_ATTENTE_A_17 + voitureA18:NB_ATTENTE_A_18 + voitureA19:NB_ATTENTE_A_19 + voitureA20:NB_ATTENTE_A_20 = 1
invariant :CAPACITE:CAPACITE_0 + SUR_PONT_A:SUR_PONT_A_0 + -1'ATTENTE_B:ATTENTE_B_0 + -1'ROUTE_B:ROUTE_B_0 + -1'SORTI_B:SORTI_B_0 = -10
invariant :voitureB0:NB_ATTENTE_B_0 + voitureB1:NB_ATTENTE_B_1 + voitureB2:NB_ATTENTE_B_2 + voitureB3:NB_ATTENTE_B_3 + voitureB4:NB_ATTENTE_B_4 + voitureB5:NB_ATTENTE_B_5 + voitureB6:NB_ATTENTE_B_6 + voitureB7:NB_ATTENTE_B_7 + voitureB8:NB_ATTENTE_B_8 + voitureB9:NB_ATTENTE_B_9 + voitureB10:NB_ATTENTE_B_10 + voitureB11:NB_ATTENTE_B_11 + voitureB12:NB_ATTENTE_B_12 + voitureB13:NB_ATTENTE_B_13 + voitureB14:NB_ATTENTE_B_14 + voitureB15:NB_ATTENTE_B_15 + voitureB16:NB_ATTENTE_B_16 + voitureB17:NB_ATTENTE_B_17 + voitureB18:NB_ATTENTE_B_18 + voitureB19:NB_ATTENTE_B_19 + voitureB20:NB_ATTENTE_B_20 = 1
Reverse transition relation is NOT exact ! Due to transitions enregistrement_A, liberation_A, basculement, liberation_B, enregistrement_B, altern_cpt, timeout_A, timeout_B, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/3/8/11
Computing Next relation with stutter on 20 deadlock states
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
5973 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,59.777,984688,1,0,2.17569e+06,1086,1450,2.51228e+06,89,3371,8545836
no accepting run found
Formula 0 is TRUE no accepting run found.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((F("(((CAPACITE.CAPACITE_0>=10)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=10)&&(sens1.VIDANGE_1>=1)))")))
Formula 1 simplified : !F"(((CAPACITE.CAPACITE_0>=10)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=10)&&(sens1.VIDANGE_1>=1)))"
Computing Next relation with stutter on 20 deadlock states
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
184 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,61.6269,1040656,1,0,2.3722e+06,1086,1482,2.62067e+06,89,3371,9056395
no accepting run found
Formula 1 is TRUE no accepting run found.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((G(X("(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))"))))
Formula 2 simplified : !GX"(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))"
Computing Next relation with stutter on 20 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 13301 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 86 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 98 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1136 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>((LTLAP3==true)))U((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 71 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 308 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](([]((LTLAP5==true)))U(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57920 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 65 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 308 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]([](<>((LTLAP7==true)))))U(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 30302 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 363 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 428 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((LTLAP8==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 307 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(X(<>(X((LTLAP7==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4079 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]([](((LTLAP0==true))U((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 430 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X([]([]((LTLAP6==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 70 ms.
FORMULA BridgeAndVehicles-COL-V20P10N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527549776349

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 11:19:10 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 11:19:10 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 11:19:10 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 28, 2018 11:19:11 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1177 ms
May 28, 2018 11:19:11 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 15 places.
May 28, 2018 11:19:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 28, 2018 11:19:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :sens->CONTROLEUR,CHOIX,VIDANGE,
compteur->COMPTEUR,
Dot->CAPACITE,SORTI_A,ROUTE_A,ATTENTE_A,SUR_PONT_A,SUR_PONT_B,ATTENTE_B,ROUTE_B,SORTI_B,
voitureA->NB_ATTENTE_A,
voitureB->NB_ATTENTE_B,

May 28, 2018 11:19:12 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 11 transitions.
May 28, 2018 11:19:12 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 28, 2018 11:19:12 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 11 ms
May 28, 2018 11:19:12 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 11:19:12 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 11:19:12 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 59.0 instantiations of transitions. Total transitions/syncs built is 178
May 28, 2018 11:19:12 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 148 ms
May 28, 2018 11:19:14 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays NB_ATTENTE_A, NB_ATTENTE_B, CONTROLEUR, CHOIX, COMPTEUR, VIDANGE to variables to allow decomposition.
May 28, 2018 11:19:14 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 125 redundant transitions.
May 28, 2018 11:19:15 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 13 ms
May 28, 2018 11:19:15 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 62 ms
May 28, 2018 11:19:16 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 11 transitions. Expanding to a total of 631 deterministic transitions.
May 28, 2018 11:19:16 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 15 ms.
May 28, 2018 11:19:16 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 59 ms
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 488 ms
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/548 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 112 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 28, 2018 11:19:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 41 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:19:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 548 transitions.
May 28, 2018 11:19:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/548) took 588 ms. Total solver calls (SAT/UNSAT): 481(221/260)
May 28, 2018 11:19:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/548) took 3694 ms. Total solver calls (SAT/UNSAT): 4765(338/4427)
May 28, 2018 11:19:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/548) took 7000 ms. Total solver calls (SAT/UNSAT): 9430(468/8962)
May 28, 2018 11:19:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/548) took 10147 ms. Total solver calls (SAT/UNSAT): 14643(562/14081)
May 28, 2018 11:19:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/548) took 13657 ms. Total solver calls (SAT/UNSAT): 18234(576/17658)
May 28, 2018 11:19:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/548) took 16792 ms. Total solver calls (SAT/UNSAT): 22729(949/21780)
May 28, 2018 11:19:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/548) took 19814 ms. Total solver calls (SAT/UNSAT): 27454(1259/26195)
May 28, 2018 11:19:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/548) took 22895 ms. Total solver calls (SAT/UNSAT): 32123(1507/30616)
May 28, 2018 11:19:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/548) took 25951 ms. Total solver calls (SAT/UNSAT): 37805(1507/36298)
May 28, 2018 11:20:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(92/548) took 28970 ms. Total solver calls (SAT/UNSAT): 43798(1507/42291)
May 28, 2018 11:20:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(105/548) took 32002 ms. Total solver calls (SAT/UNSAT): 49622(1507/48115)
May 28, 2018 11:20:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(118/548) took 35076 ms. Total solver calls (SAT/UNSAT): 55277(1507/53770)
May 28, 2018 11:20:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(132/548) took 38262 ms. Total solver calls (SAT/UNSAT): 61178(1507/59671)
May 28, 2018 11:20:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(138/548) took 41380 ms. Total solver calls (SAT/UNSAT): 63647(1507/62140)
May 28, 2018 11:20:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(150/548) took 44545 ms. Total solver calls (SAT/UNSAT): 68477(1507/66970)
May 28, 2018 11:20:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(159/548) took 47601 ms. Total solver calls (SAT/UNSAT): 72005(1507/70498)
May 28, 2018 11:20:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(174/548) took 50635 ms. Total solver calls (SAT/UNSAT): 77705(1507/76198)
May 28, 2018 11:20:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(190/548) took 53651 ms. Total solver calls (SAT/UNSAT): 83537(1507/82030)
May 28, 2018 11:20:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(207/548) took 56795 ms. Total solver calls (SAT/UNSAT): 89453(1507/87946)
May 28, 2018 11:20:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(223/548) took 59834 ms. Total solver calls (SAT/UNSAT): 94757(1507/93250)
May 28, 2018 11:20:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(240/548) took 62887 ms. Total solver calls (SAT/UNSAT): 100112(1507/98605)
May 28, 2018 11:20:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(259/548) took 65975 ms. Total solver calls (SAT/UNSAT): 105755(1507/104248)
May 28, 2018 11:20:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(278/548) took 69036 ms. Total solver calls (SAT/UNSAT): 111037(1507/109530)
May 28, 2018 11:20:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(298/548) took 72040 ms. Total solver calls (SAT/UNSAT): 116207(1507/114700)
May 28, 2018 11:20:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(322/548) took 75048 ms. Total solver calls (SAT/UNSAT): 121883(1507/120376)
May 28, 2018 11:20:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(348/548) took 78102 ms. Total solver calls (SAT/UNSAT): 127382(1507/125875)
May 28, 2018 11:20:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(377/548) took 81112 ms. Total solver calls (SAT/UNSAT): 132718(1507/131211)
May 28, 2018 11:20:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(408/548) took 84126 ms. Total solver calls (SAT/UNSAT): 137492(1507/135985)
May 28, 2018 11:21:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(449/548) took 87167 ms. Total solver calls (SAT/UNSAT): 142330(1507/140823)
May 28, 2018 11:21:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(506/548) took 90188 ms. Total solver calls (SAT/UNSAT): 146263(1507/144756)
May 28, 2018 11:21:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 91377 ms. Total solver calls (SAT/UNSAT): 147083(1507/145576)
May 28, 2018 11:21:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 548 transitions.
May 28, 2018 11:21:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1543 ms. Total solver calls (SAT/UNSAT): 85(0/85)
May 28, 2018 11:21:06 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 110375ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V20P10N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V20P10N10.tgz
mv BridgeAndVehicles-COL-V20P10N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-COL-V20P10N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r224-ebro-152732378700038"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;