About the Execution of ITS-Tools for SafeBus-COL-06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15755.430 | 1734483.00 | 3479760.00 | 4649.20 | TFFFFFFFFTFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 216K
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.3K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 105 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 343 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 42K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is SafeBus-COL-06, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r212-smll-152732263400518
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SafeBus-COL-06-LTLFireability-00
FORMULA_NAME SafeBus-COL-06-LTLFireability-01
FORMULA_NAME SafeBus-COL-06-LTLFireability-02
FORMULA_NAME SafeBus-COL-06-LTLFireability-03
FORMULA_NAME SafeBus-COL-06-LTLFireability-04
FORMULA_NAME SafeBus-COL-06-LTLFireability-05
FORMULA_NAME SafeBus-COL-06-LTLFireability-06
FORMULA_NAME SafeBus-COL-06-LTLFireability-07
FORMULA_NAME SafeBus-COL-06-LTLFireability-08
FORMULA_NAME SafeBus-COL-06-LTLFireability-09
FORMULA_NAME SafeBus-COL-06-LTLFireability-10
FORMULA_NAME SafeBus-COL-06-LTLFireability-11
FORMULA_NAME SafeBus-COL-06-LTLFireability-12
FORMULA_NAME SafeBus-COL-06-LTLFireability-13
FORMULA_NAME SafeBus-COL-06-LTLFireability-14
FORMULA_NAME SafeBus-COL-06-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1527832449858
05:54:12.820 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
05:54:12.823 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(F(("(((((((It0.RMC_0>=1)&&(It0.wait_cable_0>=1))||((It1.RMC_1>=1)&&(It1.wait_cable_1>=1)))||((It2.RMC_2>=1)&&(It2.wait_cable_2>=1)))||((It3.RMC_3>=1)&&(It3.wait_cable_3>=1)))||((It4.RMC_4>=1)&&(It4.wait_cable_4>=1)))||((It5.RMC_5>=1)&&(It5.wait_cable_5>=1)))")U("(((((((It0.FMC_0>=1)&&(It0.cable_used_0>=1))||((It1.FMC_1>=1)&&(It1.cable_used_1>=1)))||((It2.FMC_2>=1)&&(It2.cable_used_2>=1)))||((It3.FMC_3>=1)&&(It3.cable_used_3>=1)))||((It4.FMC_4>=1)&&(It4.cable_used_4>=1)))||((It5.FMC_5>=1)&&(It5.cable_used_5>=1)))")))))
Formula 0 simplified : !XF("(((((((It0.RMC_0>=1)&&(It0.wait_cable_0>=1))||((It1.RMC_1>=1)&&(It1.wait_cable_1>=1)))||((It2.RMC_2>=1)&&(It2.wait_cable_2>=1)))||((It3.RMC_3>=1)&&(It3.wait_cable_3>=1)))||((It4.RMC_4>=1)&&(It4.wait_cable_4>=1)))||((It5.RMC_5>=1)&&(It5.wait_cable_5>=1)))" U "(((((((It0.FMC_0>=1)&&(It0.cable_used_0>=1))||((It1.FMC_1>=1)&&(It1.cable_used_1>=1)))||((It2.FMC_2>=1)&&(It2.cable_used_2>=1)))||((It3.FMC_3>=1)&&(It3.cable_used_3>=1)))||((It4.FMC_4>=1)&&(It4.cable_used_4>=1)))||((It5.FMC_5>=1)&&(It5.cable_used_5>=1)))")
built 254 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 248
// Phase 1: matrix 248 rows 144 cols
invariant :Dom30:AMC_30 + Dom30:wait_ack_30 + Dom31:AMC_31 + Dom31:wait_ack_31 + Dom32:AMC_32 + Dom32:wait_ack_32 + Dom33:AMC_33 + Dom33:wait_ack_33 + Dom34:AMC_34 + Dom34:wait_ack_34 + Dom35:AMC_35 + Dom35:wait_ack_35 + It5:listen_5 + It5:RMC_5 + It5:PMC_5 + It5:wait_msg_5 + It5:loop_em_5 = 1
invariant :Dom2:AMC_2 + -1'Dom3:AMC_3 + Dom8:AMC_8 + -1'Dom9:AMC_9 + Dom14:AMC_14 + -1'Dom15:AMC_15 + Dom20:AMC_20 + -1'Dom21:AMC_21 + Dom26:AMC_26 + -1'Dom27:AMC_27 + Dom32:AMC_32 + -1'Dom33:AMC_33 + It0:Cpt1_0 + It1:Cpt1_1 + It2:Cpt1_2 + It3:Cpt2_3 + It4:Cpt1_4 + It5:Cpt1_5 = 1
invariant :Dom24:AMC_24 + Dom24:wait_ack_24 + Dom25:AMC_25 + Dom25:wait_ack_25 + Dom26:AMC_26 + Dom26:wait_ack_26 + Dom27:AMC_27 + Dom27:wait_ack_27 + Dom28:AMC_28 + Dom28:wait_ack_28 + Dom29:AMC_29 + Dom29:wait_ack_29 + It4:listen_4 + It4:RMC_4 + It4:PMC_4 + It4:wait_msg_4 + It4:loop_em_4 = 1
invariant :Dom12:wait_ack_12 + Dom13:wait_ack_13 + Dom14:wait_ack_14 + Dom15:wait_ack_15 + Dom16:wait_ack_16 + Dom17:wait_ack_17 + It2:wait_cable_2 + It2:listen_2 + It2:wait_msg_2 + It2:loop_em_2 = 1
invariant :Dom4:AMC_4 + -1'Dom5:AMC_5 + Dom10:AMC_10 + -1'Dom11:AMC_11 + Dom16:AMC_16 + -1'Dom17:AMC_17 + Dom22:AMC_22 + -1'Dom23:AMC_23 + Dom28:AMC_28 + -1'Dom29:AMC_29 + Dom34:AMC_34 + -1'Dom35:AMC_35 + It5:Cpt2_5 + -1'It5:Cpt1_5 = 0
invariant :-1'Dom0:AMC_0 + Dom5:AMC_5 + -1'Dom6:AMC_6 + Dom11:AMC_11 + -1'Dom12:AMC_12 + Dom17:AMC_17 + -1'Dom18:AMC_18 + Dom23:AMC_23 + -1'Dom24:AMC_24 + Dom29:AMC_29 + -1'Dom30:AMC_30 + Dom35:AMC_35 + It0:Cpt2_0 + -1'It0:Cpt1_0 = 0
invariant :Dom18:AMC_18 + Dom18:wait_ack_18 + Dom19:AMC_19 + Dom19:wait_ack_19 + Dom20:AMC_20 + Dom20:wait_ack_20 + Dom21:AMC_21 + Dom21:wait_ack_21 + Dom22:AMC_22 + Dom22:wait_ack_22 + Dom23:AMC_23 + Dom23:wait_ack_23 + It3:listen_3 + It3:RMC_3 + It3:PMC_3 + It3:wait_msg_3 + It3:loop_em_3 = 1
invariant :Dom30:wait_ack_30 + Dom31:wait_ack_31 + Dom32:wait_ack_32 + Dom33:wait_ack_33 + Dom34:wait_ack_34 + Dom35:wait_ack_35 + It5:wait_cable_5 + It5:listen_5 + It5:wait_msg_5 + It5:loop_em_5 = 1
invariant :-1'Dom24:AMC_24 + -1'Dom25:AMC_25 + -1'Dom26:AMC_26 + -1'Dom27:AMC_27 + -1'Dom28:AMC_28 + -1'Dom29:AMC_29 + It4:wait_cable_4 + -1'It4:RMC_4 + -1'It4:PMC_4 = 0
invariant :-1'Dom24:wait_ack_24 + -1'Dom25:wait_ack_25 + -1'Dom26:wait_ack_26 + -1'Dom27:wait_ack_27 + -1'Dom28:wait_ack_28 + -1'Dom29:wait_ack_29 + It4:cable_used_4 + -1'It4:FMC_4 + -1'It4:PMC_4 = 0
invariant :Dom6:AMC_6 + Dom6:wait_ack_6 + Dom7:AMC_7 + Dom7:wait_ack_7 + Dom8:AMC_8 + Dom8:wait_ack_8 + Dom9:AMC_9 + Dom9:wait_ack_9 + Dom10:AMC_10 + Dom10:wait_ack_10 + Dom11:AMC_11 + Dom11:wait_ack_11 + It1:listen_1 + It1:RMC_1 + It1:PMC_1 + It1:wait_msg_1 + It1:loop_em_1 = 1
invariant :It0:Cpt1_0 + It1:Cpt1_1 + It2:Cpt1_2 + It3:Cpt1_3 + It4:Cpt1_4 + It5:Cpt1_5 = 1
invariant :Dom6:wait_ack_6 + Dom7:wait_ack_7 + Dom8:wait_ack_8 + Dom9:wait_ack_9 + Dom10:wait_ack_10 + Dom11:wait_ack_11 + It1:wait_cable_1 + It1:listen_1 + It1:wait_msg_1 + It1:loop_em_1 = 1
invariant :Dom1:AMC_1 + -1'Dom2:AMC_2 + Dom7:AMC_7 + -1'Dom8:AMC_8 + Dom13:AMC_13 + -1'Dom14:AMC_14 + Dom19:AMC_19 + -1'Dom20:AMC_20 + Dom25:AMC_25 + -1'Dom26:AMC_26 + Dom31:AMC_31 + -1'Dom32:AMC_32 + It2:Cpt2_2 + -1'It2:Cpt1_2 = 0
invariant :-1'Dom0:wait_ack_0 + -1'Dom1:wait_ack_1 + -1'Dom2:wait_ack_2 + -1'Dom3:wait_ack_3 + -1'Dom4:wait_ack_4 + -1'Dom5:wait_ack_5 + It0:cable_used_0 + -1'It0:FMC_0 + -1'It0:PMC_0 = 0
invariant :-1'Dom6:wait_ack_6 + -1'Dom7:wait_ack_7 + -1'Dom8:wait_ack_8 + -1'Dom9:wait_ack_9 + -1'Dom10:wait_ack_10 + -1'Dom11:wait_ack_11 + It1:cable_used_1 + -1'It1:FMC_1 + -1'It1:PMC_1 = 0
invariant :Dom3:AMC_3 + -1'Dom4:AMC_4 + Dom9:AMC_9 + -1'Dom10:AMC_10 + Dom15:AMC_15 + -1'Dom16:AMC_16 + Dom21:AMC_21 + -1'Dom22:AMC_22 + Dom27:AMC_27 + -1'Dom28:AMC_28 + Dom33:AMC_33 + -1'Dom34:AMC_34 + It4:Cpt2_4 + -1'It4:Cpt1_4 = 0
invariant :Dom0:wait_ack_0 + Dom1:wait_ack_1 + Dom2:wait_ack_2 + Dom3:wait_ack_3 + Dom4:wait_ack_4 + Dom5:wait_ack_5 + Dom6:wait_ack_6 + Dom7:wait_ack_7 + Dom8:wait_ack_8 + Dom9:wait_ack_9 + Dom10:wait_ack_10 + Dom11:wait_ack_11 + -1'Dom12:AMC_12 + -1'Dom13:AMC_13 + -1'Dom14:AMC_14 + -1'Dom15:AMC_15 + -1'Dom16:AMC_16 + -1'Dom17:AMC_17 + Dom18:wait_ack_18 + Dom19:wait_ack_19 + Dom20:wait_ack_20 + Dom21:wait_ack_21 + Dom22:wait_ack_22 + Dom23:wait_ack_23 + Dom24:wait_ack_24 + Dom25:wait_ack_25 + Dom26:wait_ack_26 + Dom27:wait_ack_27 + Dom28:wait_ack_28 + Dom29:wait_ack_29 + Dom30:wait_ack_30 + Dom31:wait_ack_31 + Dom32:wait_ack_32 + Dom33:wait_ack_33 + Dom34:wait_ack_34 + Dom35:wait_ack_35 + cable_free:cable_free_0 + It0:FMC_0 + It0:PMC_0 + It1:FMC_1 + It1:PMC_1 + It2:FMC_2 + -1'It2:listen_2 + -1'It2:RMC_2 + -1'It2:wait_msg_2 + -1'It2:loop_em_2 + It3:FMC_3 + It3:PMC_3 + It4:FMC_4 + It4:PMC_4 + It5:FMC_5 + It5:PMC_5 = 0
invariant :-1'Dom18:AMC_18 + -1'Dom19:AMC_19 + -1'Dom20:AMC_20 + -1'Dom21:AMC_21 + -1'Dom22:AMC_22 + -1'Dom23:AMC_23 + It3:wait_cable_3 + -1'It3:RMC_3 + -1'It3:PMC_3 = 0
invariant :FMCb:FMCb_0 + It0:FMC_0 + It1:FMC_1 + It2:FMC_2 + It3:FMC_3 + It4:FMC_4 + It5:FMC_5 = 1
invariant :R_tout:R_tout_0 + S_tout:S_tout_0 = 1
invariant :Dom12:AMC_12 + Dom12:wait_ack_12 + Dom13:AMC_13 + Dom13:wait_ack_13 + Dom14:AMC_14 + Dom14:wait_ack_14 + Dom15:AMC_15 + Dom15:wait_ack_15 + Dom16:AMC_16 + Dom16:wait_ack_16 + Dom17:AMC_17 + Dom17:wait_ack_17 + It2:listen_2 + It2:RMC_2 + It2:PMC_2 + It2:wait_msg_2 + It2:loop_em_2 = 1
invariant :-1'Dom0:wait_ack_0 + -1'Dom1:wait_ack_1 + -1'Dom2:wait_ack_2 + -1'Dom3:wait_ack_3 + -1'Dom4:wait_ack_4 + -1'Dom5:wait_ack_5 + -1'Dom6:wait_ack_6 + -1'Dom7:wait_ack_7 + -1'Dom8:wait_ack_8 + -1'Dom9:wait_ack_9 + -1'Dom10:wait_ack_10 + -1'Dom11:wait_ack_11 + -1'Dom12:wait_ack_12 + -1'Dom13:wait_ack_13 + -1'Dom14:wait_ack_14 + -1'Dom15:wait_ack_15 + -1'Dom16:wait_ack_16 + -1'Dom17:wait_ack_17 + -1'Dom18:wait_ack_18 + -1'Dom19:wait_ack_19 + -1'Dom20:wait_ack_20 + -1'Dom21:wait_ack_21 + -1'Dom22:wait_ack_22 + -1'Dom23:wait_ack_23 + -1'Dom24:wait_ack_24 + -1'Dom25:wait_ack_25 + -1'Dom26:wait_ack_26 + -1'Dom27:wait_ack_27 + -1'Dom28:wait_ack_28 + -1'Dom29:wait_ack_29 + -1'Dom30:wait_ack_30 + -1'Dom31:wait_ack_31 + -1'Dom32:wait_ack_32 + -1'Dom33:wait_ack_33 + -1'Dom34:wait_ack_34 + -1'Dom35:wait_ack_35 + ACK:ACK_0 + T_out:T_out_0 + It0:MSG_0 + It1:MSG_1 + It2:MSG_2 + It3:MSG_3 + It4:MSG_4 + It5:MSG_5 = 0
invariant :-1'Dom18:wait_ack_18 + -1'Dom19:wait_ack_19 + -1'Dom20:wait_ack_20 + -1'Dom21:wait_ack_21 + -1'Dom22:wait_ack_22 + -1'Dom23:wait_ack_23 + It3:cable_used_3 + -1'It3:FMC_3 + -1'It3:PMC_3 = 0
invariant :Dom0:AMC_0 + Dom0:wait_ack_0 + Dom1:AMC_1 + Dom1:wait_ack_1 + Dom2:AMC_2 + Dom2:wait_ack_2 + Dom3:AMC_3 + Dom3:wait_ack_3 + Dom4:AMC_4 + Dom4:wait_ack_4 + Dom5:AMC_5 + Dom5:wait_ack_5 + It0:listen_0 + It0:RMC_0 + It0:PMC_0 + It0:wait_msg_0 + It0:loop_em_0 = 1
invariant :-1'Dom0:AMC_0 + -1'Dom1:AMC_1 + -1'Dom2:AMC_2 + -1'Dom3:AMC_3 + -1'Dom4:AMC_4 + -1'Dom5:AMC_5 + It0:wait_cable_0 + -1'It0:RMC_0 + -1'It0:PMC_0 = 0
invariant :Dom0:AMC_0 + -1'Dom1:AMC_1 + Dom6:AMC_6 + -1'Dom7:AMC_7 + Dom12:AMC_12 + -1'Dom13:AMC_13 + Dom18:AMC_18 + -1'Dom19:AMC_19 + Dom24:AMC_24 + -1'Dom25:AMC_25 + Dom30:AMC_30 + -1'Dom31:AMC_31 + It1:Cpt2_1 + -1'It1:Cpt1_1 = 0
invariant :-1'Dom30:wait_ack_30 + -1'Dom31:wait_ack_31 + -1'Dom32:wait_ack_32 + -1'Dom33:wait_ack_33 + -1'Dom34:wait_ack_34 + -1'Dom35:wait_ack_35 + It5:cable_used_5 + -1'It5:FMC_5 + -1'It5:PMC_5 = 0
invariant :Dom12:AMC_12 + Dom13:AMC_13 + Dom14:AMC_14 + Dom15:AMC_15 + Dom16:AMC_16 + Dom17:AMC_17 + It2:cable_used_2 + -1'It2:FMC_2 + It2:listen_2 + It2:RMC_2 + It2:wait_msg_2 + It2:loop_em_2 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 9585 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 51 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(((LTLAP0==true))U((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60713 ms.
FORMULA SafeBus-COL-06-LTLFireability-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []((<>(<>((LTLAP2==true))))U([](X((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 270 ms.
FORMULA SafeBus-COL-06-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP4==true)))U([](<>((LTLAP5==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 61 ms.
FORMULA SafeBus-COL-06-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP6==true)))U((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 32 ms.
FORMULA SafeBus-COL-06-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(((LTLAP1==true))U(X(X((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 49 ms.
FORMULA SafeBus-COL-06-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((<>((LTLAP4==true)))U(X((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 118 ms.
FORMULA SafeBus-COL-06-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 256 ms.
FORMULA SafeBus-COL-06-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP8==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 255 ms.
FORMULA SafeBus-COL-06-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 41 ms.
FORMULA SafeBus-COL-06-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](X(<>(<>((LTLAP8==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions I_reemit, C_free, I_rec1, loss_m, I_rec2, I_ask2_0, I_ask2_1, I_ask2_2, I_ask2_3, I_ask2_4, I_ask2_5, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/23/11/34
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
46261 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,462.667,6193216,1,0,1.72581e+07,85555,2383,7.7586e+06,239,484659,50938359
no accepting run found
Formula 0 is TRUE no accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((G((F(F("(((((((It0.MSG_0>=1)&&(It0.wait_msg_0>=1))||((It1.MSG_1>=1)&&(It1.wait_msg_1>=1)))||((It2.MSG_2>=1)&&(It2.wait_msg_2>=1)))||((It3.MSG_3>=1)&&(It3.wait_msg_3>=1)))||((It4.MSG_4>=1)&&(It4.wait_msg_4>=1)))||((It5.MSG_5>=1)&&(It5.wait_msg_5>=1)))")))U(G(X("((((((((((((((((((((((((((((((((((((((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom0.wait_ack_0>=1))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom6.wait_ack_6>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom12.wait_ack_12>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom18.wait_ack_18>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom24.wait_ack_24>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom30.wait_ack_30>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom1.wait_ack_1>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom7.wait_ack_7>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom13.wait_ack_13>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom19.wait_ack_19>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom25.wait_ack_25>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom31.wait_ack_31>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom2.wait_ack_2>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom8.wait_ack_8>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom14.wait_ack_14>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom20.wait_ack_20>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom26.wait_ack_26>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom32.wait_ack_32>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom3.wait_ack_3>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom9.wait_ack_9>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom15.wait_ack_15>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom21.wait_ack_21>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom27.wait_ack_27>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom33.wait_ack_33>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom4.wait_ack_4>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom10.wait_ack_10>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom16.wait_ack_16>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom22.wait_ack_22>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom28.wait_ack_28>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom34.wait_ack_34>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom5.wait_ack_5>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom11.wait_ack_11>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom17.wait_ack_17>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom23.wait_ack_23>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom29.wait_ack_29>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom35.wait_ack_35>=1)))"))))))
Formula 1 simplified : !G(F"(((((((It0.MSG_0>=1)&&(It0.wait_msg_0>=1))||((It1.MSG_1>=1)&&(It1.wait_msg_1>=1)))||((It2.MSG_2>=1)&&(It2.wait_msg_2>=1)))||((It3.MSG_3>=1)&&(It3.wait_msg_3>=1)))||((It4.MSG_4>=1)&&(It4.wait_msg_4>=1)))||((It5.MSG_5>=1)&&(It5.wait_msg_5>=1)))" U GX"((((((((((((((((((((((((((((((((((((((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom0.wait_ack_0>=1))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom6.wait_ack_6>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom12.wait_ack_12>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom18.wait_ack_18>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom24.wait_ack_24>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom30.wait_ack_30>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom1.wait_ack_1>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom7.wait_ack_7>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom13.wait_ack_13>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom19.wait_ack_19>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom25.wait_ack_25>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom31.wait_ack_31>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom2.wait_ack_2>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom8.wait_ack_8>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom14.wait_ack_14>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom20.wait_ack_20>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom26.wait_ack_26>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom32.wait_ack_32>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom3.wait_ack_3>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom9.wait_ack_9>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom15.wait_ack_15>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom21.wait_ack_21>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom27.wait_ack_27>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom33.wait_ack_33>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom4.wait_ack_4>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom10.wait_ack_10>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom16.wait_ack_16>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom22.wait_ack_22>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom28.wait_ack_28>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom34.wait_ack_34>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom5.wait_ack_5>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom11.wait_ack_11>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom17.wait_ack_17>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom23.wait_ack_23>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom29.wait_ack_29>=1)))||(((FMCb.FMCb_0>=1)&&(ACK.ACK_0>=1))&&(Dom35.wait_ack_35>=1)))")
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](X(<>(<>((LTLAP8==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((LTLAP2==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 170 ms.
FORMULA SafeBus-COL-06-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(X((LTLAP3==true))))U(X([]((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1518 ms.
FORMULA SafeBus-COL-06-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](([]((LTLAP9==true)))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 51 ms.
FORMULA SafeBus-COL-06-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 268 ms.
FORMULA SafeBus-COL-06-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](<>([]((LTLAP0==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 240 ms.
FORMULA SafeBus-COL-06-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 30 ms.
FORMULA SafeBus-COL-06-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](X(<>(<>((LTLAP8==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
4 unique states visited
4 strongly connected components in search stack
5 transitions explored
4 items max in DFS search stack
42450 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,887.169,11068840,1,0,3.05096e+07,85685,1790,1.39908e+07,157,502810,29108792
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !(((X("(((((((R_tout.R_tout_0>=1)&&(It0.MSG_0>=1))||((R_tout.R_tout_0>=1)&&(It1.MSG_1>=1)))||((R_tout.R_tout_0>=1)&&(It2.MSG_2>=1)))||((R_tout.R_tout_0>=1)&&(It3.MSG_3>=1)))||((R_tout.R_tout_0>=1)&&(It4.MSG_4>=1)))||((R_tout.R_tout_0>=1)&&(It5.MSG_5>=1)))"))U(G(F("(((((((S_tout.S_tout_0>=1)&&(It0.FMC_0>=1))||((S_tout.S_tout_0>=1)&&(It1.FMC_1>=1)))||((S_tout.S_tout_0>=1)&&(It2.FMC_2>=1)))||((S_tout.S_tout_0>=1)&&(It3.FMC_3>=1)))||((S_tout.S_tout_0>=1)&&(It4.FMC_4>=1)))||((S_tout.S_tout_0>=1)&&(It5.FMC_5>=1)))")))))
Formula 2 simplified : !(X"(((((((R_tout.R_tout_0>=1)&&(It0.MSG_0>=1))||((R_tout.R_tout_0>=1)&&(It1.MSG_1>=1)))||((R_tout.R_tout_0>=1)&&(It2.MSG_2>=1)))||((R_tout.R_tout_0>=1)&&(It3.MSG_3>=1)))||((R_tout.R_tout_0>=1)&&(It4.MSG_4>=1)))||((R_tout.R_tout_0>=1)&&(It5.MSG_5>=1)))" U GF"(((((((S_tout.S_tout_0>=1)&&(It0.FMC_0>=1))||((S_tout.S_tout_0>=1)&&(It1.FMC_1>=1)))||((S_tout.S_tout_0>=1)&&(It2.FMC_2>=1)))||((S_tout.S_tout_0>=1)&&(It3.FMC_3>=1)))||((S_tout.S_tout_0>=1)&&(It4.FMC_4>=1)))||((S_tout.S_tout_0>=1)&&(It5.FMC_5>=1)))")
3 unique states visited
3 strongly connected components in search stack
4 transitions explored
3 items max in DFS search stack
4152 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,928.697,11069084,1,0,3.05096e+07,85685,2213,1.39908e+07,171,502810,38598170
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !(((X("(((((((It0.MSG_0>=1)&&(It0.listen_0>=1))||((It1.MSG_1>=1)&&(It1.listen_1>=1)))||((It2.MSG_2>=1)&&(It2.listen_2>=1)))||((It3.MSG_3>=1)&&(It3.listen_3>=1)))||((It4.MSG_4>=1)&&(It4.listen_4>=1)))||((It5.MSG_5>=1)&&(It5.listen_5>=1)))"))U("(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))")))
Formula 3 simplified : !(X"(((((((It0.MSG_0>=1)&&(It0.listen_0>=1))||((It1.MSG_1>=1)&&(It1.listen_1>=1)))||((It2.MSG_2>=1)&&(It2.listen_2>=1)))||((It3.MSG_3>=1)&&(It3.listen_3>=1)))||((It4.MSG_4>=1)&&(It4.listen_4>=1)))||((It5.MSG_5>=1)&&(It5.listen_5>=1)))" U "(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))")
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
18630 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1114.99,11069084,1,0,3.05343e+07,85685,2401,1.55801e+07,175,502810,73404429
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 4 : !((X(("(((((((It0.FMC_0>=1)&&(It0.cable_used_0>=1))||((It1.FMC_1>=1)&&(It1.cable_used_1>=1)))||((It2.FMC_2>=1)&&(It2.cable_used_2>=1)))||((It3.FMC_3>=1)&&(It3.cable_used_3>=1)))||((It4.FMC_4>=1)&&(It4.cable_used_4>=1)))||((It5.FMC_5>=1)&&(It5.cable_used_5>=1)))")U(X(X("(((((((It0.MSG_0>=1)&&(It0.listen_0>=1))||((It1.MSG_1>=1)&&(It1.listen_1>=1)))||((It2.MSG_2>=1)&&(It2.listen_2>=1)))||((It3.MSG_3>=1)&&(It3.listen_3>=1)))||((It4.MSG_4>=1)&&(It4.listen_4>=1)))||((It5.MSG_5>=1)&&(It5.listen_5>=1)))"))))))
Formula 4 simplified : !X("(((((((It0.FMC_0>=1)&&(It0.cable_used_0>=1))||((It1.FMC_1>=1)&&(It1.cable_used_1>=1)))||((It2.FMC_2>=1)&&(It2.cable_used_2>=1)))||((It3.FMC_3>=1)&&(It3.cable_used_3>=1)))||((It4.FMC_4>=1)&&(It4.cable_used_4>=1)))||((It5.FMC_5>=1)&&(It5.cable_used_5>=1)))" U XX"(((((((It0.MSG_0>=1)&&(It0.listen_0>=1))||((It1.MSG_1>=1)&&(It1.listen_1>=1)))||((It2.MSG_2>=1)&&(It2.listen_2>=1)))||((It3.MSG_3>=1)&&(It3.listen_3>=1)))||((It4.MSG_4>=1)&&(It4.listen_4>=1)))||((It5.MSG_5>=1)&&(It5.listen_5>=1)))")
6 unique states visited
6 strongly connected components in search stack
6 transitions explored
6 items max in DFS search stack
30976 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1424.75,14164288,1,0,3.83155e+07,85685,1524,2.01955e+07,157,502810,15864478
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 5 : !((X(G((F("(((((((R_tout.R_tout_0>=1)&&(It0.MSG_0>=1))||((R_tout.R_tout_0>=1)&&(It1.MSG_1>=1)))||((R_tout.R_tout_0>=1)&&(It2.MSG_2>=1)))||((R_tout.R_tout_0>=1)&&(It3.MSG_3>=1)))||((R_tout.R_tout_0>=1)&&(It4.MSG_4>=1)))||((R_tout.R_tout_0>=1)&&(It5.MSG_5>=1)))"))U(X("(((((((It0.RMC_0>=1)&&(It0.wait_cable_0>=1))||((It1.RMC_1>=1)&&(It1.wait_cable_1>=1)))||((It2.RMC_2>=1)&&(It2.wait_cable_2>=1)))||((It3.RMC_3>=1)&&(It3.wait_cable_3>=1)))||((It4.RMC_4>=1)&&(It4.wait_cable_4>=1)))||((It5.RMC_5>=1)&&(It5.wait_cable_5>=1)))"))))))
Formula 5 simplified : !XG(F"(((((((R_tout.R_tout_0>=1)&&(It0.MSG_0>=1))||((R_tout.R_tout_0>=1)&&(It1.MSG_1>=1)))||((R_tout.R_tout_0>=1)&&(It2.MSG_2>=1)))||((R_tout.R_tout_0>=1)&&(It3.MSG_3>=1)))||((R_tout.R_tout_0>=1)&&(It4.MSG_4>=1)))||((R_tout.R_tout_0>=1)&&(It5.MSG_5>=1)))" U X"(((((((It0.RMC_0>=1)&&(It0.wait_cable_0>=1))||((It1.RMC_1>=1)&&(It1.wait_cable_1>=1)))||((It2.RMC_2>=1)&&(It2.wait_cable_2>=1)))||((It3.RMC_3>=1)&&(It3.wait_cable_3>=1)))||((It4.RMC_4>=1)&&(It4.wait_cable_4>=1)))||((It5.RMC_5>=1)&&(It5.wait_cable_5>=1)))")
5 unique states visited
5 strongly connected components in search stack
6 transitions explored
5 items max in DFS search stack
29422 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1718.97,14164516,1,0,3.83155e+07,85685,1998,2.01955e+07,173,502810,79140944
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 6 : !(("(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))"))
Formula 6 simplified : !"(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1718.97,14164516,1,0,3.83155e+07,85685,2152,2.01955e+07,175,502810,79141026
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 7 : !((G(G("(((((((((((((((((((((((((((((((((((((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom0.AMC_0>=1))&&(FMCb.FMCb_0>=1))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom6.AMC_6>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom12.AMC_12>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom18.AMC_18>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom24.AMC_24>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom30.AMC_30>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom1.AMC_1>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom7.AMC_7>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom13.AMC_13>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom19.AMC_19>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom25.AMC_25>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom31.AMC_31>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom2.AMC_2>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom8.AMC_8>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom14.AMC_14>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom20.AMC_20>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom26.AMC_26>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom32.AMC_32>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom3.AMC_3>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom9.AMC_9>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom15.AMC_15>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom21.AMC_21>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom27.AMC_27>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom33.AMC_33>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom4.AMC_4>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom10.AMC_10>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom16.AMC_16>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom22.AMC_22>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom28.AMC_28>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom34.AMC_34>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom5.AMC_5>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom11.AMC_11>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom17.AMC_17>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom23.AMC_23>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom29.AMC_29>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom35.AMC_35>=1))&&(FMCb.FMCb_0>=1)))"))))
Formula 7 simplified : !G"(((((((((((((((((((((((((((((((((((((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom0.AMC_0>=1))&&(FMCb.FMCb_0>=1))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom6.AMC_6>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom12.AMC_12>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom18.AMC_18>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom24.AMC_24>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It0.Cpt2_0>=1))&&(Dom30.AMC_30>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom1.AMC_1>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom7.AMC_7>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom13.AMC_13>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom19.AMC_19>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom25.AMC_25>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It1.Cpt2_1>=1))&&(Dom31.AMC_31>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom2.AMC_2>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom8.AMC_8>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom14.AMC_14>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom20.AMC_20>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom26.AMC_26>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It2.Cpt2_2>=1))&&(Dom32.AMC_32>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom3.AMC_3>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom9.AMC_9>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom15.AMC_15>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom21.AMC_21>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom27.AMC_27>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It3.Cpt2_3>=1))&&(Dom33.AMC_33>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom4.AMC_4>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom10.AMC_10>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom16.AMC_16>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom22.AMC_22>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom28.AMC_28>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It4.Cpt2_4>=1))&&(Dom34.AMC_34>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom5.AMC_5>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom11.AMC_11>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom17.AMC_17>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom23.AMC_23>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom29.AMC_29>=1))&&(FMCb.FMCb_0>=1)))||((((cable_free.cable_free_0>=1)&&(It5.Cpt2_5>=1))&&(Dom35.AMC_35>=1))&&(FMCb.FMCb_0>=1)))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
2 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,1719,14164516,1,0,3.83155e+07,85685,2515,2.01955e+07,175,502810,79141178
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA SafeBus-COL-06-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 8 : !((X("(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))")))
Formula 8 simplified : !X"(((((((((((((((((((((((((((((((((((((It0.Cpt1_0>=1)&&(It0.loop_em_0>=1))||((It0.Cpt1_0>=1)&&(It1.loop_em_1>=1)))||((It0.Cpt1_0>=1)&&(It2.loop_em_2>=1)))||((It0.Cpt1_0>=1)&&(It3.loop_em_3>=1)))||((It0.Cpt1_0>=1)&&(It4.loop_em_4>=1)))||((It0.Cpt1_0>=1)&&(It5.loop_em_5>=1)))||((It1.Cpt1_1>=1)&&(It0.loop_em_0>=1)))||((It1.Cpt1_1>=1)&&(It1.loop_em_1>=1)))||((It1.Cpt1_1>=1)&&(It2.loop_em_2>=1)))||((It1.Cpt1_1>=1)&&(It3.loop_em_3>=1)))||((It1.Cpt1_1>=1)&&(It4.loop_em_4>=1)))||((It1.Cpt1_1>=1)&&(It5.loop_em_5>=1)))||((It2.Cpt1_2>=1)&&(It0.loop_em_0>=1)))||((It2.Cpt1_2>=1)&&(It1.loop_em_1>=1)))||((It2.Cpt1_2>=1)&&(It2.loop_em_2>=1)))||((It2.Cpt1_2>=1)&&(It3.loop_em_3>=1)))||((It2.Cpt1_2>=1)&&(It4.loop_em_4>=1)))||((It2.Cpt1_2>=1)&&(It5.loop_em_5>=1)))||((It3.Cpt1_3>=1)&&(It0.loop_em_0>=1)))||((It3.Cpt1_3>=1)&&(It1.loop_em_1>=1)))||((It3.Cpt1_3>=1)&&(It2.loop_em_2>=1)))||((It3.Cpt1_3>=1)&&(It3.loop_em_3>=1)))||((It3.Cpt1_3>=1)&&(It4.loop_em_4>=1)))||((It3.Cpt1_3>=1)&&(It5.loop_em_5>=1)))||((It4.Cpt1_4>=1)&&(It0.loop_em_0>=1)))||((It4.Cpt1_4>=1)&&(It1.loop_em_1>=1)))||((It4.Cpt1_4>=1)&&(It2.loop_em_2>=1)))||((It4.Cpt1_4>=1)&&(It3.loop_em_3>=1)))||((It4.Cpt1_4>=1)&&(It4.loop_em_4>=1)))||((It4.Cpt1_4>=1)&&(It5.loop_em_5>=1)))||((It5.Cpt1_5>=1)&&(It0.loop_em_0>=1)))||((It5.Cpt1_5>=1)&&(It1.loop_em_1>=1)))||((It5.Cpt1_5>=1)&&(It2.loop_em_2>=1)))||((It5.Cpt1_5>=1)&&(It3.loop_em_3>=1)))||((It5.Cpt1_5>=1)&&(It4.loop_em_4>=1)))||((It5.Cpt1_5>=1)&&(It5.loop_em_5>=1)))"
LTSmin run took 1231462 ms.
FORMULA SafeBus-COL-06-LTLFireability-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.
BK_STOP 1527834184341
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 5:54:12 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 01, 2018 5:54:12 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 5:54:12 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1071 ms
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 20 places.
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :Dom->AMC,wait_ack,
Dot->cable_free,ACK,T_out,R_tout,S_tout,FMCb,
It->Cpt2,Cpt1,msgl,cable_used,FMC,wait_cable,listen,RMC,PMC,MSG,wait_msg,loop_em,
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 14 transitions.
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Jun 01, 2018 5:54:13 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 7 ms
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $x and $y of transition C_refuse
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition C_free
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $x and $y of transition C_provide
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $r and $i of transition I_rec1
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition I_emit
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition I_refused
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $r and $i of transition I_rec2
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 1 fixed domain variables (out of 150 variables) in GAL type Document
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 6 constant array cells/variables (out of 150 variables) in type Document
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: msgl[0-5],
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 6.0 instantiations of transitions. Total transitions/syncs built is 340
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 1 fixed domain variables (out of 150 variables) in GAL type Document
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 6 constant array cells/variables (out of 150 variables) in type Document
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: msgl[0-5],
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :msgl[]
Jun 01, 2018 5:54:13 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 127 ms
Jun 01, 2018 5:54:14 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays Cpt2, Cpt1, cable_used, FMC, AMC, wait_ack, wait_cable, listen, RMC, PMC, MSG, wait_msg, loop_em to variables to allow decomposition.
Jun 01, 2018 5:54:14 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 402 redundant transitions.
Jun 01, 2018 5:54:15 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 12 ms
Jun 01, 2018 5:54:15 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 13 ms
Jun 01, 2018 5:54:15 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 34 transitions. Expanding to a total of 586 deterministic transitions.
Jun 01, 2018 5:54:15 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 17 ms.
Jun 01, 2018 5:54:16 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 29 place invariants in 91 ms
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 144 variables to be positive in 795 ms
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 463 transitions.
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/463 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 65 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 463 transitions.
Jun 01, 2018 5:54:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 44 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 5:54:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 463 transitions.
Jun 01, 2018 5:54:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/463) took 110 ms. Total solver calls (SAT/UNSAT): 96(90/6)
Jun 01, 2018 5:54:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/463) took 3325 ms. Total solver calls (SAT/UNSAT): 1785(1362/423)
Jun 01, 2018 5:54:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/463) took 6876 ms. Total solver calls (SAT/UNSAT): 3165(2392/773)
Jun 01, 2018 5:54:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/463) took 9942 ms. Total solver calls (SAT/UNSAT): 4776(3376/1400)
Jun 01, 2018 5:54:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/463) took 13443 ms. Total solver calls (SAT/UNSAT): 6086(4340/1746)
Jun 01, 2018 5:54:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/463) took 16930 ms. Total solver calls (SAT/UNSAT): 7371(5280/2091)
Jun 01, 2018 5:54:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/463) took 20163 ms. Total solver calls (SAT/UNSAT): 8631(6190/2441)
Jun 01, 2018 5:54:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/463) took 23279 ms. Total solver calls (SAT/UNSAT): 10930(7661/3269)
Jun 01, 2018 5:54:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(48/463) took 26423 ms. Total solver calls (SAT/UNSAT): 12944(8950/3994)
Jun 01, 2018 5:55:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(53/463) took 29592 ms. Total solver calls (SAT/UNSAT): 14739(10087/4652)
Jun 01, 2018 5:55:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/463) took 33162 ms. Total solver calls (SAT/UNSAT): 16861(11520/5341)
Jun 01, 2018 5:55:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/463) took 36691 ms. Total solver calls (SAT/UNSAT): 19118(13105/6013)
Jun 01, 2018 5:55:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(72/463) took 39699 ms. Total solver calls (SAT/UNSAT): 20988(14394/6594)
Jun 01, 2018 5:55:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/463) took 42742 ms. Total solver calls (SAT/UNSAT): 23124(15739/7385)
Jun 01, 2018 5:55:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(84/463) took 46641 ms. Total solver calls (SAT/UNSAT): 24620(16614/8006)
Jun 01, 2018 5:55:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(88/463) took 50826 ms. Total solver calls (SAT/UNSAT): 25913(17347/8566)
Jun 01, 2018 5:55:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/463) took 54183 ms. Total solver calls (SAT/UNSAT): 27508(18339/9169)
Jun 01, 2018 5:55:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(96/463) took 57225 ms. Total solver calls (SAT/UNSAT): 28456(19122/9334)
Jun 01, 2018 5:55:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/463) took 60617 ms. Total solver calls (SAT/UNSAT): 29867(20002/9865)
Jun 01, 2018 5:55:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(107/463) took 63762 ms. Total solver calls (SAT/UNSAT): 31527(21112/10415)
Jun 01, 2018 5:55:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(115/463) took 67290 ms. Total solver calls (SAT/UNSAT): 33823(22082/11741)
Jun 01, 2018 5:55:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/463) took 70356 ms. Total solver calls (SAT/UNSAT): 35548(22727/12821)
Jun 01, 2018 5:55:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(125/463) took 73386 ms. Total solver calls (SAT/UNSAT): 36778(23186/13592)
Jun 01, 2018 5:55:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(130/463) took 77352 ms. Total solver calls (SAT/UNSAT): 38293(23799/14494)
Jun 01, 2018 5:55:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(132/463) took 81004 ms. Total solver calls (SAT/UNSAT): 38892(24102/14790)
Jun 01, 2018 5:55:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/463) took 84374 ms. Total solver calls (SAT/UNSAT): 40222(24596/15626)
Jun 01, 2018 5:56:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(140/463) took 87761 ms. Total solver calls (SAT/UNSAT): 41008(24966/16042)
Jun 01, 2018 5:56:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(150/463) took 90947 ms. Total solver calls (SAT/UNSAT): 43444(26120/17324)
Jun 01, 2018 5:56:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(156/463) took 94529 ms. Total solver calls (SAT/UNSAT): 44810(26908/17902)
Jun 01, 2018 5:56:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(162/463) took 97618 ms. Total solver calls (SAT/UNSAT): 46314(27840/18474)
Jun 01, 2018 5:56:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(169/463) took 100914 ms. Total solver calls (SAT/UNSAT): 47994(28935/19059)
Jun 01, 2018 5:56:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(176/463) took 104040 ms. Total solver calls (SAT/UNSAT): 49451(29885/19566)
Jun 01, 2018 5:56:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(187/463) took 107264 ms. Total solver calls (SAT/UNSAT): 51642(31084/20558)
Jun 01, 2018 5:56:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(194/463) took 110311 ms. Total solver calls (SAT/UNSAT): 53033(31879/21154)
Jun 01, 2018 5:56:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(200/463) took 113394 ms. Total solver calls (SAT/UNSAT): 54309(32632/21677)
Jun 01, 2018 5:56:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(206/463) took 116421 ms. Total solver calls (SAT/UNSAT): 55489(33325/22164)
Jun 01, 2018 5:56:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(213/463) took 119555 ms. Total solver calls (SAT/UNSAT): 56693(34044/22649)
Jun 01, 2018 5:56:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(224/463) took 122562 ms. Total solver calls (SAT/UNSAT): 58471(34901/23570)
Jun 01, 2018 5:56:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(233/463) took 125899 ms. Total solver calls (SAT/UNSAT): 59990(35724/24266)
Jun 01, 2018 5:56:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(240/463) took 128919 ms. Total solver calls (SAT/UNSAT): 61198(36298/24900)
Jun 01, 2018 5:56:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(249/463) took 131938 ms. Total solver calls (SAT/UNSAT): 62429(36983/25446)
Jun 01, 2018 5:56:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(262/463) took 135062 ms. Total solver calls (SAT/UNSAT): 64171(37871/26300)
Jun 01, 2018 5:56:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(269/463) took 138424 ms. Total solver calls (SAT/UNSAT): 65206(38666/26540)
Jun 01, 2018 5:56:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(274/463) took 141928 ms. Total solver calls (SAT/UNSAT): 65917(38983/26934)
Jun 01, 2018 5:56:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(283/463) took 145036 ms. Total solver calls (SAT/UNSAT): 67105(39752/27353)
Jun 01, 2018 5:57:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/463) took 148410 ms. Total solver calls (SAT/UNSAT): 68133(40502/27631)
Jun 01, 2018 5:57:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(302/463) took 151737 ms. Total solver calls (SAT/UNSAT): 69148(41171/27977)
Jun 01, 2018 5:57:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(311/463) took 154940 ms. Total solver calls (SAT/UNSAT): 70030(41807/28223)
Jun 01, 2018 5:57:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(323/463) took 158239 ms. Total solver calls (SAT/UNSAT): 70882(42329/28553)
Jun 01, 2018 5:57:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(334/463) took 161306 ms. Total solver calls (SAT/UNSAT): 71718(42861/28857)
Jun 01, 2018 5:57:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(364/463) took 164376 ms. Total solver calls (SAT/UNSAT): 73018(43718/29300)
Jun 01, 2018 5:57:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(424/463) took 167382 ms. Total solver calls (SAT/UNSAT): 75466(44196/31270)
Jun 01, 2018 5:57:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 168285 ms. Total solver calls (SAT/UNSAT): 75994(44266/31728)
Jun 01, 2018 5:57:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 463 transitions.
Jun 01, 2018 5:57:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 10525 ms. Total solver calls (SAT/UNSAT): 7874(0/7874)
Jun 01, 2018 5:57:32 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 196521ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SafeBus-COL-06"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/SafeBus-COL-06.tgz
mv SafeBus-COL-06 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is SafeBus-COL-06, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r212-smll-152732263400518"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;