About the Execution of ITS-Tools for DNAwalker-PT-09ringLR
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15753.170 | 22632.00 | 46088.00 | 388.00 | FFFFFTFFFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.......................
/home/mcc/execution
total 272K
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.8K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 9 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 112K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DNAwalker-PT-09ringLR, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r212-smll-152732263000244
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-00
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-01
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-02
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-03
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-04
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-05
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-06
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-07
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-08
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-09
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-10
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-11
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-12
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-13
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-14
FORMULA_NAME DNAwalker-PT-09ringLR-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1527935055923
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F(("((A18>=2)&&(A20>=1))")U(X(G("((A10>=2)&&(A11>=1))"))))))
Formula 0 simplified : !F("((A18>=2)&&(A20>=1))" U XG"((A10>=2)&&(A11>=1))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 259
// Phase 1: matrix 259 rows 27 cols
Reverse transition relation is NOT exact ! Due to transitions tb2, tAb2, tb3, tAb3, tb10, tAb10, tb11, tAb11, tb20, tAb20, tb21, tAb21, t1_2, t1_3, t1_4, t1_5, t1_6, t1_7, t1_8, t1_9, t1_10, t1_11, t1_12, t1_13, t1_14, t1_15, t1_16, t1_17, t1_18, t1_19, t1_20, t1_21, t2_3, t2_4, t2_5, t2_6, t2_7, t2_8, t2_9, t2_10, t2_11, t2_12, t2_13, t2_14, t2_15, t2_16, t2_17, t2_18, t2_19, t2_20, t2_21, t3_2, t3_4, t3_5, t3_6, t3_7, t3_8, t3_13, t3_17, t3_18, t3_19, t3_20, t3_21, t4_2, t4_3, t4_5, t4_6, t4_7, t4_8, t4_13, t4_18, t4_19, t4_20, t4_21, t5_2, t5_3, t5_4, t5_6, t5_7, t5_8, t5_9, t5_13, t5_20, t5_21, t6_2, t6_3, t6_4, t6_5, t6_7, t6_8, t6_9, t6_10, t6_13, t6_21, t8_2, t8_3, t8_4, t8_5, t8_6, t8_7, t8_9, t8_10, t8_11, t8_12, t8_13, t8_14, t9_2, t9_5, t9_6, t9_7, t9_8, t9_10, t9_11, t9_12, t9_13, t9_14, t10_2, t10_6, t10_7, t10_8, t10_9, t10_11, t10_12, t10_13, t10_14, t10_15, t11_2, t11_7, t11_8, t11_9, t11_10, t11_12, t11_13, t11_14, t11_15, t11_16, t12_2, t12_7, t12_8, t12_9, t12_10, t12_11, t12_13, t12_14, t12_15, t12_16, t12_17, t12_18, t13_2, t13_3, t13_4, t13_5, t13_6, t13_7, t13_8, t13_9, t13_10, t13_11, t13_12, t13_14, t13_15, t13_16, t13_17, t13_18, t13_19, t13_20, t13_21, t14_2, t14_8, t14_9, t14_10, t14_11, t14_12, t14_13, t14_15, t14_16, t14_17, t14_18, t15_2, t15_10, t15_11, t15_12, t15_13, t15_14, t15_16, t15_17, t15_18, t15_19, t16_2, t16_11, t16_12, t16_13, t16_14, t16_15, t16_17, t16_18, t16_19, t16_20, t18_2, t18_3, t18_4, t18_12, t18_13, t18_14, t18_15, t18_16, t18_17, t18_19, t18_20, t18_21, t19_2, t19_3, t19_4, t19_13, t19_15, t19_16, t19_17, t19_18, t19_20, t19_21, t20_2, t20_3, t20_4, t20_5, t20_13, t20_16, t20_17, t20_18, t20_19, t20_21, t21_2, t21_3, t21_4, t21_5, t21_6, t21_13, t21_17, t21_18, t21_19, t21_20, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :18/2/240/260
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
1236 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,12.416,282496,1,0,935,1.15346e+06,529,304,2649,1.82601e+06,953
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !((X("((A21>=2)&&(A18>=1))")))
Formula 1 simplified : !X"((A21>=2)&&(A18>=1))"
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
149 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,13.9138,312964,1,0,935,1.23525e+06,538,304,2703,1.98827e+06,1031
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 2 : !(("((A19>=2)&&(A3>=1))"))
Formula 2 simplified : !"((A19>=2)&&(A3>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
18 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,14.0912,316660,1,0,935,1.24694e+06,541,304,2706,2.00942e+06,1041
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 3 : !((X(X("((A16>=2)&&(A12>=1))"))))
Formula 3 simplified : !XX"((A16>=2)&&(A12>=1))"
5 unique states visited
5 strongly connected components in search stack
5 transitions explored
5 items max in DFS search stack
110 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,15.1881,332480,1,0,960,1.30875e+06,544,304,2709,2.10692e+06,1125
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 4 : !((X((X("((A10>=2)&&(A11>=1))"))U(X(F("((A18>=2)&&(A2>=1))"))))))
Formula 4 simplified : !X(X"((A10>=2)&&(A11>=1))" U XF"((A18>=2)&&(A2>=1))")
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
190 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,17.0938,379436,1,0,1055,1.50812e+06,553,322,2712,2.41108e+06,1336
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 5 : !((F("(B20>=1)")))
Formula 5 simplified : !F"(B20>=1)"
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,17.0944,379436,1,0,1055,1.50812e+06,562,322,2713,2.41108e+06,1340
no accepting run found
Formula 5 is TRUE no accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 6 : !((X("((A19>=2)&&(A15>=1))")))
Formula 6 simplified : !X"((A19>=2)&&(A15>=1))"
Compilation finished in 3520 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 43 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
17 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,17.267,382868,1,0,1081,1.51885e+06,565,322,2715,2.43116e+06,1427
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 7 : !(("((A20>=2)&&(A21>=1))"))
Formula 7 simplified : !"((A20>=2)&&(A21>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,17.2678,383132,1,0,1081,1.51885e+06,568,322,2718,2.43116e+06,1429
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 8 : !(((F(G("((A13>=2)&&(A20>=1))")))U(F(X(X("((A16>=2)&&(A13>=1))"))))))
Formula 8 simplified : !(FG"((A13>=2)&&(A20>=1))" U FXX"((A16>=2)&&(A13>=1))")
LTSmin run took 32 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>([]((LTLAP9==true))))U(<>(X(X((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 16 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 43 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>((LTLAP12==true))))U(<>(X(X((LTLAP13==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 15 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([]([](X((LTLAP14==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 16 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([]([](<>((LTLAP15==true)))))U([]((LTLAP16==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 44 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 42 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>((LTLAP18==true)))U((<>((LTLAP19==true)))U((LTLAP20==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 41 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP21==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 48 ms.
FORMULA DNAwalker-PT-09ringLR-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.
BK_STOP 1527935078555
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 88 ms
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 27 places.
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 260 transitions.
Jun 02, 2018 10:24:19 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 18 ms
Jun 02, 2018 10:24:19 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 159 ms
Jun 02, 2018 10:24:19 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 8 ms
Jun 02, 2018 10:24:19 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 260 transitions.
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 18 ms
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 27 variables to be positive in 185 ms
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 260 transitions.
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/260 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 53 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 260 transitions.
Jun 02, 2018 10:24:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 25 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 10:24:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 260 transitions.
Jun 02, 2018 10:24:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/260) took 842 ms. Total solver calls (SAT/UNSAT): 1027(1027/0)
Jun 02, 2018 10:24:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(152/260) took 3851 ms. Total solver calls (SAT/UNSAT): 4415(4415/0)
Jun 02, 2018 10:24:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 5595 ms. Total solver calls (SAT/UNSAT): 5918(5918/0)
Jun 02, 2018 10:24:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 260 transitions.
Jun 02, 2018 10:24:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 5014 ms. Total solver calls (SAT/UNSAT): 1563(0/1563)
Jun 02, 2018 10:24:33 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 13790ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DNAwalker-PT-09ringLR"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/DNAwalker-PT-09ringLR.tgz
mv DNAwalker-PT-09ringLR execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DNAwalker-PT-09ringLR, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r212-smll-152732263000244"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;