About the Execution of ITS-Tools for DES-PT-30a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15755.710 | 39330.00 | 82405.00 | 386.60 | FFFFFFFFFFFFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 236K
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.5K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 101 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 339 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 70K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DES-PT-30a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r212-smll-152732262800148
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-30a-LTLFireability-00
FORMULA_NAME DES-PT-30a-LTLFireability-01
FORMULA_NAME DES-PT-30a-LTLFireability-02
FORMULA_NAME DES-PT-30a-LTLFireability-03
FORMULA_NAME DES-PT-30a-LTLFireability-04
FORMULA_NAME DES-PT-30a-LTLFireability-05
FORMULA_NAME DES-PT-30a-LTLFireability-06
FORMULA_NAME DES-PT-30a-LTLFireability-07
FORMULA_NAME DES-PT-30a-LTLFireability-08
FORMULA_NAME DES-PT-30a-LTLFireability-09
FORMULA_NAME DES-PT-30a-LTLFireability-10
FORMULA_NAME DES-PT-30a-LTLFireability-11
FORMULA_NAME DES-PT-30a-LTLFireability-12
FORMULA_NAME DES-PT-30a-LTLFireability-13
FORMULA_NAME DES-PT-30a-LTLFireability-14
FORMULA_NAME DES-PT-30a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1527895241733
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G("(((u20.p152>=1)&&(u21.p154>=1))&&(u1.p11>=1))")))
Formula 0 simplified : !G"(((u20.p152>=1)&&(u21.p154>=1))&&(u1.p11>=1))"
built 53 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 177 rows 234 cols
invariant :u58:p230 + u58:p231 + u61:p229 + u62:p0 = 1
invariant :u10:p131 + u62:p0 = 1
invariant :u24:p159 + u31:p174 + -1'u32:p176 + u39:p190 + u40:p192 + -1'u47:p206 + u62:p0 = 1
invariant :u21:p153 + u21:p154 + u62:p0 = 1
invariant :u7:p124 + u7:p125 + u7:p126 + u62:p0 = 1
invariant :u50:p211 + u50:p212 + u62:p0 = 1
invariant :u31:p173 + u31:p174 + u62:p0 = 1
invariant :u37:p185 + u37:p186 + u62:p0 = 1
invariant :u32:p175 + u32:p176 + u62:p0 = 1
invariant :u48:p207 + u48:p208 + -1'u49:p209 + -1'u49:p210 = 0
invariant :u24:p160 + -1'u31:p174 + u32:p176 + -1'u39:p190 + -1'u40:p192 + u47:p206 = 0
invariant :u30:p172 + -1'u31:p174 + u38:p188 + -1'u39:p190 + -1'u46:p204 + u47:p206 = 0
invariant :u27:p166 + -1'u31:p174 + u35:p182 + -1'u39:p190 + -1'u43:p198 + u47:p206 = 0
invariant :u28:p167 + u31:p174 + -1'u36:p184 + u39:p190 + u44:p200 + -1'u47:p206 + u62:p0 = 1
invariant :u19:p149 + u19:p150 + u62:p0 = 1
invariant :u29:p170 + -1'u31:p174 + u37:p186 + -1'u39:p190 + -1'u45:p202 + u47:p206 = 0
invariant :u34:p179 + u34:p180 + u62:p0 = 1
invariant :u52:p216 + u52:p217 + u54:p220 + u54:p221 + u60:p213 + u60:p214 + u60:p215 + u62:p0 = 1
invariant :-1'u54:p220 + -1'u54:p221 + u55:p222 + u55:p223 = 0
invariant :u27:p165 + u31:p174 + -1'u35:p182 + u39:p190 + u43:p198 + -1'u47:p206 + u62:p0 = 1
invariant :u39:p189 + u39:p190 + u62:p0 = 1
invariant :u56:p224 + u56:p225 + u56:p226 + u56:p227 + u56:p228 + u62:p0 = 1
invariant :29'u1:p1 + u1:p2 + 2'u1:p3 + 3'u1:p4 + 4'u1:p5 + 5'u1:p6 + 6'u1:p7 + 7'u1:p8 + 8'u1:p9 + 9'u1:p10 + 10'u1:p11 + 11'u1:p12 + 12'u1:p13 + 13'u1:p14 + 14'u1:p15 + 15'u1:p16 + 16'u1:p17 + 17'u1:p18 + 18'u1:p19 + 19'u1:p20 + 20'u1:p21 + 21'u1:p22 + 22'u1:p23 + 23'u1:p24 + 24'u1:p25 + 25'u1:p26 + 26'u1:p27 + 27'u1:p28 + 28'u1:p29 + -30'u2:p30 + -1'u2:p31 + -2'u2:p32 + -3'u2:p33 + -4'u2:p34 + -5'u2:p35 + -6'u2:p36 + -7'u2:p37 + -8'u2:p38 + -9'u2:p39 + -10'u2:p40 + -11'u2:p41 + -12'u2:p42 + -13'u2:p43 + -14'u2:p44 + -15'u2:p45 + -16'u2:p46 + -17'u2:p47 + -18'u2:p48 + -19'u2:p49 + -20'u2:p50 + -21'u2:p51 + -22'u2:p52 + -23'u2:p53 + -24'u2:p54 + -25'u2:p55 + -26'u2:p56 + -27'u2:p57 + -28'u2:p58 + -29'u2:p59 + u8:p128 + -1'u9:p130 + -1'u21:p154 + -1'u23:p158 + u60:p215 + u56:p224 + u58:p231 + u61:p229 + u62:p0 = 1
invariant :u25:p162 + -1'u31:p174 + u33:p178 + -1'u39:p190 + -1'u41:p194 + u47:p206 = 0
invariant :-29'u1:p1 + -1'u1:p2 + -2'u1:p3 + -3'u1:p4 + -4'u1:p5 + -5'u1:p6 + -6'u1:p7 + -7'u1:p8 + -8'u1:p9 + -9'u1:p10 + -10'u1:p11 + -11'u1:p12 + -12'u1:p13 + -13'u1:p14 + -14'u1:p15 + -15'u1:p16 + -16'u1:p17 + -17'u1:p18 + -18'u1:p19 + -19'u1:p20 + -20'u1:p21 + -21'u1:p22 + -22'u1:p23 + -23'u1:p24 + -24'u1:p25 + -25'u1:p26 + -26'u1:p27 + -27'u1:p28 + -28'u1:p29 + 30'u2:p30 + u2:p31 + 2'u2:p32 + 3'u2:p33 + 4'u2:p34 + 5'u2:p35 + 6'u2:p36 + 7'u2:p37 + 8'u2:p38 + 9'u2:p39 + 10'u2:p40 + 11'u2:p41 + 12'u2:p42 + 13'u2:p43 + 14'u2:p44 + 15'u2:p45 + 16'u2:p46 + 17'u2:p47 + 18'u2:p48 + 19'u2:p49 + 20'u2:p50 + 21'u2:p51 + 22'u2:p52 + 23'u2:p53 + 24'u2:p54 + 25'u2:p55 + 26'u2:p56 + 27'u2:p57 + 28'u2:p58 + 29'u2:p59 + u8:p127 + u9:p130 + u21:p154 + u23:p158 + -1'u60:p215 + -1'u56:p224 + -1'u58:p231 + -1'u61:p229 = 0
invariant :u45:p201 + u45:p202 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :u59:p232 + u59:p233 + u61:p229 + u62:p0 = 1
invariant :u5:p120 + u5:p121 + u62:p0 = 1
invariant :u36:p183 + u36:p184 + u62:p0 = 1
invariant :u43:p197 + u43:p198 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :58'u1:p1 + 2'u1:p2 + 4'u1:p3 + 6'u1:p4 + 8'u1:p5 + 10'u1:p6 + 12'u1:p7 + 14'u1:p8 + 16'u1:p9 + 18'u1:p10 + 20'u1:p11 + 22'u1:p12 + 24'u1:p13 + 26'u1:p14 + 28'u1:p15 + 30'u1:p16 + 32'u1:p17 + 34'u1:p18 + 36'u1:p19 + 38'u1:p20 + 40'u1:p21 + 42'u1:p22 + 44'u1:p23 + 46'u1:p24 + 48'u1:p25 + 50'u1:p26 + 52'u1:p27 + 54'u1:p28 + 56'u1:p29 + -30'u2:p30 + -1'u2:p31 + -2'u2:p32 + -3'u2:p33 + -4'u2:p34 + -5'u2:p35 + -6'u2:p36 + -7'u2:p37 + -8'u2:p38 + -9'u2:p39 + -10'u2:p40 + -11'u2:p41 + -12'u2:p42 + -13'u2:p43 + -14'u2:p44 + -15'u2:p45 + -16'u2:p46 + -17'u2:p47 + -18'u2:p48 + -19'u2:p49 + -20'u2:p50 + -21'u2:p51 + -22'u2:p52 + -23'u2:p53 + -24'u2:p54 + -25'u2:p55 + -26'u2:p56 + -27'u2:p57 + -28'u2:p58 + -29'u2:p59 + -30'u4:p90 + -1'u4:p91 + -2'u4:p92 + -3'u4:p93 + -4'u4:p94 + -5'u4:p95 + -6'u4:p96 + -7'u4:p97 + -8'u4:p98 + -9'u4:p99 + -10'u4:p100 + -11'u4:p101 + -12'u4:p102 + -13'u4:p103 + -14'u4:p104 + -15'u4:p105 + -16'u4:p106 + -17'u4:p107 + -18'u4:p108 + -19'u4:p109 + -20'u4:p110 + -21'u4:p111 + -22'u4:p112 + -23'u4:p113 + -24'u4:p114 + -25'u4:p115 + -26'u4:p116 + -27'u4:p117 + -28'u4:p118 + -29'u4:p119 + -1'u7:p126 + -1'u9:p130 + u11:p133 + -1'u14:p140 + -1'u15:p141 + u18:p148 + -1'u20:p152 + -1'u21:p154 + -1'u23:p158 + u48:p208 + -1'u49:p210 + -1'u50:p212 + u52:p217 + u54:p221 + u60:p213 + u60:p215 + u56:p224 + u58:p231 + u61:p229 = 0
invariant :u47:p205 + u47:p206 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :29'u1:p1 + u1:p2 + 2'u1:p3 + 3'u1:p4 + 4'u1:p5 + 5'u1:p6 + 6'u1:p7 + 7'u1:p8 + 8'u1:p9 + 9'u1:p10 + 10'u1:p11 + 11'u1:p12 + 12'u1:p13 + 13'u1:p14 + 14'u1:p15 + 15'u1:p16 + 16'u1:p17 + 17'u1:p18 + 18'u1:p19 + 19'u1:p20 + 20'u1:p21 + 21'u1:p22 + 22'u1:p23 + 23'u1:p24 + 24'u1:p25 + 25'u1:p26 + 26'u1:p27 + 27'u1:p28 + 28'u1:p29 + -30'u2:p30 + -1'u2:p31 + -2'u2:p32 + -3'u2:p33 + -4'u2:p34 + -5'u2:p35 + -6'u2:p36 + -7'u2:p37 + -8'u2:p38 + -9'u2:p39 + -10'u2:p40 + -11'u2:p41 + -12'u2:p42 + -13'u2:p43 + -14'u2:p44 + -15'u2:p45 + -16'u2:p46 + -17'u2:p47 + -18'u2:p48 + -19'u2:p49 + -20'u2:p50 + -21'u2:p51 + -22'u2:p52 + -23'u2:p53 + -24'u2:p54 + -25'u2:p55 + -26'u2:p56 + -27'u2:p57 + -28'u2:p58 + -29'u2:p59 + -1'u20:p152 + u22:p155 + -1'u31:p174 + -1'u39:p190 + u47:p206 + u49:p209 + -1'u50:p212 + u52:p217 + u54:p221 + u60:p213 + u60:p215 + u58:p231 + u61:p229 + 3'u62:p0 = 3
invariant :u41:p193 + u41:p194 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :u9:p129 + u9:p130 + u62:p0 = 1
invariant :u17:p145 + u17:p146 + u62:p0 = 1
invariant :-29'u1:p1 + -1'u1:p2 + -2'u1:p3 + -3'u1:p4 + -4'u1:p5 + -5'u1:p6 + -6'u1:p7 + -7'u1:p8 + -8'u1:p9 + -9'u1:p10 + -10'u1:p11 + -11'u1:p12 + -12'u1:p13 + -13'u1:p14 + -14'u1:p15 + -15'u1:p16 + -16'u1:p17 + -17'u1:p18 + -18'u1:p19 + -19'u1:p20 + -20'u1:p21 + -21'u1:p22 + -22'u1:p23 + -23'u1:p24 + -24'u1:p25 + -25'u1:p26 + -26'u1:p27 + -27'u1:p28 + -28'u1:p29 + 30'u2:p30 + u2:p31 + 2'u2:p32 + 3'u2:p33 + 4'u2:p34 + 5'u2:p35 + 6'u2:p36 + 7'u2:p37 + 8'u2:p38 + 9'u2:p39 + 10'u2:p40 + 11'u2:p41 + 12'u2:p42 + 13'u2:p43 + 14'u2:p44 + 15'u2:p45 + 16'u2:p46 + 17'u2:p47 + 18'u2:p48 + 19'u2:p49 + 20'u2:p50 + 21'u2:p51 + 22'u2:p52 + 23'u2:p53 + 24'u2:p54 + 25'u2:p55 + 26'u2:p56 + 27'u2:p57 + 28'u2:p58 + 29'u2:p59 + u20:p152 + u22:p156 + u31:p174 + u39:p190 + -1'u47:p206 + -1'u49:p209 + u50:p212 + -1'u52:p217 + -1'u54:p221 + -1'u60:p213 + -1'u60:p215 + -1'u58:p231 + -1'u61:p229 + -2'u62:p0 = -2
invariant :u26:p163 + u31:p174 + -1'u34:p180 + u39:p190 + u42:p196 + -1'u47:p206 + u62:p0 = 1
invariant :u20:p151 + u20:p152 + u62:p0 = 1
invariant :u33:p177 + u33:p178 + u62:p0 = 1
invariant :u44:p199 + u44:p200 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :58'u1:p1 + 2'u1:p2 + 4'u1:p3 + 6'u1:p4 + 8'u1:p5 + 10'u1:p6 + 12'u1:p7 + 14'u1:p8 + 16'u1:p9 + 18'u1:p10 + 20'u1:p11 + 22'u1:p12 + 24'u1:p13 + 26'u1:p14 + 28'u1:p15 + 30'u1:p16 + 32'u1:p17 + 34'u1:p18 + 36'u1:p19 + 38'u1:p20 + 40'u1:p21 + 42'u1:p22 + 44'u1:p23 + 46'u1:p24 + 48'u1:p25 + 50'u1:p26 + 52'u1:p27 + 54'u1:p28 + 56'u1:p29 + -60'u2:p30 + -2'u2:p31 + -4'u2:p32 + -6'u2:p33 + -8'u2:p34 + -10'u2:p35 + -12'u2:p36 + -14'u2:p37 + -16'u2:p38 + -18'u2:p39 + -20'u2:p40 + -22'u2:p41 + -24'u2:p42 + -26'u2:p43 + -28'u2:p44 + -30'u2:p45 + -32'u2:p46 + -34'u2:p47 + -36'u2:p48 + -38'u2:p49 + -40'u2:p50 + -42'u2:p51 + -44'u2:p52 + -46'u2:p53 + -48'u2:p54 + -50'u2:p55 + -52'u2:p56 + -54'u2:p57 + -56'u2:p58 + -58'u2:p59 + -1'u20:p152 + -1'u21:p154 + -1'u23:p158 + u53:p219 + u55:p223 + u60:p213 + u60:p215 + u56:p224 + u56:p228 + u58:p231 + u59:p233 + 2'u61:p229 + 2'u62:p0 = 2
invariant :u38:p187 + u38:p188 + u62:p0 = 1
invariant :u6:p122 + u6:p123 + u62:p0 = 1
invariant :u46:p203 + u46:p204 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :u25:p161 + u31:p174 + -1'u33:p178 + u39:p190 + u41:p194 + -1'u47:p206 + u62:p0 = 1
invariant :u29:p169 + u31:p174 + -1'u37:p186 + u39:p190 + u45:p202 + -1'u47:p206 + u62:p0 = 1
invariant :u42:p195 + u42:p196 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :-58'u1:p1 + -2'u1:p2 + -4'u1:p3 + -6'u1:p4 + -8'u1:p5 + -10'u1:p6 + -12'u1:p7 + -14'u1:p8 + -16'u1:p9 + -18'u1:p10 + -20'u1:p11 + -22'u1:p12 + -24'u1:p13 + -26'u1:p14 + -28'u1:p15 + -30'u1:p16 + -32'u1:p17 + -34'u1:p18 + -36'u1:p19 + -38'u1:p20 + -40'u1:p21 + -42'u1:p22 + -44'u1:p23 + -46'u1:p24 + -48'u1:p25 + -50'u1:p26 + -52'u1:p27 + -54'u1:p28 + -56'u1:p29 + 30'u2:p30 + u2:p31 + 2'u2:p32 + 3'u2:p33 + 4'u2:p34 + 5'u2:p35 + 6'u2:p36 + 7'u2:p37 + 8'u2:p38 + 9'u2:p39 + 10'u2:p40 + 11'u2:p41 + 12'u2:p42 + 13'u2:p43 + 14'u2:p44 + 15'u2:p45 + 16'u2:p46 + 17'u2:p47 + 18'u2:p48 + 19'u2:p49 + 20'u2:p50 + 21'u2:p51 + 22'u2:p52 + 23'u2:p53 + 24'u2:p54 + 25'u2:p55 + 26'u2:p56 + 27'u2:p57 + 28'u2:p58 + 29'u2:p59 + 30'u4:p90 + u4:p91 + 2'u4:p92 + 3'u4:p93 + 4'u4:p94 + 5'u4:p95 + 6'u4:p96 + 7'u4:p97 + 8'u4:p98 + 9'u4:p99 + 10'u4:p100 + 11'u4:p101 + 12'u4:p102 + 13'u4:p103 + 14'u4:p104 + 15'u4:p105 + 16'u4:p106 + 17'u4:p107 + 18'u4:p108 + 19'u4:p109 + 20'u4:p110 + 21'u4:p111 + 22'u4:p112 + 23'u4:p113 + 24'u4:p114 + 25'u4:p115 + 26'u4:p116 + 27'u4:p117 + 28'u4:p118 + 29'u4:p119 + u7:p126 + u9:p130 + u11:p132 + u14:p140 + u15:p141 + -1'u18:p148 + u20:p152 + u21:p154 + u23:p158 + -1'u48:p208 + u49:p210 + u50:p212 + -1'u52:p217 + -1'u54:p221 + -1'u60:p213 + -1'u60:p215 + -1'u56:p224 + -1'u58:p231 + -1'u61:p229 + u62:p0 = 1
invariant :u28:p168 + -1'u31:p174 + u36:p184 + -1'u39:p190 + -1'u44:p200 + u47:p206 = 0
invariant :u23:p157 + u23:p158 + u62:p0 = 1
invariant :u30:p171 + u31:p174 + -1'u38:p188 + u39:p190 + u46:p204 + -1'u47:p206 + u62:p0 = 1
invariant :u35:p181 + u35:p182 + u62:p0 = 1
invariant :-58'u1:p1 + -2'u1:p2 + -4'u1:p3 + -6'u1:p4 + -8'u1:p5 + -10'u1:p6 + -12'u1:p7 + -14'u1:p8 + -16'u1:p9 + -18'u1:p10 + -20'u1:p11 + -22'u1:p12 + -24'u1:p13 + -26'u1:p14 + -28'u1:p15 + -30'u1:p16 + -32'u1:p17 + -34'u1:p18 + -36'u1:p19 + -38'u1:p20 + -40'u1:p21 + -42'u1:p22 + -44'u1:p23 + -46'u1:p24 + -48'u1:p25 + -50'u1:p26 + -52'u1:p27 + -54'u1:p28 + -56'u1:p29 + 60'u2:p30 + 2'u2:p31 + 4'u2:p32 + 6'u2:p33 + 8'u2:p34 + 10'u2:p35 + 12'u2:p36 + 14'u2:p37 + 16'u2:p38 + 18'u2:p39 + 20'u2:p40 + 22'u2:p41 + 24'u2:p42 + 26'u2:p43 + 28'u2:p44 + 30'u2:p45 + 32'u2:p46 + 34'u2:p47 + 36'u2:p48 + 38'u2:p49 + 40'u2:p50 + 42'u2:p51 + 44'u2:p52 + 46'u2:p53 + 48'u2:p54 + 50'u2:p55 + 52'u2:p56 + 54'u2:p57 + 56'u2:p58 + 58'u2:p59 + u20:p152 + u21:p154 + u23:p158 + u53:p218 + u54:p220 + u54:p221 + -1'u55:p223 + u60:p214 + -1'u56:p224 + -1'u56:p228 + -1'u58:p231 + -1'u59:p233 + -2'u61:p229 + -1'u62:p0 = -1
invariant :u26:p164 + -1'u31:p174 + u34:p180 + -1'u39:p190 + -1'u42:p196 + u47:p206 = 0
invariant :u40:p191 + u40:p192 + u49:p209 + u49:p210 + u62:p0 = 1
invariant :u18:p147 + u18:p148 + u62:p0 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 4321 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 40 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 108 ms.
FORMULA DES-PT-30a-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DES-PT-30a-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((<>((LTLAP2==true)))U(<>(<>((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 71 ms.
FORMULA DES-PT-30a-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP4==true))U((LTLAP5==true)))U(((LTLAP6==true))U((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 21 ms.
FORMULA DES-PT-30a-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X([](X((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 20 ms.
FORMULA DES-PT-30a-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](<>(<>(<>([]((LTLAP9==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 65 ms.
FORMULA DES-PT-30a-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 63 ms.
FORMULA DES-PT-30a-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](<>((LTLAP11==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 20 ms.
FORMULA DES-PT-30a-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP12==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 110 ms.
FORMULA DES-PT-30a-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](X((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 19 ms.
FORMULA DES-PT-30a-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA DES-PT-30a-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP15==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DES-PT-30a-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(([]([]((LTLAP16==true))))U(<>(<>((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 17 ms.
FORMULA DES-PT-30a-LTLFireability-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](<>(<>([]((LTLAP18==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DES-PT-30a-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP18==true))U([]((LTLAP19==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DES-PT-30a-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 100 ms.
FORMULA DES-PT-30a-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.
BK_STOP 1527895281063
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 11:20:44 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 01, 2018 11:20:44 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 11:20:44 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 100 ms
Jun 01, 2018 11:20:44 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 234 places.
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 191 transitions.
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 11:20:45 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 26 ms
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 114 ms
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 253 redundant transitions.
Jun 01, 2018 11:20:45 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 10 ms
Jun 01, 2018 11:20:45 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 2 ms
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.semantics.CompositeNextBuilder getNextForLabel
INFO: Semantic construction discarded 14 identical transitions.
Jun 01, 2018 11:20:45 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 177 transitions.
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 57 place invariants in 98 ms
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 234 variables to be positive in 612 ms
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 177 transitions.
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/177 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 20 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 177 transitions.
Jun 01, 2018 11:20:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 01, 2018 11:20:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 177 transitions.
Jun 01, 2018 11:20:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/177) took 1772 ms. Total solver calls (SAT/UNSAT): 528(485/43)
Jun 01, 2018 11:20:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/177) took 5023 ms. Total solver calls (SAT/UNSAT): 1547(1294/253)
Jun 01, 2018 11:20:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/177) took 8356 ms. Total solver calls (SAT/UNSAT): 2429(2158/271)
Jun 01, 2018 11:20:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/177) took 11356 ms. Total solver calls (SAT/UNSAT): 3230(2941/289)
Jun 01, 2018 11:21:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/177) took 14675 ms. Total solver calls (SAT/UNSAT): 4019(3710/309)
Jun 01, 2018 11:21:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(54/177) took 17916 ms. Total solver calls (SAT/UNSAT): 4829(4496/333)
Jun 01, 2018 11:21:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(68/177) took 20944 ms. Total solver calls (SAT/UNSAT): 5578(5215/363)
SMT solver raised 'unknown', retrying with same input.
Jun 01, 2018 11:21:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(136/177) took 23976 ms. Total solver calls (SAT/UNSAT): 6879(6367/512)
Jun 01, 2018 11:21:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 24749 ms. Total solver calls (SAT/UNSAT): 6983(6416/567)
Jun 01, 2018 11:21:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 177 transitions.
Jun 01, 2018 11:21:13 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Jun 01, 2018 11:21:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1540 ms. Total solver calls (SAT/UNSAT): 31(0/31)
Jun 01, 2018 11:21:14 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 29017ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-30a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-30a.tgz
mv DES-PT-30a execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DES-PT-30a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r212-smll-152732262800148"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;