Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 8.6K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.1K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 346 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 48K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is AutoFlight-PT-02b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r201-qhx1-152732198000022
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-00
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-01
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-02
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-03
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-04
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-05
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-06
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-07
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-08
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-09
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-10
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-11
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-12
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-13
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-14
FORMULA_NAME AutoFlight-PT-02b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527414431443

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G(G(X(X(G("(i1.i0.i0.i0.u25.p160>=1)")))))))
Formula 0 simplified : !GXXG"(i1.i0.i0.i0.u25.p160>=1)"
built 4 ordering constraints for composite.
built 30 ordering constraints for composite.
built 28 ordering constraints for composite.
built 26 ordering constraints for composite.
built 24 ordering constraints for composite.
built 22 ordering constraints for composite.
built 17 ordering constraints for composite.
built 14 ordering constraints for composite.
built 11 ordering constraints for composite.
built 6 ordering constraints for composite.
built 33 ordering constraints for composite.
built 32 ordering constraints for composite.
built 25 ordering constraints for composite.
built 18 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 204 rows 206 cols
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u19:p120 + i0:u19:p121 + i0:u19:p122 + i0:u19:p123 + i0:u30:p3 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i1:u39:p124 + i1:i0:u41:p125 + i1:i0:i0:u40:p126 + i1:i0:i0:i0:u24:p128 + i1:i0:i0:i0:u24:p129 + i1:i0:i0:i0:u24:p130 + i1:i0:i0:i0:u24:p131 + i1:i0:i0:i0:u24:p132 + i1:i0:i0:i0:u24:p133 + i1:i0:i0:i0:u24:p134 + i1:i0:i0:i0:u24:p135 + i1:i0:i0:i0:u24:p136 + i1:i0:i0:i0:u24:p137 + i1:i0:i0:i0:u24:p138 + i1:i0:i0:i0:u24:p139 + i1:i0:i0:i0:u24:p140 + i1:i0:i0:i0:u24:p141 + i1:i0:i0:i0:u24:p142 + i1:i0:i0:i0:u24:p143 + i1:i0:i0:i0:u24:p144 + i1:i0:i0:i0:u24:p145 + i1:i0:i0:i0:u24:p146 + i1:i0:i0:i0:u24:p147 + i1:i0:i0:i0:u24:p148 + i1:i0:i0:i0:u24:p149 + i1:i0:i0:i0:u24:p150 + i1:i0:i0:i0:u24:p151 + i1:i0:i0:i0:u42:p127 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u15:p73 + i0:i0:i0:i0:i0:u15:p74 + i0:i0:i0:i0:i0:u15:p75 + i0:i0:i0:i0:i0:u15:p76 + i0:i0:i0:i0:i0:u15:p77 + i0:i0:i0:i0:i0:u15:p78 + i0:i0:i0:i0:i0:u15:p79 + i0:i0:i0:i0:i0:u15:p80 + i0:i0:i0:i0:i0:u15:p81 + i0:i0:i0:i0:i0:u15:p82 + i0:i0:i0:i0:i0:u15:p83 + i0:i0:i0:i0:i0:u15:p84 + i0:i0:i0:i0:i0:u15:p85 + i0:i0:i0:i0:i0:u15:p86 + i0:i0:i0:i0:i0:u15:p87 + i0:i0:i0:i0:i0:u15:p88 + i0:i0:i0:i0:i0:u15:p89 + i0:i0:i0:i0:i0:u34:p7 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i1:u39:p124 + i1:i0:u41:p125 + i1:i0:i0:u26:p168 + i1:i0:i0:u26:p169 + i1:i0:i0:u26:p170 + i1:i0:i0:u26:p171 + i1:i0:i0:u26:p172 + i1:i0:i0:u26:p173 + i1:i0:i0:u26:p174 + i1:i0:i0:u26:p175 + i1:i0:i0:u26:p176 + i1:i0:i0:u26:p177 + i1:i0:i0:u26:p178 + i1:i0:i0:u26:p179 + i1:i0:i0:u26:p180 + i1:i0:i0:u26:p181 + i1:i0:i0:u26:p182 + i1:i0:i0:u26:p183 + i1:i0:i0:u26:p184 + i1:i0:i0:u40:p126 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i1:u39:p124 + i1:i0:u27:p185 + i1:i0:u27:p186 + i1:i0:u27:p187 + i1:i0:u27:p188 + i1:i0:u27:p189 + i1:i0:u27:p190 + i1:i0:u27:p191 + i1:i0:u27:p192 + i1:i0:u27:p193 + i1:i0:u27:p194 + i1:i0:u27:p195 + i1:i0:u27:p196 + i1:i0:u27:p197 + i1:i0:u27:p198 + i1:i0:u27:p199 + i1:i0:u27:p200 + i1:i0:u27:p201 + i1:i0:u41:p125 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u34:p7 + i0:i0:i0:i0:i0:i0:u35:p8 + i0:i0:i0:i0:i0:i0:i0:u36:p9 + i0:i0:i0:i0:i0:i0:i0:i0:u37:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p12 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p13 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p14 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p15 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p16 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p17 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p18 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p19 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p20 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p21 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u10:p22 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u38:p11 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u18:p107 + i0:i0:u18:p108 + i0:i0:u18:p109 + i0:i0:u18:p110 + i0:i0:u18:p111 + i0:i0:u18:p112 + i0:i0:u18:p113 + i0:i0:u18:p114 + i0:i0:u18:p115 + i0:i0:u18:p116 + i0:i0:u18:p117 + i0:i0:u18:p118 + i0:i0:u18:p119 + i0:i0:u31:p4 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u16:p90 + i0:i0:i0:i0:u16:p91 + i0:i0:i0:i0:u16:p92 + i0:i0:i0:i0:u16:p93 + i0:i0:i0:i0:u16:p94 + i0:i0:i0:i0:u16:p95 + i0:i0:i0:i0:u16:p96 + i0:i0:i0:i0:u16:p97 + i0:i0:i0:i0:u16:p98 + i0:i0:i0:i0:u16:p99 + i0:i0:i0:i0:u16:p100 + i0:i0:i0:i0:u16:p101 + i0:i0:i0:i0:u16:p102 + i0:i0:i0:i0:u33:p6 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u34:p7 + i0:i0:i0:i0:i0:i0:u35:p8 + i0:i0:i0:i0:i0:i0:i0:u36:p9 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p34 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p35 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p36 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p37 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p38 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p39 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p40 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p41 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p42 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p43 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p44 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p45 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p46 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p47 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p48 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p49 + i0:i0:i0:i0:i0:i0:i0:i0:u12:p50 + i0:i0:i0:i0:i0:i0:i0:i0:u37:p10 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u34:p7 + i0:i0:i0:i0:i0:i0:u14:p62 + i0:i0:i0:i0:i0:i0:u14:p63 + i0:i0:i0:i0:i0:i0:u14:p64 + i0:i0:i0:i0:i0:i0:u14:p65 + i0:i0:i0:i0:i0:i0:u14:p66 + i0:i0:i0:i0:i0:i0:u14:p67 + i0:i0:i0:i0:i0:i0:u14:p68 + i0:i0:i0:i0:i0:i0:u14:p69 + i0:i0:i0:i0:i0:i0:u14:p70 + i0:i0:i0:i0:i0:i0:u14:p71 + i0:i0:i0:i0:i0:i0:u14:p72 + i0:i0:i0:i0:i0:i0:u35:p8 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u34:p7 + i0:i0:i0:i0:i0:i0:u35:p8 + i0:i0:i0:i0:i0:i0:i0:u13:p51 + i0:i0:i0:i0:i0:i0:i0:u13:p52 + i0:i0:i0:i0:i0:i0:i0:u13:p53 + i0:i0:i0:i0:i0:i0:i0:u13:p54 + i0:i0:i0:i0:i0:i0:i0:u13:p55 + i0:i0:i0:i0:i0:i0:i0:u13:p56 + i0:i0:i0:i0:i0:i0:i0:u13:p57 + i0:i0:i0:i0:i0:i0:i0:u13:p58 + i0:i0:i0:i0:i0:i0:i0:u13:p59 + i0:i0:i0:i0:i0:i0:i0:u13:p60 + i0:i0:i0:i0:i0:i0:i0:u13:p61 + i0:i0:i0:i0:i0:i0:i0:u36:p9 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i1:u28:p202 + i1:u28:p203 + i1:u39:p124 + i1:i0:u27:p187 + i1:i0:u27:p188 + i1:i0:u27:p189 + i1:i0:u27:p190 + i1:i0:u27:p191 + i1:i0:u27:p192 + i1:i0:u27:p193 + i1:i0:i0:u26:p170 + i1:i0:i0:u26:p171 + i1:i0:i0:u26:p172 + i1:i0:i0:u26:p173 + i1:i0:i0:u26:p174 + i1:i0:i0:u26:p175 + i1:i0:i0:u26:p176 + i1:i0:i0:i0:u24:p130 + i1:i0:i0:i0:u24:p131 + i1:i0:i0:i0:u24:p132 + i1:i0:i0:i0:u24:p133 + i1:i0:i0:i0:u24:p134 + i1:i0:i0:i0:u24:p135 + i1:i0:i0:i0:u24:p136 + i1:i0:i0:i0:u24:p137 + i1:i0:i0:i0:u24:p138 + i1:i0:i0:i0:u24:p139 + i1:i0:i0:i0:u24:p140 + i1:i0:i0:i0:u24:p141 + i1:i0:i0:i0:u24:p142 + i1:i0:i0:i0:u25:p154 + i1:i0:i0:i0:u25:p155 + i1:i0:i0:i0:u25:p156 + i1:i0:i0:i0:u25:p157 + i1:i0:i0:i0:u25:p158 + i1:i0:i0:i0:u25:p159 + i1:i0:i0:i0:u25:p160 + i1:i0:i0:i0:u25:p161 + i1:i0:i0:i0:u25:p162 + i1:i0:i0:i0:u25:p163 + i1:i0:i0:i0:u25:p164 = 1
invariant :i1:u28:p204 + i1:u28:p205 + -1'i1:i0:u27:p187 + -1'i1:i0:u27:p188 + -1'i1:i0:u27:p189 + -1'i1:i0:u27:p190 + -1'i1:i0:u27:p191 + -1'i1:i0:u27:p192 + -1'i1:i0:u27:p193 + -1'i1:i0:i0:u26:p170 + -1'i1:i0:i0:u26:p171 + -1'i1:i0:i0:u26:p172 + -1'i1:i0:i0:u26:p173 + -1'i1:i0:i0:u26:p174 + -1'i1:i0:i0:u26:p175 + -1'i1:i0:i0:u26:p176 + -1'i1:i0:i0:i0:u24:p130 + -1'i1:i0:i0:i0:u24:p131 + -1'i1:i0:i0:i0:u24:p132 + -1'i1:i0:i0:i0:u24:p133 + -1'i1:i0:i0:i0:u24:p134 + -1'i1:i0:i0:i0:u24:p135 + -1'i1:i0:i0:i0:u24:p136 + -1'i1:i0:i0:i0:u24:p137 + -1'i1:i0:i0:i0:u24:p138 + -1'i1:i0:i0:i0:u24:p139 + -1'i1:i0:i0:i0:u24:p140 + -1'i1:i0:i0:i0:u24:p141 + -1'i1:i0:i0:i0:u24:p142 + -1'i1:i0:i0:i0:u25:p154 + -1'i1:i0:i0:i0:u25:p155 + -1'i1:i0:i0:i0:u25:p156 + -1'i1:i0:i0:i0:u25:p157 + -1'i1:i0:i0:i0:u25:p158 + -1'i1:i0:i0:i0:u25:p159 + -1'i1:i0:i0:i0:u25:p160 + -1'i1:i0:i0:i0:u25:p161 + -1'i1:i0:i0:i0:u25:p162 + -1'i1:i0:i0:i0:u25:p163 + -1'i1:i0:i0:i0:u25:p164 = 0
invariant :u29:p0 + u29:p1 + u29:p2 + i1:u39:p124 + i1:i0:u41:p125 + i1:i0:i0:u40:p126 + i1:i0:i0:i0:u25:p152 + i1:i0:i0:i0:u25:p153 + i1:i0:i0:i0:u25:p154 + i1:i0:i0:i0:u25:p155 + i1:i0:i0:i0:u25:p156 + i1:i0:i0:i0:u25:p157 + i1:i0:i0:i0:u25:p158 + i1:i0:i0:i0:u25:p159 + i1:i0:i0:i0:u25:p160 + i1:i0:i0:i0:u25:p161 + i1:i0:i0:i0:u25:p162 + i1:i0:i0:i0:u25:p163 + i1:i0:i0:i0:u25:p164 + i1:i0:i0:i0:u25:p165 + i1:i0:i0:i0:u25:p166 + i1:i0:i0:i0:u25:p167 + i1:i0:i0:i0:u42:p127 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u17:p103 + i0:i0:i0:u17:p104 + i0:i0:i0:u17:p105 + i0:i0:i0:u17:p106 + i0:i0:i0:u32:p5 = 1
invariant :u29:p0 + u29:p1 + u29:p2 + i0:u30:p3 + i0:i0:u31:p4 + i0:i0:i0:u32:p5 + i0:i0:i0:i0:u33:p6 + i0:i0:i0:i0:i0:u34:p7 + i0:i0:i0:i0:i0:i0:u35:p8 + i0:i0:i0:i0:i0:i0:i0:u36:p9 + i0:i0:i0:i0:i0:i0:i0:i0:u37:p10 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p23 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p24 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p25 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p26 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p27 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p28 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p29 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p30 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p31 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p32 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u11:p33 + i0:i0:i0:i0:i0:i0:i0:i0:i0:u38:p11 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 5215 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 107 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](X(X([]((LTLAP0==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 170 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](<>(X(<>((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions t73, t89, t196, t197, t198, t199, i0.u19.t75, i0.i0.u18.t78, i0.i0.u18.t88, i0.i0.i0.u17.t91, i0.i0.i0.i0.u16.t94, i0.i0.i0.i0.u16.t104, i0.i0.i0.i0.i0.u15.t16, i0.i0.i0.i0.i0.u15.t17, i0.i0.i0.i0.i0.u15.t18, i0.i0.i0.i0.i0.u15.t19, i0.i0.i0.i0.i0.u15.t109, i0.i0.i0.i0.i0.u15.t117, i0.i0.i0.i0.i0.i0.u14.t13, i0.i0.i0.i0.i0.i0.u14.t14, i0.i0.i0.i0.i0.i0.u14.t15, i0.i0.i0.i0.i0.i0.u14.t120, i0.i0.i0.i0.i0.i0.u14.t127, i0.i0.i0.i0.i0.i0.i0.u13.t10, i0.i0.i0.i0.i0.i0.i0.u13.t11, i0.i0.i0.i0.i0.i0.i0.u13.t12, i0.i0.i0.i0.i0.i0.i0.u13.t130, i0.i0.i0.i0.i0.i0.i0.u13.t137, i0.i0.i0.i0.i0.i0.i0.i0.u12.t6, i0.i0.i0.i0.i0.i0.i0.i0.u12.t7, i0.i0.i0.i0.i0.i0.i0.i0.u12.t8, i0.i0.i0.i0.i0.i0.i0.i0.u12.t9, i0.i0.i0.i0.i0.i0.i0.i0.u12.t142, i0.i0.i0.i0.i0.i0.i0.i0.u12.t150, i0.i0.i0.i0.i0.i0.i0.i0.i0.u10.t0, i0.i0.i0.i0.i0.i0.i0.i0.i0.u10.t1, i0.i0.i0.i0.i0.i0.i0.i0.i0.u10.t2, i0.i0.i0.i0.i0.i0.i0.i0.i0.u10.t162, i0.i0.i0.i0.i0.i0.i0.i0.i0.u10.t169, i0.i0.i0.i0.i0.i0.i0.i0.i0.u11.t3, i0.i0.i0.i0.i0.i0.i0.i0.i0.u11.t4, i0.i0.i0.i0.i0.i0.i0.i0.i0.u11.t5, i0.i0.i0.i0.i0.i0.i0.i0.i0.u11.t153, i0.i0.i0.i0.i0.i0.i0.i0.i0.u11.t160, i1.u28.t29, i1.i0.u27.t38, i1.i0.u27.t41, i1.i0.i0.u26.t50, i1.i0.i0.u26.t53, i1.i0.i0.i0.u24.t69, i1.i0.i0.i0.u24.t72, i1.i0.i0.i0.u25.t57, i1.i0.i0.i0.u25.t60, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/151/53/204
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](<>(X(<>((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP2==true)))U(<>((LTLAP3==true))))U((<>((LTLAP4==true)))U([]((LTLAP5==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 333 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 178 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X(([]((LTLAP7==true)))U((LTLAP8==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 152 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](((LTLAP9==true))U((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 165 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([](X([]((LTLAP11==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 134 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP12==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 165 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(([]([]((LTLAP13==true))))U(X((LTLAP14==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 155 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 168 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(([]((LTLAP16==true)))U([]((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 186 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 192 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>((LTLAP18==true))))U(X(((LTLAP19==true))U((LTLAP20==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Computing Next relation with stutter on 40 deadlock states
LTSmin run took 34495 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP21==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 277 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X([]((LTLAP7==true)))))U((LTLAP22==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 242 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](<>([]((LTLAP23==true)))))U((LTLAP24==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 211 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](<>(X(<>((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 151 ms.
FORMULA AutoFlight-PT-02b-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527414735127

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 27, 2018 9:47:30 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 27, 2018 9:47:30 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 27, 2018 9:47:30 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 86 ms
May 27, 2018 9:47:30 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 206 places.
May 27, 2018 9:47:30 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 204 transitions.
May 27, 2018 9:47:30 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 27, 2018 9:47:30 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 19 ms
May 27, 2018 9:47:30 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 27, 2018 9:47:30 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 114 ms
May 27, 2018 9:47:30 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 49 ms
May 27, 2018 9:47:30 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 27, 2018 9:47:30 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 39 ms
May 27, 2018 9:47:30 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 27, 2018 9:47:31 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 6 redundant transitions.
May 27, 2018 9:47:31 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 44 ms
May 27, 2018 9:47:31 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 3 ms
May 27, 2018 9:47:31 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 204 transitions.
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 16 place invariants in 90 ms
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 206 variables to be positive in 595 ms
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 204 transitions.
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/204 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 17 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 204 transitions.
May 27, 2018 9:47:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 12 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 9:47:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 204 transitions.
May 27, 2018 9:47:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/204) took 1185 ms. Total solver calls (SAT/UNSAT): 604(0/604)
May 27, 2018 9:47:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/204) took 4336 ms. Total solver calls (SAT/UNSAT): 2824(42/2782)
May 27, 2018 9:47:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(118/204) took 7363 ms. Total solver calls (SAT/UNSAT): 3439(49/3390)
May 27, 2018 9:47:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(197/204) took 10376 ms. Total solver calls (SAT/UNSAT): 3988(68/3920)
May 27, 2018 9:47:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 10660 ms. Total solver calls (SAT/UNSAT): 4003(68/3935)
May 27, 2018 9:47:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 204 transitions.
May 27, 2018 9:47:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 38 ms. Total solver calls (SAT/UNSAT): 4(0/4)
May 27, 2018 9:47:45 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 14136ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-02b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-02b.tgz
mv AutoFlight-PT-02b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is AutoFlight-PT-02b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r201-qhx1-152732198000022"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;