Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.............................................................................
/home/mcc/execution
total 344K
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.2K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 346 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 169K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is AutoFlight-PT-24a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r200-qhx1-152732197100044
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-00
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-01
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-02
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-03
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-04
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-05
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-06
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-07
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-08
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-09
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-10
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-11
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-12
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-13
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-14
FORMULA_NAME AutoFlight-PT-24a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527408190311

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((((X("((u48.p112>=1)&&(u122.p427>=1))"))U("((u24.p56>=1)&&(u122.p371>=1))"))U(G(F(F("(u55.p128>=1)"))))))
Formula 0 simplified : !((X"((u48.p112>=1)&&(u122.p427>=1))" U "((u24.p56>=1)&&(u122.p371>=1))") U GF"(u55.p128>=1)")
built 219 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 485 rows 607 cols
invariant :u27:p63 + u148:p0 = 1
invariant :u115:p232 + u115:p233 + u148:p0 = 1
invariant :u139:p557 + u139:p558 + u139:p559 + u139:p560 + u139:p561 + u139:p562 + u148:p0 = 1
invariant :u134:p527 + u134:p528 + u134:p529 + u134:p530 + u134:p531 + u134:p532 + u148:p0 = 1
invariant :u76:p174 + u148:p0 = 1
invariant :u135:p533 + u135:p534 + u135:p535 + u135:p536 + u135:p537 + u135:p538 + u148:p0 = 1
invariant :u106:p219 + u148:p0 = 1
invariant :u64:p148 + u64:p149 + u64:p150 + u148:p0 = 1
invariant :u114:p231 + u148:p0 = 1
invariant :u104:p216 + u148:p0 = 1
invariant :u40:p92 + u40:p93 + u40:p94 + u148:p0 = 1
invariant :u96:p204 + u148:p0 = 1
invariant :u3:p7 + u148:p0 = 1
invariant :u57:p133 + u148:p0 = 1
invariant :u97:p205 + u97:p206 + u148:p0 = 1
invariant :u103:p214 + u103:p215 + u148:p0 = 1
invariant :u62:p144 + u62:p145 + u62:p146 + u148:p0 = 1
invariant :u83:p184 + u83:p185 + u148:p0 = 1
invariant :u126:p479 + u126:p480 + u126:p481 + u126:p482 + u126:p483 + u126:p484 + u148:p0 = 1
invariant :u92:p198 + u148:p0 = 1
invariant :u121:p241 + u121:p242 + u121:p243 + u121:p244 + u121:p245 + u121:p246 + u121:p247 + u121:p248 + u121:p249 + u121:p250 + u121:p251 + u121:p252 + u121:p253 + u121:p254 + u121:p255 + u121:p256 + u121:p257 + u121:p258 + u121:p259 + u121:p260 + u121:p261 + u121:p262 + u121:p263 + u121:p264 + u121:p265 + u121:p266 + u121:p267 + u121:p268 + u121:p269 + u121:p270 + u121:p271 + u121:p272 + u121:p273 + u121:p274 + u121:p275 + u121:p276 + u121:p277 + u121:p278 + u121:p279 + u121:p280 + u121:p281 + u121:p282 + u121:p283 + u121:p284 + u121:p285 + u121:p286 + u121:p287 + u121:p288 + u121:p289 + u121:p290 + u121:p291 + u121:p292 + u121:p293 + u121:p294 + u121:p295 + u121:p296 + u121:p297 + u121:p298 + u121:p299 + u121:p300 + u121:p301 + u121:p302 + u121:p303 + u121:p304 + u121:p305 + u121:p306 + u121:p307 + u121:p308 + u121:p309 + u121:p310 + u121:p311 + u121:p312 + u121:p313 + u121:p314 + u121:p315 + u121:p316 + u121:p317 + u121:p318 + u121:p319 + u121:p320 + u121:p321 + u121:p322 + u121:p323 + u121:p324 + u121:p325 + u121:p326 + u121:p327 + u121:p328 + u121:p329 + u121:p330 + u121:p331 + u121:p332 + u121:p333 + u121:p334 + u121:p335 + u121:p336 + u121:p337 + u121:p338 + u121:p339 + u121:p340 + u121:p341 + u121:p342 + u121:p343 + u121:p344 + u121:p345 + u121:p346 + u121:p347 + u121:p348 + u121:p349 + u121:p350 + u121:p351 + u121:p352 + u121:p353 + u121:p354 + u121:p355 + u121:p356 + u121:p357 + u121:p358 + u121:p359 + u121:p360 + u121:p361 + -1'u122:p460 + -1'u123:p466 + -1'u124:p472 + -1'u125:p478 + -1'u126:p484 + -1'u127:p490 + -1'u128:p496 + -1'u129:p502 + -1'u130:p508 + -1'u131:p514 + -1'u132:p520 + -1'u133:p526 + -1'u134:p532 + -1'u135:p538 + -1'u136:p544 + -1'u137:p550 + -1'u138:p556 + -1'u139:p562 + -1'u140:p568 + -1'u141:p574 + -1'u142:p580 + -1'u143:p586 + -1'u144:p592 + -1'u145:p598 + -1'u146:p604 + -1'u147:p606 + -25'u148:p0 = -25
invariant :u142:p575 + u142:p576 + u142:p577 + u142:p578 + u142:p579 + u142:p580 + u148:p0 = 1
invariant :u86:p189 + u148:p0 = 1
invariant :u20:p46 + u20:p47 + u20:p48 + u148:p0 = 1
invariant :u29:p67 + u29:p68 + u29:p69 + u148:p0 = 1
invariant :u39:p91 + u148:p0 = 1
invariant :u117:p235 + u117:p236 + u148:p0 = 1
invariant :u136:p539 + u136:p540 + u136:p541 + u136:p542 + u136:p543 + u136:p544 + u148:p0 = 1
invariant :u72:p168 + u148:p0 = 1
invariant :u32:p74 + u32:p75 + u32:p76 + u148:p0 = 1
invariant :u69:p161 + u148:p0 = 1
invariant :u118:p237 + u148:p0 = 1
invariant :u137:p545 + u137:p546 + u137:p547 + u137:p548 + u137:p549 + u137:p550 + u148:p0 = 1
invariant :u44:p102 + u44:p103 + u44:p104 + u148:p0 = 1
invariant :u100:p210 + u148:p0 = 1
invariant :u140:p563 + u140:p564 + u140:p565 + u140:p566 + u140:p567 + u140:p568 + u148:p0 = 1
invariant :u37:p85 + u37:p86 + u37:p87 + u148:p0 = 1
invariant :u75:p172 + u75:p173 + u148:p0 = 1
invariant :u53:p123 + u53:p124 + u53:p125 + u148:p0 = 1
invariant :u105:p217 + u105:p218 + u148:p0 = 1
invariant :u108:p222 + u148:p0 = 1
invariant :u7:p15 + u7:p16 + u7:p17 + u148:p0 = 1
invariant :u87:p190 + u87:p191 + u148:p0 = 1
invariant :u51:p119 + u148:p0 = 1
invariant :u31:p71 + u31:p72 + u31:p73 + u148:p0 = 1
invariant :u56:p130 + u56:p131 + u56:p132 + u148:p0 = 1
invariant :u93:p199 + u93:p200 + u148:p0 = 1
invariant :u49:p113 + u49:p114 + u49:p115 + u148:p0 = 1
invariant :u43:p99 + u43:p100 + u43:p101 + u148:p0 = 1
invariant :u145:p593 + u145:p594 + u145:p595 + u145:p596 + u145:p597 + u145:p598 + u148:p0 = 1
invariant :u98:p207 + u148:p0 = 1
invariant :u71:p165 + u71:p166 + u71:p167 + u148:p0 = 1
invariant :u59:p137 + u59:p138 + u59:p139 + u148:p0 = 1
invariant :u124:p467 + u124:p468 + u124:p469 + u124:p470 + u124:p471 + u124:p472 + u148:p0 = 1
invariant :u68:p158 + u68:p159 + u68:p160 + u148:p0 = 1
invariant :u79:p178 + u79:p179 + u148:p0 = 1
invariant :u38:p88 + u38:p89 + u38:p90 + u148:p0 = 1
invariant :u60:p140 + u148:p0 = 1
invariant :u41:p95 + u41:p96 + u41:p97 + u148:p0 = 1
invariant :u8:p18 + u8:p19 + u8:p20 + u148:p0 = 1
invariant :u52:p120 + u52:p121 + u52:p122 + u148:p0 = 1
invariant :u129:p497 + u129:p498 + u129:p499 + u129:p500 + u129:p501 + u129:p502 + u148:p0 = 1
invariant :u24:p56 + u148:p0 = 1
invariant :u42:p98 + u148:p0 = 1
invariant :u66:p154 + u148:p0 = 1
invariant :u36:p84 + u148:p0 = 1
invariant :u12:p28 + u148:p0 = 1
invariant :u138:p551 + u138:p552 + u138:p553 + u138:p554 + u138:p555 + u138:p556 + u148:p0 = 1
invariant :u74:p171 + u148:p0 = 1
invariant :u109:p223 + u109:p224 + u148:p0 = 1
invariant :u33:p77 + u148:p0 = 1
invariant :u123:p461 + u123:p462 + u123:p463 + u123:p464 + u123:p465 + u123:p466 + u148:p0 = 1
invariant :u121:p362 + u122:p460 + u123:p466 + u124:p472 + u125:p478 + u126:p484 + u127:p490 + u128:p496 + u129:p502 + u130:p508 + u131:p514 + u132:p520 + u133:p526 + u134:p532 + u135:p538 + u136:p544 + u137:p550 + u138:p556 + u139:p562 + u140:p568 + u141:p574 + u142:p580 + u143:p586 + u144:p592 + u145:p598 + u146:p604 + u147:p606 + 26'u148:p0 = 26
invariant :u22:p50 + u22:p51 + u22:p52 + u148:p0 = 1
invariant :u46:p106 + u46:p107 + u46:p108 + u148:p0 = 1
invariant :u25:p57 + u25:p58 + u25:p59 + u148:p0 = 1
invariant :u116:p234 + u148:p0 = 1
invariant :u119:p238 + u119:p239 + u148:p0 = 1
invariant :u47:p109 + u47:p110 + u47:p111 + u148:p0 = 1
invariant :u122:p363 + u122:p364 + u122:p365 + u122:p366 + u122:p367 + u122:p368 + u122:p369 + u122:p370 + u122:p371 + u122:p372 + u122:p373 + u122:p374 + u122:p375 + u122:p376 + u122:p377 + u122:p378 + u122:p379 + u122:p380 + u122:p381 + u122:p382 + u122:p383 + u122:p384 + u122:p385 + u122:p386 + u122:p387 + u122:p388 + u122:p389 + u122:p390 + u122:p391 + u122:p392 + u122:p393 + u122:p394 + u122:p395 + u122:p396 + u122:p397 + u122:p398 + u122:p399 + u122:p400 + u122:p401 + u122:p402 + u122:p403 + u122:p404 + u122:p405 + u122:p406 + u122:p407 + u122:p408 + u122:p409 + u122:p410 + u122:p411 + u122:p412 + u122:p413 + u122:p414 + u122:p415 + u122:p416 + u122:p417 + u122:p418 + u122:p419 + u122:p420 + u122:p421 + u122:p422 + u122:p423 + u122:p424 + u122:p425 + u122:p426 + u122:p427 + u122:p428 + u122:p429 + u122:p430 + u122:p431 + u122:p432 + u122:p433 + u122:p434 + u122:p435 + u122:p436 + u122:p437 + u122:p438 + u122:p439 + u122:p440 + u122:p441 + u122:p442 + u122:p443 + u122:p444 + u122:p445 + u122:p446 + u122:p447 + u122:p448 + u122:p449 + u122:p450 + u122:p451 + u122:p452 + u122:p453 + u122:p454 + u122:p455 + u122:p456 + u122:p457 + u122:p458 + u122:p459 + u122:p460 + u148:p0 = 1
invariant :u16:p36 + u16:p37 + u16:p38 + u148:p0 = 1
invariant :u45:p105 + u148:p0 = 1
invariant :u67:p155 + u67:p156 + u67:p157 + u148:p0 = 1
invariant :u128:p491 + u128:p492 + u128:p493 + u128:p494 + u128:p495 + u128:p496 + u148:p0 = 1
invariant :u127:p485 + u127:p486 + u127:p487 + u127:p488 + u127:p489 + u127:p490 + u148:p0 = 1
invariant :u5:p11 + u5:p12 + u5:p13 + u148:p0 = 1
invariant :u58:p134 + u58:p135 + u58:p136 + u148:p0 = 1
invariant :u120:p240 + u148:p0 = 1
invariant :u94:p201 + u148:p0 = 1
invariant :u90:p195 + u148:p0 = 1
invariant :u26:p60 + u26:p61 + u26:p62 + u148:p0 = 1
invariant :u55:p127 + u55:p128 + u55:p129 + u148:p0 = 1
invariant :u107:p220 + u107:p221 + u148:p0 = 1
invariant :u82:p183 + u148:p0 = 1
invariant :u15:p35 + u148:p0 = 1
invariant :u144:p587 + u144:p588 + u144:p589 + u144:p590 + u144:p591 + u144:p592 + u148:p0 = 1
invariant :u19:p43 + u19:p44 + u19:p45 + u148:p0 = 1
invariant :u6:p14 + u148:p0 = 1
invariant :u10:p22 + u10:p23 + u10:p24 + u148:p0 = 1
invariant :u77:p175 + u77:p176 + u148:p0 = 1
invariant :u91:p196 + u91:p197 + u148:p0 = 1
invariant :u11:p25 + u11:p26 + u11:p27 + u148:p0 = 1
invariant :u30:p70 + u148:p0 = 1
invariant :u125:p473 + u125:p474 + u125:p475 + u125:p476 + u125:p477 + u125:p478 + u148:p0 = 1
invariant :u146:p599 + u146:p600 + u146:p601 + u146:p602 + u146:p603 + u146:p604 + u148:p0 = 1
invariant :u17:p39 + u17:p40 + u17:p41 + u148:p0 = 1
invariant :u1:p1 + u1:p2 + u1:p3 + u148:p0 = 1
invariant :u35:p81 + u35:p82 + u35:p83 + u148:p0 = 1
invariant :u28:p64 + u28:p65 + u28:p66 + u148:p0 = 1
invariant :u4:p8 + u4:p9 + u4:p10 + u148:p0 = 1
invariant :u18:p42 + u148:p0 = 1
invariant :u34:p78 + u34:p79 + u34:p80 + u148:p0 = 1
invariant :u63:p147 + u148:p0 = 1
invariant :u13:p29 + u13:p30 + u13:p31 + u148:p0 = 1
invariant :u89:p193 + u89:p194 + u148:p0 = 1
invariant :u99:p208 + u99:p209 + u148:p0 = 1
invariant :u65:p151 + u65:p152 + u65:p153 + u148:p0 = 1
invariant :u81:p181 + u81:p182 + u148:p0 = 1
invariant :u84:p186 + u148:p0 = 1
invariant :u2:p4 + u2:p5 + u2:p6 + u148:p0 = 1
invariant :u143:p581 + u143:p582 + u143:p583 + u143:p584 + u143:p585 + u143:p586 + u148:p0 = 1
invariant :u112:p228 + u148:p0 = 1
invariant :u54:p126 + u148:p0 = 1
invariant :u113:p229 + u113:p230 + u148:p0 = 1
invariant :u9:p21 + u148:p0 = 1
invariant :u101:p211 + u101:p212 + u148:p0 = 1
invariant :u110:p225 + u148:p0 = 1
invariant :u61:p141 + u61:p142 + u61:p143 + u148:p0 = 1
invariant :u131:p509 + u131:p510 + u131:p511 + u131:p512 + u131:p513 + u131:p514 + u148:p0 = 1
invariant :u70:p162 + u70:p163 + u70:p164 + u148:p0 = 1
invariant :u50:p116 + u50:p117 + u50:p118 + u148:p0 = 1
invariant :u141:p569 + u141:p570 + u141:p571 + u141:p572 + u141:p573 + u141:p574 + u148:p0 = 1
invariant :u95:p202 + u95:p203 + u148:p0 = 1
invariant :u102:p213 + u148:p0 = 1
invariant :u14:p32 + u14:p33 + u14:p34 + u148:p0 = 1
invariant :u147:p605 + u147:p606 + u148:p0 = 1
invariant :u133:p521 + u133:p522 + u133:p523 + u133:p524 + u133:p525 + u133:p526 + u148:p0 = 1
invariant :u21:p49 + u148:p0 = 1
invariant :u88:p192 + u148:p0 = 1
invariant :u23:p53 + u23:p54 + u23:p55 + u148:p0 = 1
invariant :u130:p503 + u130:p504 + u130:p505 + u130:p506 + u130:p507 + u130:p508 + u148:p0 = 1
invariant :u85:p187 + u85:p188 + u148:p0 = 1
invariant :u48:p112 + u148:p0 = 1
invariant :u132:p515 + u132:p516 + u132:p517 + u132:p518 + u132:p519 + u132:p520 + u148:p0 = 1
invariant :u73:p169 + u73:p170 + u148:p0 = 1
invariant :u80:p180 + u148:p0 = 1
invariant :u111:p226 + u111:p227 + u148:p0 = 1
invariant :u78:p177 + u148:p0 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12228 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 92 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((X((LTLAP0==true)))U((LTLAP1==true)))U([](<>(<>((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 357 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X([]((LTLAP3==true))))U(<>(X((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 323 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1465 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1270 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP7==true)))U(X([]([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 314 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X([](X((LTLAP9==true)))))U((LTLAP10==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 337 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(([](X((LTLAP11==true))))U(X(X((LTLAP12==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 352 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1257 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1276 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X(X([]((LTLAP15==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 308 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([](<>((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 337 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(<>((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 345 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X(<>((LTLAP18==true))))U((LTLAP19==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 81 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1057 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (([]((LTLAP21==true)))U([]((LTLAP22==true))))U((X((LTLAP23==true)))U([]((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 539 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](<>([]([]((LTLAP25==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 314 ms.
FORMULA AutoFlight-PT-24a-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527408279060

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 27, 2018 8:03:20 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 27, 2018 8:03:20 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 27, 2018 8:03:20 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 138 ms
May 27, 2018 8:03:20 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 607 places.
May 27, 2018 8:03:20 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 605 transitions.
May 27, 2018 8:03:20 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 27, 2018 8:03:20 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 40 ms
May 27, 2018 8:03:20 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 27, 2018 8:03:21 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 27, 2018 8:03:21 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 201 ms
May 27, 2018 8:03:21 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 27, 2018 8:03:21 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 122 redundant transitions.
May 27, 2018 8:03:21 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 23 ms
May 27, 2018 8:03:21 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 2 ms
May 27, 2018 8:03:22 AM fr.lip6.move.gal.semantics.CompositeNextBuilder getNextForLabel
INFO: Semantic construction discarded 120 identical transitions.
May 27, 2018 8:03:22 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 485 transitions.
May 27, 2018 8:03:23 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 148 place invariants in 394 ms
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 607 variables to be positive in 2292 ms
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 485 transitions.
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/485 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 62 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 485 transitions.
May 27, 2018 8:03:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 18 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 8:03:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 485 transitions.
May 27, 2018 8:03:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/485) took 495 ms. Total solver calls (SAT/UNSAT): 484(0/484)
May 27, 2018 8:03:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(51/485) took 3566 ms. Total solver calls (SAT/UNSAT): 1249(537/712)
May 27, 2018 8:03:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/485) took 6899 ms. Total solver calls (SAT/UNSAT): 2248(1536/712)
May 27, 2018 8:03:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(63/485) took 10097 ms. Total solver calls (SAT/UNSAT): 3211(2499/712)
May 27, 2018 8:03:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/485) took 13228 ms. Total solver calls (SAT/UNSAT): 4138(3426/712)
May 27, 2018 8:03:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/485) took 16366 ms. Total solver calls (SAT/UNSAT): 5029(4317/712)
May 27, 2018 8:03:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/485) took 19874 ms. Total solver calls (SAT/UNSAT): 6023(5311/712)
May 27, 2018 8:03:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/485) took 23154 ms. Total solver calls (SAT/UNSAT): 6968(6256/712)
May 27, 2018 8:03:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(97/485) took 26305 ms. Total solver calls (SAT/UNSAT): 7988(7274/714)
May 27, 2018 8:03:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/485) took 29568 ms. Total solver calls (SAT/UNSAT): 8832(8100/732)
May 27, 2018 8:04:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(111/485) took 32663 ms. Total solver calls (SAT/UNSAT): 9626(8877/749)
May 27, 2018 8:04:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/485) took 35980 ms. Total solver calls (SAT/UNSAT): 10474(9705/769)
May 27, 2018 8:04:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(152/485) took 39010 ms. Total solver calls (SAT/UNSAT): 13184(9804/3380)
May 27, 2018 8:04:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(204/485) took 42038 ms. Total solver calls (SAT/UNSAT): 15121(9810/5311)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 27, 2018 8:04:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 44260 ms. Total solver calls (SAT/UNSAT): 15294(9830/5464)
May 27, 2018 8:04:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 485 transitions.
May 27, 2018 8:04:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1821 ms. Total solver calls (SAT/UNSAT): 868(0/868)
May 27, 2018 8:04:15 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 53381ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-24a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-24a.tgz
mv AutoFlight-PT-24a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is AutoFlight-PT-24a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r200-qhx1-152732197100044"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;