About the Execution of ITS-Tools for QuasiCertifProtocol-COL-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15744.930 | 333530.00 | 663525.00 | 998.70 | FFFFFFTFFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
........................................................
/home/mcc/execution
total 240K
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.8K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.5K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 117 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 355 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 72K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is QuasiCertifProtocol-COL-10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r188-qhx2-152732140200046
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-00
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-01
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-02
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-03
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-04
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-05
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-06
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-07
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-08
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-09
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-10
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-11
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-12
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-13
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-14
FORMULA_NAME QuasiCertifProtocol-COL-10-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1528281085863
10:31:50.339 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
10:31:50.344 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]
its-ltl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F("((((((((((((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid0.c1_0>=1))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid1.c1_1>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid2.c1_2>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid3.c1_3>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid4.c1_4>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid5.c1_5>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid6.c1_6>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid7.c1_7>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid8.c1_8>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid9.c1_9>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid10.c1_10>=1)))")))
Formula 0 simplified : !F"((((((((((((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid0.c1_0>=1))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid1.c1_1>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid2.c1_2>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid3.c1_3>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid4.c1_4>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid5.c1_5>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid6.c1_6>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid7.c1_7>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid8.c1_8>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid9.c1_9>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid10.c1_10>=1)))"
built 57 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 176 rows 550 cols
invariant :tsidxtsid33:n9_33 + tsid0:CstopOK_0 + -1'tsid3:SstopOK_3 = 0
invariant :tsidxtsid71:n7_71 + -1'tsidxtsid76:n7_76 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid92:n8_92 + -1'tsidxtsid98:n8_98 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid52:n7_52 + -1'tsidxtsid54:n7_54 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid82:n7_82 + -1'tsidxtsid87:n7_87 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid104:n9_104 + tsid5:CstopOK_5 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid92:n9_92 + tsid4:CstopOK_4 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid69:n7_69 + -1'tsidxtsid76:n7_76 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid108:n7_108 + -1'tsidxtsid109:n7_109 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid20:n7_20 + -1'tsidxtsid21:n7_21 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid17:n9_17 + -1'tsid1:SstopOK_1 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid51:n9_51 + -1'tsid4:SstopOK_4 + tsid7:CstopOK_7 = 0
invariant :tsidxtsid41:n9_41 + -1'tsid3:SstopOK_3 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid111:n8_111 + -1'tsidxtsid120:n8_120 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid111:n7_111 + -1'tsidxtsid120:n7_120 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid74:n7_74 + -1'tsidxtsid76:n7_76 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid90:n7_90 + -1'tsidxtsid98:n7_98 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid45:n9_45 + tsid1:CstopOK_1 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid12:n8_12 + -1'tsidxtsid21:n8_21 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid41:n7_41 + -1'tsidxtsid43:n7_43 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid83:n8_83 + -1'tsidxtsid87:n8_87 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsid8:n6_8 + tsid8:n5_8 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid114:n8_114 + -1'tsidxtsid120:n8_120 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid74:n9_74 + -1'tsid6:SstopOK_6 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid80:n9_80 + tsid3:CstopOK_3 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid20:n8_20 + -1'tsidxtsid21:n8_21 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid46:n9_46 + tsid2:CstopOK_2 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid116:n7_116 + -1'tsidxtsid120:n7_120 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsid1:n2_1 + tsid1:n1_1 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid113:n9_113 + tsid3:CstopOK_3 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid101:n8_101 + -1'tsidxtsid109:n8_109 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid95:n8_95 + -1'tsidxtsid98:n8_98 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid23:n7_23 + -1'tsidxtsid32:n7_32 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid107:n7_107 + -1'tsidxtsid109:n7_109 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid113:n7_113 + -1'tsidxtsid120:n7_120 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid35:n8_35 + -1'tsidxtsid43:n8_43 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid40:n8_40 + -1'tsidxtsid43:n8_43 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid93:n9_93 + tsid5:CstopOK_5 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid115:n8_115 + -1'tsidxtsid120:n8_120 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid71:n9_71 + tsid5:CstopOK_5 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid93:n8_93 + -1'tsidxtsid98:n8_98 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid88:n8_88 + -1'tsidxtsid98:n8_98 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid29:n7_29 + -1'tsidxtsid32:n7_32 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid9:n8_9 + -1'tsidxtsid10:n8_10 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid31:n9_31 + -1'tsid2:SstopOK_2 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid46:n8_46 + -1'tsidxtsid54:n8_54 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid30:n9_30 + -1'tsid2:SstopOK_2 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid78:n7_78 + -1'tsidxtsid87:n7_87 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid89:n7_89 + -1'tsidxtsid98:n7_98 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid106:n8_106 + -1'tsidxtsid109:n8_109 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsid5:n2_5 + tsid5:n1_5 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid49:n8_49 + -1'tsidxtsid54:n8_54 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid92:n7_92 + -1'tsidxtsid98:n7_98 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid11:n7_11 + -1'tsidxtsid21:n7_21 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid26:n7_26 + -1'tsidxtsid32:n7_32 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid12:n7_12 + -1'tsidxtsid21:n7_21 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsid4:n2_4 + tsid4:n1_4 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid69:n9_69 + tsid3:CstopOK_3 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid34:n7_34 + -1'tsidxtsid43:n7_43 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid73:n7_73 + -1'tsidxtsid76:n7_76 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid99:n9_99 + tsid0:CstopOK_0 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid58:n8_58 + -1'tsidxtsid65:n8_65 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid68:n9_68 + tsid2:CstopOK_2 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid14:n9_14 + -1'tsid1:SstopOK_1 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid44:n9_44 + tsid0:CstopOK_0 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid57:n7_57 + -1'tsidxtsid65:n7_65 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid34:n9_34 + tsid1:CstopOK_1 + -1'tsid3:SstopOK_3 = 0
invariant :malicious_reservoir:malicious_reservoir_0 + -1'tsid0:c1_0 + -1'tsid0:Cstart_0 + -1'tsid0:Sstart_0 + -1'tsid0:s2_0 + -1'tsid0:s3_0 + -1'tsid0:s4_0 + -1'tsid0:s5_0 + -1'tsid0:s6_0 + -1'tsid0:SstopOK_0 + -1'tsid0:CstopOK_0 + -1'tsid1:c1_1 + -1'tsid1:Cstart_1 + -1'tsid1:Sstart_1 + -1'tsid1:s2_1 + -1'tsid1:s3_1 + -1'tsid1:s4_1 + -1'tsid1:s5_1 + -1'tsid1:s6_1 + -1'tsid1:SstopOK_1 + -1'tsid1:CstopOK_1 + -1'tsid2:c1_2 + -1'tsid2:Cstart_2 + -1'tsid2:Sstart_2 + -1'tsid2:s2_2 + -1'tsid2:s3_2 + -1'tsid2:s4_2 + -1'tsid2:s5_2 + -1'tsid2:s6_2 + -1'tsid2:SstopOK_2 + -1'tsid2:CstopOK_2 + -1'tsid3:c1_3 + -1'tsid3:Cstart_3 + -1'tsid3:Sstart_3 + -1'tsid3:s2_3 + -1'tsid3:s3_3 + -1'tsid3:s4_3 + -1'tsid3:s5_3 + -1'tsid3:s6_3 + -1'tsid3:SstopOK_3 + -1'tsid3:CstopOK_3 + -1'tsid4:c1_4 + -1'tsid4:Cstart_4 + -1'tsid4:Sstart_4 + -1'tsid4:s2_4 + -1'tsid4:s3_4 + -1'tsid4:s4_4 + -1'tsid4:s5_4 + -1'tsid4:s6_4 + -1'tsid4:SstopOK_4 + -1'tsid4:CstopOK_4 + -1'tsid5:c1_5 + -1'tsid5:Cstart_5 + -1'tsid5:Sstart_5 + -1'tsid5:s2_5 + -1'tsid5:s3_5 + -1'tsid5:s4_5 + -1'tsid5:s5_5 + -1'tsid5:s6_5 + -1'tsid5:SstopOK_5 + -1'tsid5:CstopOK_5 + -1'tsid6:c1_6 + -1'tsid6:Cstart_6 + -1'tsid6:Sstart_6 + -1'tsid6:s2_6 + -1'tsid6:s3_6 + -1'tsid6:s4_6 + -1'tsid6:s5_6 + -1'tsid6:s6_6 + -1'tsid6:SstopOK_6 + -1'tsid6:CstopOK_6 + -1'tsid7:c1_7 + -1'tsid7:Cstart_7 + -1'tsid7:Sstart_7 + -1'tsid7:s2_7 + -1'tsid7:s3_7 + -1'tsid7:s4_7 + -1'tsid7:s5_7 + -1'tsid7:s6_7 + -1'tsid7:SstopOK_7 + -1'tsid7:CstopOK_7 + -1'tsid8:c1_8 + -1'tsid8:Cstart_8 + -1'tsid8:Sstart_8 + -1'tsid8:s2_8 + -1'tsid8:s3_8 + -1'tsid8:s4_8 + -1'tsid8:s5_8 + -1'tsid8:s6_8 + -1'tsid8:SstopOK_8 + -1'tsid8:CstopOK_8 + -1'tsid9:c1_9 + -1'tsid9:Cstart_9 + -1'tsid9:Sstart_9 + -1'tsid9:s2_9 + -1'tsid9:s3_9 + -1'tsid9:s4_9 + -1'tsid9:s5_9 + -1'tsid9:s6_9 + -1'tsid9:SstopOK_9 + -1'tsid9:CstopOK_9 + -1'tsid10:c1_10 + -1'tsid10:Cstart_10 + -1'tsid10:Sstart_10 + -1'tsid10:s2_10 + -1'tsid10:s3_10 + -1'tsid10:s4_10 + -1'tsid10:s5_10 + -1'tsid10:s6_10 + -1'tsid10:SstopOK_10 + -1'tsid10:CstopOK_10 = -16
invariant :tsidxtsid50:n9_50 + -1'tsid4:SstopOK_4 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid50:n8_50 + -1'tsidxtsid54:n8_54 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid48:n9_48 + -1'tsid4:SstopOK_4 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid5:n9_5 + -1'tsid0:SstopOK_0 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid68:n8_68 + -1'tsidxtsid76:n8_76 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid112:n8_112 + -1'tsidxtsid120:n8_120 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid46:n7_46 + -1'tsidxtsid54:n7_54 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid80:n8_80 + -1'tsidxtsid87:n8_87 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsid1:n4_1 + tsid1:n3_1 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid81:n9_81 + tsid4:CstopOK_4 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid119:n9_119 + tsid9:CstopOK_9 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid64:n9_64 + -1'tsid5:SstopOK_5 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid59:n7_59 + -1'tsidxtsid65:n7_65 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid7:n9_7 + -1'tsid0:SstopOK_0 + tsid7:CstopOK_7 = 0
invariant :SstopAbort:SstopAbort_0 + tsid0:Sstart_0 + tsid0:s2_0 + tsid0:s3_0 + tsid0:s4_0 + tsid0:s5_0 + tsid0:s6_0 + tsid0:SstopOK_0 + tsid1:Sstart_1 + tsid1:s2_1 + tsid1:s3_1 + tsid1:s4_1 + tsid1:s5_1 + tsid1:s6_1 + tsid1:SstopOK_1 + tsid2:Sstart_2 + tsid2:s2_2 + tsid2:s3_2 + tsid2:s4_2 + tsid2:s5_2 + tsid2:s6_2 + tsid2:SstopOK_2 + tsid3:Sstart_3 + tsid3:s2_3 + tsid3:s3_3 + tsid3:s4_3 + tsid3:s5_3 + tsid3:s6_3 + tsid3:SstopOK_3 + tsid4:Sstart_4 + tsid4:s2_4 + tsid4:s3_4 + tsid4:s4_4 + tsid4:s5_4 + tsid4:s6_4 + tsid4:SstopOK_4 + tsid5:Sstart_5 + tsid5:s2_5 + tsid5:s3_5 + tsid5:s4_5 + tsid5:s5_5 + tsid5:s6_5 + tsid5:SstopOK_5 + tsid6:Sstart_6 + tsid6:s2_6 + tsid6:s3_6 + tsid6:s4_6 + tsid6:s5_6 + tsid6:s6_6 + tsid6:SstopOK_6 + tsid7:Sstart_7 + tsid7:s2_7 + tsid7:s3_7 + tsid7:s4_7 + tsid7:s5_7 + tsid7:s6_7 + tsid7:SstopOK_7 + tsid8:Sstart_8 + tsid8:s2_8 + tsid8:s3_8 + tsid8:s4_8 + tsid8:s5_8 + tsid8:s6_8 + tsid8:SstopOK_8 + tsid9:Sstart_9 + tsid9:s2_9 + tsid9:s3_9 + tsid9:s4_9 + tsid9:s5_9 + tsid9:s6_9 + tsid9:SstopOK_9 + tsid10:Sstart_10 + tsid10:s2_10 + tsid10:s3_10 + tsid10:s4_10 + tsid10:s5_10 + tsid10:s6_10 + tsid10:SstopOK_10 = 11
invariant :tsidxtsid105:n9_105 + tsid6:CstopOK_6 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid24:n9_24 + -1'tsid2:SstopOK_2 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid111:n9_111 + tsid1:CstopOK_1 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid110:n8_110 + -1'tsidxtsid120:n8_120 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid80:n7_80 + -1'tsidxtsid87:n7_87 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid41:n8_41 + -1'tsidxtsid43:n8_43 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid55:n7_55 + -1'tsidxtsid65:n7_65 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid72:n9_72 + -1'tsid6:SstopOK_6 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid78:n8_78 + -1'tsidxtsid87:n8_87 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid102:n8_102 + -1'tsidxtsid109:n8_109 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid16:n9_16 + -1'tsid1:SstopOK_1 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid15:n8_15 + -1'tsidxtsid21:n8_21 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid66:n8_66 + -1'tsidxtsid76:n8_76 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid47:n7_47 + -1'tsidxtsid54:n7_54 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid66:n9_66 + tsid0:CstopOK_0 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid91:n8_91 + -1'tsidxtsid98:n8_98 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid84:n7_84 + -1'tsidxtsid87:n7_87 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid48:n7_48 + -1'tsidxtsid54:n7_54 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsid0:n6_0 + tsid0:n5_0 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid117:n7_117 + -1'tsidxtsid120:n7_120 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid89:n9_89 + tsid1:CstopOK_1 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid113:n8_113 + -1'tsidxtsid120:n8_120 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid106:n7_106 + -1'tsidxtsid109:n7_109 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid18:n8_18 + -1'tsidxtsid21:n8_21 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid22:n8_22 + -1'tsidxtsid32:n8_32 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid11:n9_11 + tsid0:CstopOK_0 + -1'tsid1:SstopOK_1 = 0
invariant :tsidxtsid42:n9_42 + -1'tsid3:SstopOK_3 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid77:n7_77 + -1'tsidxtsid87:n7_87 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid104:n8_104 + -1'tsidxtsid109:n8_109 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid105:n8_105 + -1'tsidxtsid109:n8_109 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsid2:n4_2 + tsid2:n3_2 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid54:n9_54 + -1'tsid4:SstopOK_4 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid103:n9_103 + tsid4:CstopOK_4 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid64:n7_64 + -1'tsidxtsid65:n7_65 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid118:n8_118 + -1'tsidxtsid120:n8_120 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid28:n7_28 + -1'tsidxtsid32:n7_32 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid112:n7_112 + -1'tsidxtsid120:n7_120 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid37:n9_37 + -1'tsid3:SstopOK_3 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid62:n7_62 + -1'tsidxtsid65:n7_65 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid119:n8_119 + -1'tsidxtsid120:n8_120 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid0:n9_0 + -1'tsid0:SstopOK_0 + tsid0:CstopOK_0 = 0
invariant :tsidxtsid48:n8_48 + -1'tsidxtsid54:n8_54 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid70:n8_70 + -1'tsidxtsid76:n8_76 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid3:n9_3 + -1'tsid0:SstopOK_0 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid94:n8_94 + -1'tsidxtsid98:n8_98 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid18:n9_18 + -1'tsid1:SstopOK_1 + tsid7:CstopOK_7 = 0
invariant :tsidxtsid87:n9_87 + -1'tsid7:SstopOK_7 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid13:n8_13 + -1'tsidxtsid21:n8_21 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid22:n9_22 + tsid0:CstopOK_0 + -1'tsid2:SstopOK_2 = 0
invariant :tsidxtsid99:n7_99 + -1'tsidxtsid109:n7_109 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsid8:n2_8 + tsid8:n1_8 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid30:n8_30 + -1'tsidxtsid32:n8_32 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid35:n7_35 + -1'tsidxtsid43:n7_43 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid36:n7_36 + -1'tsidxtsid43:n7_43 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid74:n8_74 + -1'tsidxtsid76:n8_76 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid39:n7_39 + -1'tsidxtsid43:n7_43 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid13:n7_13 + -1'tsidxtsid21:n7_21 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid23:n8_23 + -1'tsidxtsid32:n8_32 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid19:n7_19 + -1'tsidxtsid21:n7_21 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid67:n7_67 + -1'tsidxtsid76:n7_76 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid88:n9_88 + tsid0:CstopOK_0 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid91:n7_91 + -1'tsidxtsid98:n7_98 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid86:n9_86 + -1'tsid7:SstopOK_7 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid107:n9_107 + tsid8:CstopOK_8 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid28:n8_28 + -1'tsidxtsid32:n8_32 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsid8:n4_8 + tsid8:n3_8 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid55:n9_55 + tsid0:CstopOK_0 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid57:n9_57 + tsid2:CstopOK_2 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid29:n9_29 + -1'tsid2:SstopOK_2 + tsid7:CstopOK_7 = 0
invariant :tsidxtsid36:n9_36 + -1'tsid3:SstopOK_3 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid1:n7_1 + -1'tsidxtsid10:n7_10 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid14:n8_14 + -1'tsidxtsid21:n8_21 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid114:n7_114 + -1'tsidxtsid120:n7_120 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid21:n9_21 + -1'tsid1:SstopOK_1 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid24:n7_24 + -1'tsidxtsid32:n7_32 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsid2:n6_2 + tsid2:n5_2 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid15:n9_15 + -1'tsid1:SstopOK_1 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid81:n7_81 + -1'tsidxtsid87:n7_87 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid2:n7_2 + -1'tsidxtsid10:n7_10 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid114:n9_114 + tsid4:CstopOK_4 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid47:n8_47 + -1'tsidxtsid54:n8_54 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid96:n8_96 + -1'tsidxtsid98:n8_98 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :AstopAbort:AstopAbort_0 + a5:a5_0 + a4:a4_0 + a3:a3_0 + a2:a2_0 + a1:a1_0 + Astart:Astart_0 + AstopOK:AstopOK_0 = 1
invariant :tsidxtsid65:n9_65 + -1'tsid5:SstopOK_5 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid37:n8_37 + -1'tsidxtsid43:n8_43 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid95:n7_95 + -1'tsidxtsid98:n7_98 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid53:n7_53 + -1'tsidxtsid54:n7_54 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid78:n9_78 + tsid1:CstopOK_1 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid38:n7_38 + -1'tsidxtsid43:n7_43 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid35:n9_35 + tsid2:CstopOK_2 + -1'tsid3:SstopOK_3 = 0
invariant :tsidxtsid2:n8_2 + -1'tsidxtsid10:n8_10 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid119:n7_119 + -1'tsidxtsid120:n7_120 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid38:n9_38 + -1'tsid3:SstopOK_3 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid27:n9_27 + -1'tsid2:SstopOK_2 + tsid5:CstopOK_5 = 0
invariant :tsid7:n2_7 + tsid7:n1_7 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid16:n7_16 + -1'tsidxtsid21:n7_21 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid118:n9_118 + tsid8:CstopOK_8 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid57:n8_57 + -1'tsidxtsid65:n8_65 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid88:n7_88 + -1'tsidxtsid98:n7_98 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid15:n7_15 + -1'tsidxtsid21:n7_21 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid40:n7_40 + -1'tsidxtsid43:n7_43 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid79:n9_79 + tsid2:CstopOK_2 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid117:n8_117 + -1'tsidxtsid120:n8_120 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid63:n7_63 + -1'tsidxtsid65:n7_65 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid69:n8_69 + -1'tsidxtsid76:n8_76 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid40:n9_40 + -1'tsid3:SstopOK_3 + tsid7:CstopOK_7 = 0
invariant :tsid3:n6_3 + tsid3:n5_3 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid84:n8_84 + -1'tsidxtsid87:n8_87 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid75:n9_75 + -1'tsid6:SstopOK_6 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid6:n7_6 + -1'tsidxtsid10:n7_10 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid86:n8_86 + -1'tsidxtsid87:n8_87 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid4:n7_4 + -1'tsidxtsid10:n7_10 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid76:n9_76 + -1'tsid6:SstopOK_6 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid61:n7_61 + -1'tsidxtsid65:n7_65 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid70:n9_70 + tsid4:CstopOK_4 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid49:n9_49 + -1'tsid4:SstopOK_4 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid38:n8_38 + -1'tsidxtsid43:n8_43 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid17:n8_17 + -1'tsidxtsid21:n8_21 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid61:n9_61 + -1'tsid5:SstopOK_5 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid62:n8_62 + -1'tsidxtsid65:n8_65 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid51:n7_51 + -1'tsidxtsid54:n7_54 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid73:n9_73 + -1'tsid6:SstopOK_6 + tsid7:CstopOK_7 = 0
invariant :tsid7:n4_7 + tsid7:n3_7 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :CstopAbort:CstopAbort_0 + tsid0:c1_0 + tsid0:Cstart_0 + tsid0:CstopOK_0 + tsid1:c1_1 + tsid1:Cstart_1 + tsid1:CstopOK_1 + tsid2:c1_2 + tsid2:Cstart_2 + tsid2:CstopOK_2 + tsid3:c1_3 + tsid3:Cstart_3 + tsid3:CstopOK_3 + tsid4:c1_4 + tsid4:Cstart_4 + tsid4:CstopOK_4 + tsid5:c1_5 + tsid5:Cstart_5 + tsid5:CstopOK_5 + tsid6:c1_6 + tsid6:Cstart_6 + tsid6:CstopOK_6 + tsid7:c1_7 + tsid7:Cstart_7 + tsid7:CstopOK_7 + tsid8:c1_8 + tsid8:Cstart_8 + tsid8:CstopOK_8 + tsid9:c1_9 + tsid9:Cstart_9 + tsid9:CstopOK_9 + tsid10:c1_10 + tsid10:Cstart_10 + tsid10:CstopOK_10 = 11
invariant :tsidxtsid91:n9_91 + tsid3:CstopOK_3 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid103:n7_103 + -1'tsidxtsid109:n7_109 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid22:n7_22 + -1'tsidxtsid32:n7_32 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid82:n9_82 + tsid5:CstopOK_5 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid33:n8_33 + -1'tsidxtsid43:n8_43 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid25:n8_25 + -1'tsidxtsid32:n8_32 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid47:n9_47 + tsid3:CstopOK_3 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid10:n9_10 + -1'tsid0:SstopOK_0 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid51:n8_51 + -1'tsidxtsid54:n8_54 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid60:n7_60 + -1'tsidxtsid65:n7_65 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid104:n7_104 + -1'tsidxtsid109:n7_109 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid95:n9_95 + tsid7:CstopOK_7 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid86:n7_86 + -1'tsidxtsid87:n7_87 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid116:n8_116 + -1'tsidxtsid120:n8_120 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsid0:n2_0 + tsid0:n1_0 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid102:n9_102 + tsid3:CstopOK_3 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid79:n7_79 + -1'tsidxtsid87:n7_87 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid58:n7_58 + -1'tsidxtsid65:n7_65 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid115:n9_115 + tsid5:CstopOK_5 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid32:n9_32 + -1'tsid2:SstopOK_2 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid118:n7_118 + -1'tsidxtsid120:n7_120 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid102:n7_102 + -1'tsidxtsid109:n7_109 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid3:n8_3 + -1'tsidxtsid10:n8_10 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid55:n8_55 + -1'tsidxtsid65:n8_65 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsid0:n4_0 + tsid0:n3_0 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid45:n7_45 + -1'tsidxtsid54:n7_54 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid53:n9_53 + -1'tsid4:SstopOK_4 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid97:n8_97 + -1'tsidxtsid98:n8_98 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid108:n9_108 + -1'tsid9:SstopOK_9 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid3:n7_3 + -1'tsidxtsid10:n7_10 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid103:n8_103 + -1'tsidxtsid109:n8_109 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid110:n9_110 + tsid0:CstopOK_0 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid105:n7_105 + -1'tsidxtsid109:n7_109 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid115:n7_115 + -1'tsidxtsid120:n7_120 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid8:n7_8 + -1'tsidxtsid10:n7_10 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid27:n8_27 + -1'tsidxtsid32:n8_32 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid63:n8_63 + -1'tsidxtsid65:n8_65 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid2:n9_2 + -1'tsid0:SstopOK_0 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid116:n9_116 + tsid6:CstopOK_6 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid5:n7_5 + -1'tsidxtsid10:n7_10 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid96:n7_96 + -1'tsidxtsid98:n7_98 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid56:n7_56 + -1'tsidxtsid65:n7_65 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid71:n8_71 + -1'tsidxtsid76:n8_76 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid83:n9_83 + tsid6:CstopOK_6 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid37:n7_37 + -1'tsidxtsid43:n7_43 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid68:n7_68 + -1'tsidxtsid76:n7_76 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid67:n9_67 + tsid1:CstopOK_1 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid44:n7_44 + -1'tsidxtsid54:n7_54 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid97:n7_97 + -1'tsidxtsid98:n7_98 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid107:n8_107 + -1'tsidxtsid109:n8_109 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid0:n8_0 + -1'tsidxtsid10:n8_10 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsid2:n2_2 + tsid2:n1_2 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid100:n7_100 + -1'tsidxtsid109:n7_109 + -1'tsid1:Cstart_1 + tsid10:Cstart_10 = 0
invariant :tsidxtsid101:n7_101 + -1'tsidxtsid109:n7_109 + -1'tsid2:Cstart_2 + tsid10:Cstart_10 = 0
invariant :tsidxtsid6:n8_6 + -1'tsidxtsid10:n8_10 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid56:n8_56 + -1'tsidxtsid65:n8_65 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid5:n8_5 + -1'tsidxtsid10:n8_10 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid19:n9_19 + -1'tsid1:SstopOK_1 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid75:n8_75 + -1'tsidxtsid76:n8_76 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid12:n9_12 + -1'tsid1:SstopOK_1 + tsid1:CstopOK_1 = 0
invariant :tsidxtsid89:n8_89 + -1'tsidxtsid98:n8_98 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid31:n8_31 + -1'tsidxtsid32:n8_32 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid9:n9_9 + -1'tsid0:SstopOK_0 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid27:n7_27 + -1'tsidxtsid32:n7_32 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid23:n9_23 + tsid1:CstopOK_1 + -1'tsid2:SstopOK_2 = 0
invariant :tsidxtsid25:n9_25 + -1'tsid2:SstopOK_2 + tsid3:CstopOK_3 = 0
invariant :tsid7:n6_7 + tsid7:n5_7 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid72:n8_72 + -1'tsidxtsid76:n8_76 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid110:n7_110 + -1'tsidxtsid120:n7_120 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid6:n9_6 + -1'tsid0:SstopOK_0 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid13:n9_13 + -1'tsid1:SstopOK_1 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid96:n9_96 + -1'tsid8:SstopOK_8 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid52:n9_52 + -1'tsid4:SstopOK_4 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid82:n8_82 + -1'tsidxtsid87:n8_87 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid9:n7_9 + -1'tsidxtsid10:n7_10 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid16:n8_16 + -1'tsidxtsid21:n8_21 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid39:n9_39 + -1'tsid3:SstopOK_3 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid26:n8_26 + -1'tsidxtsid32:n8_32 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsid4:n4_4 + tsid4:n3_4 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid85:n9_85 + -1'tsid7:SstopOK_7 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid94:n9_94 + tsid6:CstopOK_6 + -1'tsid8:SstopOK_8 = 0
invariant :tsid6:n2_6 + tsid6:n1_6 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid81:n8_81 + -1'tsidxtsid87:n8_87 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid42:n7_42 + -1'tsidxtsid43:n7_43 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsidxtsid85:n7_85 + -1'tsidxtsid87:n7_87 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid72:n7_72 + -1'tsidxtsid76:n7_76 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid77:n8_77 + -1'tsidxtsid87:n8_87 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid83:n7_83 + -1'tsidxtsid87:n7_87 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid30:n7_30 + -1'tsidxtsid32:n7_32 + -1'tsid8:Cstart_8 + tsid10:Cstart_10 = 0
invariant :tsidxtsid4:n9_4 + -1'tsid0:SstopOK_0 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid109:n9_109 + -1'tsid9:SstopOK_9 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid50:n7_50 + -1'tsidxtsid54:n7_54 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid77:n9_77 + tsid0:CstopOK_0 + -1'tsid7:SstopOK_7 = 0
invariant :tsidxtsid8:n9_8 + -1'tsid0:SstopOK_0 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid45:n8_45 + -1'tsidxtsid54:n8_54 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsid3:n2_3 + tsid3:n1_3 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid98:n9_98 + -1'tsid8:SstopOK_8 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid56:n9_56 + tsid1:CstopOK_1 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid4:n8_4 + -1'tsidxtsid10:n8_10 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid117:n9_117 + tsid7:CstopOK_7 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid62:n9_62 + -1'tsid5:SstopOK_5 + tsid7:CstopOK_7 = 0
invariant :tsidxtsid84:n9_84 + -1'tsid7:SstopOK_7 + tsid7:CstopOK_7 = 0
invariant :tsidxtsid99:n8_99 + -1'tsidxtsid109:n8_109 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid60:n9_60 + -1'tsid5:SstopOK_5 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid67:n8_67 + -1'tsidxtsid76:n8_76 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid106:n9_106 + tsid7:CstopOK_7 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid0:n7_0 + -1'tsidxtsid10:n7_10 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid93:n7_93 + -1'tsidxtsid98:n7_98 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid14:n7_14 + -1'tsidxtsid21:n7_21 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsidxtsid70:n7_70 + -1'tsidxtsid76:n7_76 + -1'tsid4:Cstart_4 + tsid10:Cstart_10 = 0
invariant :tsidxtsid49:n7_49 + -1'tsidxtsid54:n7_54 + -1'tsid5:Cstart_5 + tsid10:Cstart_10 = 0
invariant :tsidxtsid52:n8_52 + -1'tsidxtsid54:n8_54 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid100:n9_100 + tsid1:CstopOK_1 + -1'tsid9:SstopOK_9 = 0
invariant :tsid5:n4_5 + tsid5:n3_5 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsid1:n6_1 + tsid1:n5_1 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid90:n8_90 + -1'tsidxtsid98:n8_98 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid1:n9_1 + -1'tsid0:SstopOK_0 + tsid1:CstopOK_1 = 0
invariant :tsidxtsid108:n8_108 + -1'tsidxtsid109:n8_109 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsid9:n4_9 + tsid9:n3_9 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid59:n9_59 + tsid4:CstopOK_4 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid1:n8_1 + -1'tsidxtsid10:n8_10 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid59:n8_59 + -1'tsidxtsid65:n8_65 + tsid4:Cstart_4 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid73:n8_73 + -1'tsidxtsid76:n8_76 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid85:n8_85 + -1'tsidxtsid87:n8_87 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid25:n7_25 + -1'tsidxtsid32:n7_32 + -1'tsid3:Cstart_3 + tsid10:Cstart_10 = 0
invariant :tsid9:n6_9 + tsid9:n5_9 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid60:n8_60 + -1'tsidxtsid65:n8_65 + tsid5:Cstart_5 + -1'tsid10:Cstart_10 = 0
invariant :tsid6:n6_6 + tsid6:n5_6 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid11:n8_11 + -1'tsidxtsid21:n8_21 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid44:n8_44 + -1'tsidxtsid54:n8_54 + tsid0:Cstart_0 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid24:n8_24 + -1'tsidxtsid32:n8_32 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid36:n8_36 + -1'tsidxtsid43:n8_43 + tsid3:Cstart_3 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid66:n7_66 + -1'tsidxtsid76:n7_76 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid101:n9_101 + tsid2:CstopOK_2 + -1'tsid9:SstopOK_9 = 0
invariant :tsidxtsid31:n7_31 + -1'tsidxtsid32:n7_32 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsid3:n4_3 + tsid3:n3_3 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid90:n9_90 + tsid2:CstopOK_2 + -1'tsid8:SstopOK_8 = 0
invariant :tsidxtsid94:n7_94 + -1'tsidxtsid98:n7_98 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsidxtsid29:n8_29 + -1'tsidxtsid32:n8_32 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid19:n8_19 + -1'tsidxtsid21:n8_21 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid28:n9_28 + -1'tsid2:SstopOK_2 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid100:n8_100 + -1'tsidxtsid109:n8_109 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid112:n9_112 + tsid2:CstopOK_2 + -1'tsid10:SstopOK_10 = 0
invariant :tsidxtsid75:n7_75 + -1'tsidxtsid76:n7_76 + -1'tsid9:Cstart_9 + tsid10:Cstart_10 = 0
invariant :tsid5:n6_5 + tsid5:n5_5 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid58:n9_58 + tsid3:CstopOK_3 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid42:n8_42 + -1'tsidxtsid43:n8_43 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid61:n8_61 + -1'tsidxtsid65:n8_65 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid120:n9_120 + -1'tsid10:SstopOK_10 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid18:n7_18 + -1'tsidxtsid21:n7_21 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsidxtsid8:n8_8 + -1'tsidxtsid10:n8_10 + tsid8:Cstart_8 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid34:n8_34 + -1'tsidxtsid43:n8_43 + tsid1:Cstart_1 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid53:n8_53 + -1'tsidxtsid54:n8_54 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid7:n8_7 + -1'tsidxtsid10:n8_10 + tsid7:Cstart_7 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid97:n9_97 + -1'tsid8:SstopOK_8 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid17:n7_17 + -1'tsidxtsid21:n7_21 + -1'tsid6:Cstart_6 + tsid10:Cstart_10 = 0
invariant :tsid6:n4_6 + tsid6:n3_6 + -1'tsid10:n4_10 + -1'tsid10:n3_10 = 0
invariant :tsidxtsid63:n9_63 + -1'tsid5:SstopOK_5 + tsid8:CstopOK_8 = 0
invariant :tsidxtsid20:n9_20 + -1'tsid1:SstopOK_1 + tsid9:CstopOK_9 = 0
invariant :tsidxtsid33:n7_33 + -1'tsidxtsid43:n7_43 + -1'tsid0:Cstart_0 + tsid10:Cstart_10 = 0
invariant :tsidxtsid79:n8_79 + -1'tsidxtsid87:n8_87 + tsid2:Cstart_2 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid43:n9_43 + -1'tsid3:SstopOK_3 + tsid10:CstopOK_10 = 0
invariant :tsidxtsid64:n8_64 + -1'tsidxtsid65:n8_65 + tsid9:Cstart_9 + -1'tsid10:Cstart_10 = 0
invariant :tsidxtsid7:n7_7 + -1'tsidxtsid10:n7_10 + -1'tsid7:Cstart_7 + tsid10:Cstart_10 = 0
invariant :tsid4:n6_4 + tsid4:n5_4 + -1'tsid10:n6_10 + -1'tsid10:n5_10 = 0
invariant :tsidxtsid39:n8_39 + -1'tsidxtsid43:n8_43 + tsid6:Cstart_6 + -1'tsid10:Cstart_10 = 0
invariant :tsid9:n2_9 + tsid9:n1_9 + -1'tsid10:n2_10 + -1'tsid10:n1_10 = 0
invariant :tsidxtsid26:n9_26 + -1'tsid2:SstopOK_2 + tsid4:CstopOK_4 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12683 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 141 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 468 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 465 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((<>((LTLAP2==true)))U([]((LTLAP3==true))))U((LTLAP4==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 458 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP2==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 133 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](((LTLAP3==true))U(<>((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 455 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP6==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 444 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP3==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 429 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 116 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([]([]((LTLAP8==true))))U([](((LTLAP9==true))U((LTLAP10==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 481 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([]((<>((LTLAP1==true)))U(<>((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 438 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X(((LTLAP11==true))U((LTLAP12==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 134 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]((LTLAP0==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 91 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 439 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP10==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 118 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP1==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 476 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP14==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 444 ms.
FORMULA QuasiCertifProtocol-COL-10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.
BK_STOP 1528281419393
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 06, 2018 10:31:29 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 06, 2018 10:31:29 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 06, 2018 10:31:29 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 21946 ms
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 30 places.
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :tsidxtsid->n9,n8,n7,
Dot->malicious_reservoir,CstopAbort,SstopAbort,AstopAbort,a5,a4,a3,a2,a1,Astart,AstopOK,
tsid->n6,n5,n4,n3,n2,n1,c1,Cstart,Sstart,s2,s3,s4,s5,s6,SstopOK,CstopOK,
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 26 transitions.
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Jun 06, 2018 10:31:51 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 52 ms
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 06, 2018 10:31:51 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 06, 2018 10:31:52 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 343 ms
Jun 06, 2018 10:31:53 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays n9, n8, n7, n6, n5, n4, n3, n2, n1, c1, Cstart, Sstart, s2, s3, s4, s5, s6, SstopOK, CstopOK to variables to allow decomposition.
Jun 06, 2018 10:31:54 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 20 redundant transitions.
Jun 06, 2018 10:31:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 36 ms
Jun 06, 2018 10:31:55 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 7 ms
Jun 06, 2018 10:31:56 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 106 transitions. Expanding to a total of 183 deterministic transitions.
Jun 06, 2018 10:31:56 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 31 ms.
Jun 06, 2018 10:31:57 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 375 place invariants in 231 ms
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 550 variables to be positive in 3079 ms
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 176 transitions.
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/176 took 5 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 35 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 176 transitions.
Jun 06, 2018 10:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 19 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:32:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 176 transitions.
Jun 06, 2018 10:32:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/176) took 5413 ms. Total solver calls (SAT/UNSAT): 164(164/0)
Jun 06, 2018 10:32:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/176) took 8605 ms. Total solver calls (SAT/UNSAT): 650(650/0)
Jun 06, 2018 10:32:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/176) took 11878 ms. Total solver calls (SAT/UNSAT): 969(969/0)
Jun 06, 2018 10:32:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/176) took 18689 ms. Total solver calls (SAT/UNSAT): 1284(1284/0)
Jun 06, 2018 10:32:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/176) took 24518 ms. Total solver calls (SAT/UNSAT): 1440(1440/0)
Jun 06, 2018 10:32:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/176) took 27672 ms. Total solver calls (SAT/UNSAT): 1595(1595/0)
Jun 06, 2018 10:32:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/176) took 34893 ms. Total solver calls (SAT/UNSAT): 1749(1749/0)
Jun 06, 2018 10:32:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/176) took 47423 ms. Total solver calls (SAT/UNSAT): 1902(1902/0)
Jun 06, 2018 10:33:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/176) took 55735 ms. Total solver calls (SAT/UNSAT): 2054(2054/0)
Jun 06, 2018 10:33:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/176) took 68670 ms. Total solver calls (SAT/UNSAT): 2205(2205/0)
Jun 06, 2018 10:33:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/176) took 76031 ms. Total solver calls (SAT/UNSAT): 2355(2355/0)
Jun 06, 2018 10:33:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/176) took 82802 ms. Total solver calls (SAT/UNSAT): 2504(2504/0)
Jun 06, 2018 10:33:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(16/176) took 96869 ms. Total solver calls (SAT/UNSAT): 2652(2652/0)
Jun 06, 2018 10:33:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/176) took 106157 ms. Total solver calls (SAT/UNSAT): 2799(2799/0)
Jun 06, 2018 10:34:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/176) took 122285 ms. Total solver calls (SAT/UNSAT): 2945(2945/0)
Jun 06, 2018 10:34:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/176) took 131075 ms. Total solver calls (SAT/UNSAT): 3090(3090/0)
Jun 06, 2018 10:34:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/176) took 139108 ms. Total solver calls (SAT/UNSAT): 3234(3234/0)
Jun 06, 2018 10:34:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/176) took 147322 ms. Total solver calls (SAT/UNSAT): 3377(3377/0)
Jun 06, 2018 10:34:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/176) took 154177 ms. Total solver calls (SAT/UNSAT): 3519(3519/0)
Jun 06, 2018 10:34:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/176) took 162930 ms. Total solver calls (SAT/UNSAT): 3660(3660/0)
Jun 06, 2018 10:35:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/176) took 171054 ms. Total solver calls (SAT/UNSAT): 3800(3800/0)
Jun 06, 2018 10:35:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/176) took 180128 ms. Total solver calls (SAT/UNSAT): 3939(3939/0)
Jun 06, 2018 10:35:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/176) took 189141 ms. Total solver calls (SAT/UNSAT): 4077(4077/0)
Jun 06, 2018 10:35:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(27/176) took 195348 ms. Total solver calls (SAT/UNSAT): 4214(4214/0)
Jun 06, 2018 10:35:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/176) took 202186 ms. Total solver calls (SAT/UNSAT): 4350(4350/0)
Jun 06, 2018 10:35:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/176) took 209312 ms. Total solver calls (SAT/UNSAT): 4485(4485/0)
Jun 06, 2018 10:35:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/176) took 219565 ms. Total solver calls (SAT/UNSAT): 4619(4619/0)
Jun 06, 2018 10:35:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(31/176) took 226074 ms. Total solver calls (SAT/UNSAT): 4752(4752/0)
Jun 06, 2018 10:36:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/176) took 233631 ms. Total solver calls (SAT/UNSAT): 4884(4884/0)
Jun 06, 2018 10:36:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/176) took 243560 ms. Total solver calls (SAT/UNSAT): 5015(5015/0)
Jun 06, 2018 10:36:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/176) took 252043 ms. Total solver calls (SAT/UNSAT): 5145(5145/0)
Jun 06, 2018 10:36:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/176) took 263013 ms. Total solver calls (SAT/UNSAT): 5274(5274/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Jun 06, 2018 10:36:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(36/176) took 268557 ms. Total solver calls (SAT/UNSAT): 5305(5305/0)
Jun 06, 2018 10:36:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 268560 ms. Total solver calls (SAT/UNSAT): 5305(5305/0)
Jun 06, 2018 10:36:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 176 transitions.
Jun 06, 2018 10:36:38 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 06, 2018 10:36:39 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 283040ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-10.tgz
mv QuasiCertifProtocol-COL-10 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is QuasiCertifProtocol-COL-10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r188-qhx2-152732140200046"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;