Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 608K
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 51K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.6K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 37K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 24K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 8.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 7 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 167K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is SharedMemory-PT-000010, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r177-smll-152708747500110
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-00
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-01
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-02
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-03
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-04
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-05
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-06
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-07
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-08
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-09
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-10
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-11
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-12
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-13
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-14
FORMULA_NAME SharedMemory-PT-000010-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527429810625

FORMULA SharedMemory-PT-000010-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-00 with value :((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)<=(((((((((OwnMemAcc_4+OwnMemAcc_3)+OwnMemAcc_2)+OwnMemAcc_1)+OwnMemAcc_6)+OwnMemAcc_5)+OwnMemAcc_8)+OwnMemAcc_7)+OwnMemAcc_10)+OwnMemAcc_9))
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-01 with value :(((((((((((OwnMemAcc_4+OwnMemAcc_3)+OwnMemAcc_2)+OwnMemAcc_1)+OwnMemAcc_6)+OwnMemAcc_5)+OwnMemAcc_8)+OwnMemAcc_7)+OwnMemAcc_10)+OwnMemAcc_9)>=3)&&((!((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_6_1)+Ext_Mem_Acc_7_1)+Ext_Mem_Acc_8_1)+Ext_Mem_Acc_9_1)+Ext_Mem_Acc_10_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_7_2)+Ext_Mem_Acc_6_2)+Ext_Mem_Acc_9_2)+Ext_Mem_Acc_8_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_10_2)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_6_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_8_3)+Ext_Mem_Acc_7_3)+Ext_Mem_Acc_10_3)+Ext_Mem_Acc_9_3)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_6_4)+Ext_Mem_Acc_7_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_10_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_8_4)+Ext_Mem_Acc_9_4)+Ext_Mem_Acc_4_5)+Ext_Mem_Acc_6_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_9_5)+Ext_Mem_Acc_10_5)+Ext_Mem_Acc_7_5)+Ext_Mem_Acc_8_5)+Ext_Mem_Acc_4_6)+Ext_Mem_Acc_3_6)+Ext_Mem_Acc_2_6)+Ext_Mem_Acc_1_6)+Ext_Mem_Acc_9_6)+Ext_Mem_Acc_8_6)+Ext_Mem_Acc_7_6)+Ext_Mem_Acc_5_6)+Ext_Mem_Acc_3_7)+Ext_Mem_Acc_2_7)+Ext_Mem_Acc_1_7)+Ext_Mem_Acc_10_6)+Ext_Mem_Acc_8_7)+Ext_Mem_Acc_6_7)+Ext_Mem_Acc_5_7)+Ext_Mem_Acc_4_7)+Ext_Mem_Acc_3_8)+Ext_Mem_Acc_4_8)+Ext_Mem_Acc_5_8)+Ext_Mem_Acc_6_8)+Ext_Mem_Acc_9_7)+Ext_Mem_Acc_10_7)+Ext_Mem_Acc_1_8)+Ext_Mem_Acc_2_8)+Ext_Mem_Acc_2_9)+Ext_Mem_Acc_3_9)+Ext_Mem_Acc_4_9)+Ext_Mem_Acc_5_9)+Ext_Mem_Acc_7_8)+Ext_Mem_Acc_9_8)+Ext_Mem_Acc_10_8)+Ext_Mem_Acc_1_9)+Ext_Mem_Acc_2_10)+Ext_Mem_Acc_1_10)+Ext_Mem_Acc_4_10)+Ext_Mem_Acc_3_10)+Ext_Mem_Acc_7_9)+Ext_Mem_Acc_6_9)+Ext_Mem_Acc_10_9)+Ext_Mem_Acc_8_9)+Ext_Mem_Acc_9_10)+Ext_Mem_Acc_6_10)+Ext_Mem_Acc_5_10)+Ext_Mem_Acc_8_10)+Ext_Mem_Acc_7_10)>=2))&&(((((((((((OwnMemAcc_4+OwnMemAcc_3)+OwnMemAcc_2)+OwnMemAcc_1)+OwnMemAcc_6)+OwnMemAcc_5)+OwnMemAcc_8)+OwnMemAcc_7)+OwnMemAcc_10)+OwnMemAcc_9)>=3)&&(Ext_Bus<=(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_6_1)+Ext_Mem_Acc_7_1)+Ext_Mem_Acc_8_1)+Ext_Mem_Acc_9_1)+Ext_Mem_Acc_10_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_7_2)+Ext_Mem_Acc_6_2)+Ext_Mem_Acc_9_2)+Ext_Mem_Acc_8_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_10_2)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_6_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_8_3)+Ext_Mem_Acc_7_3)+Ext_Mem_Acc_10_3)+Ext_Mem_Acc_9_3)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_6_4)+Ext_Mem_Acc_7_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_10_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_8_4)+Ext_Mem_Acc_9_4)+Ext_Mem_Acc_4_5)+Ext_Mem_Acc_6_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_9_5)+Ext_Mem_Acc_10_5)+Ext_Mem_Acc_7_5)+Ext_Mem_Acc_8_5)+Ext_Mem_Acc_4_6)+Ext_Mem_Acc_3_6)+Ext_Mem_Acc_2_6)+Ext_Mem_Acc_1_6)+Ext_Mem_Acc_9_6)+Ext_Mem_Acc_8_6)+Ext_Mem_Acc_7_6)+Ext_Mem_Acc_5_6)+Ext_Mem_Acc_3_7)+Ext_Mem_Acc_2_7)+Ext_Mem_Acc_1_7)+Ext_Mem_Acc_10_6)+Ext_Mem_Acc_8_7)+Ext_Mem_Acc_6_7)+Ext_Mem_Acc_5_7)+Ext_Mem_Acc_4_7)+Ext_Mem_Acc_3_8)+Ext_Mem_Acc_4_8)+Ext_Mem_Acc_5_8)+Ext_Mem_Acc_6_8)+Ext_Mem_Acc_9_7)+Ext_Mem_Acc_10_7)+Ext_Mem_Acc_1_8)+Ext_Mem_Acc_2_8)+Ext_Mem_Acc_2_9)+Ext_Mem_Acc_3_9)+Ext_Mem_Acc_4_9)+Ext_Mem_Acc_5_9)+Ext_Mem_Acc_7_8)+Ext_Mem_Acc_9_8)+Ext_Mem_Acc_10_8)+Ext_Mem_Acc_1_9)+Ext_Mem_Acc_2_10)+Ext_Mem_Acc_1_10)+Ext_Mem_Acc_4_10)+Ext_Mem_Acc_3_10)+Ext_Mem_Acc_7_9)+Ext_Mem_Acc_6_9)+Ext_Mem_Acc_10_9)+Ext_Mem_Acc_8_9)+Ext_Mem_Acc_9_10)+Ext_Mem_Acc_6_10)+Ext_Mem_Acc_5_10)+Ext_Mem_Acc_8_10)+Ext_Mem_Acc_7_10)))))
Read [invariant] property : SharedMemory-PT-000010-ReachabilityCardinality-02 with value :((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)>=2)
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-03 with value :(!((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)>=2))
Read [invariant] property : SharedMemory-PT-000010-ReachabilityCardinality-05 with value :((((((((((Memory_2+Memory_1)+Memory_9)+Memory_10)+Memory_7)+Memory_8)+Memory_5)+Memory_6)+Memory_3)+Memory_4)>=3)
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-06 with value :((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)<=Ext_Bus)
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-07 with value :((((((((((((OwnMemAcc_4+OwnMemAcc_3)+OwnMemAcc_2)+OwnMemAcc_1)+OwnMemAcc_6)+OwnMemAcc_5)+OwnMemAcc_8)+OwnMemAcc_7)+OwnMemAcc_10)+OwnMemAcc_9)>=1)&&((((((((((Queue_6+Queue_5)+Queue_4)+Queue_3)+Queue_2)+Queue_1)+Queue_10)+Queue_9)+Queue_8)+Queue_7)>=3))&&((((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)<=(((((((((Queue_6+Queue_5)+Queue_4)+Queue_3)+Queue_2)+Queue_1)+Queue_10)+Queue_9)+Queue_8)+Queue_7))||(Ext_Bus<=(((((((((OwnMemAcc_4+OwnMemAcc_3)+OwnMemAcc_2)+OwnMemAcc_1)+OwnMemAcc_6)+OwnMemAcc_5)+OwnMemAcc_8)+OwnMemAcc_7)+OwnMemAcc_10)+OwnMemAcc_9)))||((((((((((Active_7+Active_8)+Active_5)+Active_6)+Active_3)+Active_4)+Active_1)+Active_2)+Active_10)+Active_9)>=2)))
Read [invariant] property : SharedMemory-PT-000010-ReachabilityCardinality-08 with value :(((!(Ext_Mem_Acc_9_7>=1))&&((Ext_Mem_Acc_4_10>=1)&&(Ext_Mem_Acc_2_9<=Ext_Mem_Acc_4_3)))||((!(OwnMemAcc_6>=1))||((Ext_Mem_Acc_4_3<=Ext_Mem_Acc_7_5)||(Ext_Mem_Acc_10_1>=1))))
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-09 with value :((((Ext_Mem_Acc_9_3<=Ext_Mem_Acc_8_4)||(Ext_Mem_Acc_3_1<=Ext_Mem_Acc_2_1))&&((Memory_9>=3)&&(Queue_8<=Queue_1)))||(!((Ext_Mem_Acc_4_9<=Ext_Mem_Acc_10_4)||(Ext_Mem_Acc_4_7<=Ext_Mem_Acc_1_2))))
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-10 with value :(Ext_Mem_Acc_7_1>=3)
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-11 with value :(((Ext_Mem_Acc_8_10>=2)&&(Ext_Mem_Acc_6_5<=Ext_Mem_Acc_5_9))||(!((Ext_Mem_Acc_8_6<=OwnMemAcc_3)||(Ext_Mem_Acc_10_6<=Queue_8))))
Read [invariant] property : SharedMemory-PT-000010-ReachabilityCardinality-12 with value :(!(OwnMemAcc_8>=3))
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-13 with value :((((Ext_Mem_Acc_8_7<=Active_1)||(OwnMemAcc_7<=Ext_Mem_Acc_7_8))||(Ext_Mem_Acc_4_10>=1))&&(((Ext_Mem_Acc_7_10<=Ext_Mem_Acc_7_1)||(Active_5>=2))&&((Ext_Mem_Acc_10_5<=Memory_4)&&(Queue_9>=2))))
Read [reachable] property : SharedMemory-PT-000010-ReachabilityCardinality-14 with value :(OwnMemAcc_5>=3)
Read [invariant] property : SharedMemory-PT-000010-ReachabilityCardinality-15 with value :((!((Memory_4>=1)&&(Ext_Mem_Acc_3_5>=2)))||(Ext_Mem_Acc_4_3<=Ext_Mem_Acc_9_2))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 210 rows 131 cols
invariant :Ext_Mem_Acc_3_8 + Ext_Mem_Acc_4_8 + Ext_Mem_Acc_5_8 + Ext_Mem_Acc_6_8 + Ext_Mem_Acc_1_8 + Ext_Mem_Acc_2_8 + Ext_Mem_Acc_7_8 + Ext_Mem_Acc_9_8 + Ext_Mem_Acc_10_8 + Memory_8 = 1
invariant :Ext_Mem_Acc_2_4 + Ext_Mem_Acc_1_4 + Ext_Mem_Acc_6_4 + Ext_Mem_Acc_7_4 + Ext_Mem_Acc_3_4 + Ext_Mem_Acc_5_4 + Ext_Mem_Acc_10_4 + Ext_Mem_Acc_8_4 + Ext_Mem_Acc_9_4 + Memory_4 = 1
invariant :Ext_Mem_Acc_2_1 + Ext_Mem_Acc_3_1 + Ext_Mem_Acc_4_1 + Ext_Mem_Acc_5_1 + Ext_Mem_Acc_6_1 + Ext_Mem_Acc_7_1 + Ext_Mem_Acc_8_1 + Ext_Mem_Acc_9_1 + Ext_Mem_Acc_10_1 + Memory_1 = 1
invariant :Ext_Mem_Acc_3_1 + Ext_Mem_Acc_3_2 + Ext_Mem_Acc_3_4 + Ext_Mem_Acc_3_5 + Ext_Mem_Acc_3_6 + -1'Ext_Mem_Acc_2_7 + -1'Ext_Mem_Acc_1_7 + -1'Ext_Mem_Acc_8_7 + -1'Ext_Mem_Acc_6_7 + -1'Ext_Mem_Acc_5_7 + -1'Ext_Mem_Acc_4_7 + -1'Ext_Mem_Acc_4_8 + -1'Ext_Mem_Acc_5_8 + -1'Ext_Mem_Acc_6_8 + -1'Ext_Mem_Acc_9_7 + -1'Ext_Mem_Acc_10_7 + -1'Ext_Mem_Acc_1_8 + -1'Ext_Mem_Acc_2_8 + Ext_Mem_Acc_3_9 + -1'Ext_Mem_Acc_7_8 + -1'Ext_Mem_Acc_9_8 + -1'Ext_Mem_Acc_10_8 + Ext_Mem_Acc_3_10 + -1'Memory_7 + -1'Memory_8 + Active_3 + Queue_3 + OwnMemAcc_3 = -1
invariant :Ext_Mem_Acc_10_1 + Ext_Mem_Acc_10_2 + Ext_Mem_Acc_10_3 + Ext_Mem_Acc_10_4 + Ext_Mem_Acc_10_5 + Ext_Mem_Acc_10_6 + Ext_Mem_Acc_10_7 + Ext_Mem_Acc_10_8 + Ext_Mem_Acc_10_9 + Active_10 + Queue_10 + OwnMemAcc_10 = 1
invariant :Ext_Mem_Acc_5_1 + Ext_Mem_Acc_5_2 + Ext_Mem_Acc_5_3 + Ext_Mem_Acc_5_4 + Ext_Mem_Acc_5_6 + Ext_Mem_Acc_5_7 + Ext_Mem_Acc_5_8 + Ext_Mem_Acc_5_9 + Ext_Mem_Acc_5_10 + Active_5 + Queue_5 + OwnMemAcc_5 = 1
invariant :Ext_Mem_Acc_4_6 + Ext_Mem_Acc_3_6 + Ext_Mem_Acc_2_6 + Ext_Mem_Acc_1_6 + Ext_Mem_Acc_9_6 + Ext_Mem_Acc_8_6 + Ext_Mem_Acc_7_6 + Ext_Mem_Acc_5_6 + Ext_Mem_Acc_10_6 + Memory_6 = 1
invariant :Ext_Mem_Acc_2_9 + Ext_Mem_Acc_3_9 + Ext_Mem_Acc_4_9 + Ext_Mem_Acc_5_9 + Ext_Mem_Acc_1_9 + Ext_Mem_Acc_7_9 + Ext_Mem_Acc_6_9 + Ext_Mem_Acc_10_9 + Ext_Mem_Acc_8_9 + Memory_9 = 1
invariant :-1'Ext_Mem_Acc_3_1 + -1'Ext_Mem_Acc_4_1 + -1'Ext_Mem_Acc_5_1 + -1'Ext_Mem_Acc_6_1 + -1'Ext_Mem_Acc_7_1 + -1'Ext_Mem_Acc_8_1 + -1'Ext_Mem_Acc_9_1 + -1'Ext_Mem_Acc_10_1 + Ext_Mem_Acc_2_3 + -1'Ext_Mem_Acc_1_4 + -1'Ext_Mem_Acc_6_4 + -1'Ext_Mem_Acc_7_4 + -1'Ext_Mem_Acc_3_4 + -1'Ext_Mem_Acc_5_4 + -1'Ext_Mem_Acc_10_4 + -1'Ext_Mem_Acc_8_4 + -1'Ext_Mem_Acc_9_4 + Ext_Mem_Acc_2_5 + Ext_Mem_Acc_2_6 + Ext_Mem_Acc_2_7 + Ext_Mem_Acc_2_8 + -1'Ext_Mem_Acc_3_9 + -1'Ext_Mem_Acc_4_9 + -1'Ext_Mem_Acc_5_9 + -1'Ext_Mem_Acc_1_9 + -1'Ext_Mem_Acc_1_10 + -1'Ext_Mem_Acc_4_10 + -1'Ext_Mem_Acc_3_10 + -1'Ext_Mem_Acc_7_9 + -1'Ext_Mem_Acc_6_9 + -1'Ext_Mem_Acc_10_9 + -1'Ext_Mem_Acc_8_9 + -1'Ext_Mem_Acc_9_10 + -1'Memory_1 + -1'Ext_Mem_Acc_6_10 + -1'Ext_Mem_Acc_5_10 + -1'Ext_Mem_Acc_8_10 + -1'Ext_Mem_Acc_7_10 + -1'Memory_9 + -1'Memory_10 + -1'Memory_4 + Active_2 + Queue_2 + OwnMemAcc_2 = -3
invariant :Ext_Mem_Acc_1_3 + Ext_Mem_Acc_4_3 + Ext_Mem_Acc_2_3 + Ext_Mem_Acc_6_3 + Ext_Mem_Acc_5_3 + Ext_Mem_Acc_8_3 + Ext_Mem_Acc_7_3 + Ext_Mem_Acc_10_3 + Ext_Mem_Acc_9_3 + Memory_3 = 1
invariant :Ext_Bus + -1'Memory_2 + -1'Memory_1 + -1'Memory_9 + -1'Memory_10 + -1'Memory_7 + -1'Memory_8 + -1'Memory_5 + -1'Memory_6 + -1'Memory_3 + -1'Memory_4 = -9
invariant :-1'Ext_Mem_Acc_3_2 + -1'Ext_Mem_Acc_4_2 + -1'Ext_Mem_Acc_5_2 + -1'Ext_Mem_Acc_7_2 + -1'Ext_Mem_Acc_6_2 + -1'Ext_Mem_Acc_9_2 + -1'Ext_Mem_Acc_8_2 + -1'Ext_Mem_Acc_10_2 + -1'Ext_Mem_Acc_4_3 + -1'Ext_Mem_Acc_2_3 + -1'Ext_Mem_Acc_6_3 + -1'Ext_Mem_Acc_5_3 + -1'Ext_Mem_Acc_8_3 + -1'Ext_Mem_Acc_7_3 + -1'Ext_Mem_Acc_10_3 + -1'Ext_Mem_Acc_9_3 + Ext_Mem_Acc_1_4 + -1'Ext_Mem_Acc_4_5 + -1'Ext_Mem_Acc_6_5 + -1'Ext_Mem_Acc_2_5 + -1'Ext_Mem_Acc_3_5 + -1'Ext_Mem_Acc_9_5 + -1'Ext_Mem_Acc_10_5 + -1'Ext_Mem_Acc_7_5 + -1'Ext_Mem_Acc_8_5 + Ext_Mem_Acc_1_6 + Ext_Mem_Acc_1_7 + Ext_Mem_Acc_1_8 + Ext_Mem_Acc_1_9 + Ext_Mem_Acc_1_10 + -1'Memory_2 + -1'Memory_5 + -1'Memory_3 + Active_1 + Queue_1 + OwnMemAcc_1 = -2
invariant :Ext_Mem_Acc_9_1 + Ext_Mem_Acc_9_2 + Ext_Mem_Acc_9_3 + Ext_Mem_Acc_9_4 + Ext_Mem_Acc_9_5 + Ext_Mem_Acc_9_6 + Ext_Mem_Acc_9_7 + Ext_Mem_Acc_9_8 + Ext_Mem_Acc_9_10 + Active_9 + Queue_9 + OwnMemAcc_9 = 1
invariant :Ext_Mem_Acc_6_1 + Ext_Mem_Acc_6_2 + Ext_Mem_Acc_6_3 + Ext_Mem_Acc_6_4 + Ext_Mem_Acc_6_5 + Ext_Mem_Acc_6_7 + Ext_Mem_Acc_6_8 + Ext_Mem_Acc_6_9 + Ext_Mem_Acc_6_10 + Active_6 + Queue_6 + OwnMemAcc_6 = 1
invariant :Ext_Mem_Acc_2_10 + Ext_Mem_Acc_1_10 + Ext_Mem_Acc_4_10 + Ext_Mem_Acc_3_10 + Ext_Mem_Acc_9_10 + Ext_Mem_Acc_6_10 + Ext_Mem_Acc_5_10 + Ext_Mem_Acc_8_10 + Ext_Mem_Acc_7_10 + Memory_10 = 1
invariant :Ext_Mem_Acc_8_1 + Ext_Mem_Acc_8_2 + Ext_Mem_Acc_8_3 + Ext_Mem_Acc_8_4 + Ext_Mem_Acc_8_5 + Ext_Mem_Acc_8_6 + Ext_Mem_Acc_8_7 + Ext_Mem_Acc_8_9 + Ext_Mem_Acc_8_10 + Active_8 + Queue_8 + OwnMemAcc_8 = 1
invariant :Ext_Mem_Acc_7_1 + Ext_Mem_Acc_7_2 + Ext_Mem_Acc_7_3 + Ext_Mem_Acc_7_4 + Ext_Mem_Acc_7_5 + Ext_Mem_Acc_7_6 + Ext_Mem_Acc_7_8 + Ext_Mem_Acc_7_9 + Ext_Mem_Acc_7_10 + Active_7 + Queue_7 + OwnMemAcc_7 = 1
invariant :Ext_Mem_Acc_4_1 + Ext_Mem_Acc_4_2 + Ext_Mem_Acc_4_3 + Ext_Mem_Acc_4_5 + -1'Ext_Mem_Acc_3_6 + -1'Ext_Mem_Acc_2_6 + -1'Ext_Mem_Acc_1_6 + -1'Ext_Mem_Acc_9_6 + -1'Ext_Mem_Acc_8_6 + -1'Ext_Mem_Acc_7_6 + -1'Ext_Mem_Acc_5_6 + -1'Ext_Mem_Acc_10_6 + Ext_Mem_Acc_4_7 + Ext_Mem_Acc_4_8 + Ext_Mem_Acc_4_9 + Ext_Mem_Acc_4_10 + -1'Memory_6 + Active_4 + Queue_4 + OwnMemAcc_4 = 0
invariant :Ext_Mem_Acc_1_5 + Ext_Mem_Acc_4_5 + Ext_Mem_Acc_6_5 + Ext_Mem_Acc_2_5 + Ext_Mem_Acc_3_5 + Ext_Mem_Acc_9_5 + Ext_Mem_Acc_10_5 + Ext_Mem_Acc_7_5 + Ext_Mem_Acc_8_5 + Memory_5 = 1
invariant :Ext_Mem_Acc_3_7 + Ext_Mem_Acc_2_7 + Ext_Mem_Acc_1_7 + Ext_Mem_Acc_8_7 + Ext_Mem_Acc_6_7 + Ext_Mem_Acc_5_7 + Ext_Mem_Acc_4_7 + Ext_Mem_Acc_9_7 + Ext_Mem_Acc_10_7 + Memory_7 = 1
invariant :Ext_Mem_Acc_1_2 + Ext_Mem_Acc_3_2 + Ext_Mem_Acc_4_2 + Ext_Mem_Acc_5_2 + Ext_Mem_Acc_7_2 + Ext_Mem_Acc_6_2 + Ext_Mem_Acc_9_2 + Ext_Mem_Acc_8_2 + Ext_Mem_Acc_10_2 + Memory_2 = 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory\_PT\_000010\_flat\_flat,1.83052e+06,0.485139,19444,2,10275,5,37971,6,0,737,18239,0
Total reachable state count : 1830519

Verifying 15 reachability properties.
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-00 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-00,1,0.487496,19536,2,132,6,37971,7,0,758,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-01 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-01,1,0.51673,19584,2,132,6,37971,8,0,950,18239,0
Invariant property SharedMemory-PT-000010-ReachabilityCardinality-02 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-02,1,0.51758,19584,2,132,6,37971,9,0,960,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-03 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-03,1,0.517979,19648,2,132,6,37971,9,0,960,18239,0
Invariant property SharedMemory-PT-000010-ReachabilityCardinality-05 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-05,0,0.528526,19648,1,0,6,37971,10,0,982,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-06 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-06,1,0.534123,19648,2,132,7,37971,11,0,1033,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-07 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-07,1,0.536928,19648,2,132,8,37971,12,0,1070,18239,0
Invariant property SharedMemory-PT-000010-ReachabilityCardinality-08 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-08,12,0.540372,19648,2,283,9,37971,13,0,1085,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-09 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : SharedMemory-PT-000010-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-09,0,0.543647,19648,1,0,9,37971,14,0,1105,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-10 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : SharedMemory-PT-000010-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-10,0,0.552343,19648,1,0,9,37971,15,0,1106,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-11 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : SharedMemory-PT-000010-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-11,0,0.55665,19648,1,0,9,37971,16,0,1123,18239,0
Invariant property SharedMemory-PT-000010-ReachabilityCardinality-12 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-12,0,0.557284,19648,1,0,9,37971,17,0,1124,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-13 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : SharedMemory-PT-000010-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-13,0,0.563885,19648,1,0,9,37971,18,0,1144,18239,0
Reachability property SharedMemory-PT-000010-ReachabilityCardinality-14 does not hold.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : SharedMemory-PT-000010-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-14,0,0.568362,19648,1,0,9,37971,19,0,1145,18239,0
Invariant property SharedMemory-PT-000010-ReachabilityCardinality-15 is true.
FORMULA SharedMemory-PT-000010-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-PT-000010-ReachabilityCardinality-15,0,0.571298,19648,1,0,9,37971,20,0,1150,18239,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527429816307

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 27, 2018 2:03:33 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 27, 2018 2:03:33 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 27, 2018 2:03:33 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 133 ms
May 27, 2018 2:03:33 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 131 places.
May 27, 2018 2:03:33 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 210 transitions.
May 27, 2018 2:03:34 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 31 ms
May 27, 2018 2:03:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 119 ms
May 27, 2018 2:03:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 89 ms
May 27, 2018 2:03:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 107 ms
May 27, 2018 2:03:34 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 7 ms
May 27, 2018 2:03:34 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 3 ms
May 27, 2018 2:03:34 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 210 transitions.
May 27, 2018 2:03:34 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 210 transitions.
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 21 place invariants in 63 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 15 in 678 ms.
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-00(UNSAT) depth K=0 took 16 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-01(UNSAT) depth K=0 took 15 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-02(UNSAT) depth K=0 took 12 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-03(UNSAT) depth K=0 took 16 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-05(UNSAT) depth K=0 took 2 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-06(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-07(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-08(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-09(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-10(UNSAT) depth K=0 took 2 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-11(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-12(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-13(UNSAT) depth K=0 took 0 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-14(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-15(UNSAT) depth K=0 took 1 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 210 transitions.
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-07(UNSAT) depth K=1 took 23 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-08(UNSAT) depth K=1 took 17 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-09(UNSAT) depth K=1 took 9 ms
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property SharedMemory-PT-000010-ReachabilityCardinality-10(UNSAT) depth K=1 took 11 ms
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying SharedMemory-PT-000010-ReachabilityCardinality-11 SMT depth 1
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 1
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 1
May 27, 2018 2:03:35 PM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (define-fun trsrc100 ((src (Array Int Int))(dst (Array Int Int))) Bool (and (_enabledsrc__100 src) (= (store (store (store (store src 124 (- (select src 124) 1)) 85 (- (select src 85) 1)) 5 (+ (select src 5) 1)) 88 (- (select src 88) 1)) dst))) with error (error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
Exception in thread "Thread-8" java.lang.RuntimeException: Error when declaring system variables to SMT solver.(error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.init(NextBMCSolver.java:93)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:59)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 27, 2018 2:03:35 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 15 properties. Interrupting other analysis methods.
May 27, 2018 2:03:35 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 894ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SharedMemory-PT-000010"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/SharedMemory-PT-000010.tgz
mv SharedMemory-PT-000010 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is SharedMemory-PT-000010, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r177-smll-152708747500110"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;