Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 248K
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.5K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 5 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rwxr-xr-x 1 mcc users 70K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is TriangularGrid-PT-3026, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r176-smll-152708747200391
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TriangularGrid-PT-3026-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527371226842

Flatten gal took : 92 ms
Applied a total of 0 rules in 9 ms. Remains 108 /108 variables (removed 0) and now considering 90/90 (removed 0) transitions.
// Phase 1: matrix 90 rows 108 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 90 rows 108 cols
invariant :pi2_3_5 + pil2_3_5 = 1
invariant :pb1_3_3 + pb2_3_3 + pb3_3_3 + pbl_3_3 = 12
invariant :po2_2_1 + pol2_2_1 = 1
invariant :pi2_2_1 + pil2_2_1 = 1
invariant :po3_2_1 + pol3_2_1 = 1
invariant :pi3_1_1 + pil3_1_1 = 1
invariant :pi1_1_1 + pil1_1_1 = 1
invariant :pi1_3_5 + pil1_3_5 = 1
invariant :po2_1_1 + pol2_1_1 = 1
invariant :pi2_2_3 + pil2_2_3 = 1
invariant :pb1_2_1 + pb2_2_1 + pb3_2_1 + pbl_2_1 = 12
invariant :pi3_2_1 + pil3_2_1 = 1
invariant :po1_1_1 + pol1_1_1 = 1
invariant :pb1_1_1 + pb2_1_1 + pb3_1_1 + pbl_1_1 = 12
invariant :pi1_3_1 + pil1_3_1 = 1
invariant :pi1_2_1 + pil1_2_1 = 1
invariant :po2_3_3 + pol2_3_3 = 1
invariant :pi1_2_3 + pil1_2_3 = 1
invariant :po1_3_5 + pol1_3_5 = 1
invariant :pb1_2_2 + pb2_2_2 + pb3_2_2 + -1'pbl_1_1 + -1'pbl_2_1 + -1'pbl_2_3 + -1'pbl_3_1 + -1'pbl_3_2 + -1'pbl_3_3 + -1'pbl_3_4 + -1'pbl_3_5 + -1'pil1_1_1 + -1'pil1_2_1 + -1'pil1_2_3 + -1'pil1_3_1 + -1'pil1_3_3 + -1'pil1_3_5 + -1'pil2_1_1 + -1'pil2_2_1 + -1'pil2_2_3 + -1'pil2_3_1 + -1'pil2_3_3 + -1'pil2_3_5 + -1'pil3_1_1 + -1'pil3_2_1 + -1'pil3_2_3 + -1'pil3_3_1 + -1'pil3_3_3 + -1'pil3_3_5 + -1'pol1_1_1 + -1'pol1_2_1 + -1'pol1_2_3 + -1'pol1_3_1 + -1'pol1_3_3 + -1'pol1_3_5 + -1'pol2_1_1 + -1'pol2_2_1 + -1'pol2_2_3 + -1'pol2_3_1 + -1'pol2_3_3 + -1'pol2_3_5 + -1'pol3_1_1 + -1'pol3_2_1 + -1'pol3_2_3 + -1'pol3_3_1 + -1'pol3_3_3 + -1'pol3_3_5 = -78
invariant :po3_1_1 + pol3_1_1 = 1
invariant :pb1_3_5 + pb2_3_5 + pb3_3_5 + pbl_3_5 = 12
invariant :pbl_1_1 + pbl_2_1 + pbl_2_2 + pbl_2_3 + pbl_3_1 + pbl_3_2 + pbl_3_3 + pbl_3_4 + pbl_3_5 + pil1_1_1 + pil1_2_1 + pil1_2_3 + pil1_3_1 + pil1_3_3 + pil1_3_5 + pil2_1_1 + pil2_2_1 + pil2_2_3 + pil2_3_1 + pil2_3_3 + pil2_3_5 + pil3_1_1 + pil3_2_1 + pil3_2_3 + pil3_3_1 + pil3_3_3 + pil3_3_5 + pol1_1_1 + pol1_2_1 + pol1_2_3 + pol1_3_1 + pol1_3_3 + pol1_3_5 + pol2_1_1 + pol2_2_1 + pol2_2_3 + pol2_3_1 + pol2_3_3 + pol2_3_5 + pol3_1_1 + pol3_2_1 + pol3_2_3 + pol3_3_1 + pol3_3_3 + pol3_3_5 = 90
invariant :po1_2_3 + pol1_2_3 = 1
invariant :pi2_3_3 + pil2_3_3 = 1
invariant :pi3_3_5 + pil3_3_5 = 1
invariant :po1_2_1 + pol1_2_1 = 1
invariant :po3_3_3 + pol3_3_3 = 1
invariant :po2_2_3 + pol2_2_3 = 1
invariant :pi1_3_3 + pil1_3_3 = 1
invariant :pb1_2_3 + pb2_2_3 + pb3_2_3 + pbl_2_3 = 12
invariant :po2_3_5 + pol2_3_5 = 1
invariant :pi3_3_1 + pil3_3_1 = 1
invariant :po2_3_1 + pol2_3_1 = 1
invariant :po1_3_3 + pol1_3_3 = 1
invariant :po3_3_1 + pol3_3_1 = 1
invariant :pb1_3_1 + pb2_3_1 + pb3_3_1 + pbl_3_1 = 12
invariant :pi3_2_3 + pil3_2_3 = 1
invariant :pi3_3_3 + pil3_3_3 = 1
invariant :pb1_3_4 + pb2_3_4 + pb3_3_4 + pbl_3_4 = 12
invariant :po3_2_3 + pol3_2_3 = 1
invariant :po3_3_5 + pol3_3_5 = 1
invariant :pb1_3_2 + pb2_3_2 + pb3_3_2 + pbl_3_2 = 12
invariant :pi2_1_1 + pil2_1_1 = 1
invariant :po1_3_1 + pol1_3_1 = 1
invariant :pi2_3_1 + pil2_3_1 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 2239 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 40 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,3.75215e+28,61.1376,1000332,2,33760,5,5.59658e+06,6,0,525,6.26965e+06,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,6.76054e+06,75.3677,1000712,2,77501,7,5.59658e+06,9,1,2870,6.26965e+06,2

System contains 6.76054e+06 deadlocks (shown below if less than --print-limit option) !
FORMULA TriangularGrid-PT-3026-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
[ 6760540 states ] showing 10 first states
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 po2_2_3=1 pi2_2_3=1 pb2_2_3=12 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=1 po2_2_3=1 pi2_2_3=1 pb2_2_3=11 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=2 po2_2_3=1 pi2_2_3=1 pb2_2_3=10 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=3 po2_2_3=1 pi2_2_3=1 pb2_2_3=9 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=4 po2_2_3=1 pi2_2_3=1 pb2_2_3=8 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=5 po2_2_3=1 pi2_2_3=1 pb2_2_3=7 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=6 po2_2_3=1 pi2_2_3=1 pb2_2_3=6 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=7 po2_2_3=1 pi2_2_3=1 pb2_2_3=5 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=8 po2_2_3=1 pi2_2_3=1 pb2_2_3=4 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
[ po3_3_5=1 po2_3_5=1 pi3_3_5=1 pi2_3_5=1 pb2_3_5=1 pb1_3_5=11 pil1_3_5=1 po1_3_5=1 pb3_3_4=12 po3_2_3=1 po2_3_3=1 pil2_3_3=1 pol3_3_3=1 pil3_3_3=1 pi3_2_3=1 pbl_3_3=12 pb3_2_3=9 po2_2_3=1 pi2_2_3=1 pb2_2_3=3 pil1_3_3=1 pol1_3_3=1 pi1_2_3=1 pol1_2_3=1 pbl_3_2=12 pb1_2_2=7 pol2_3_1=1 pbl_2_2=5 pol3_2_1=1 pol2_2_1=1 pil2_3_1=1 pol3_1_1=1 pol3_3_1=1 pil3_2_1=1 pil3_3_1=1 pbl_3_1=12 pil2_2_1=1 pil1_3_1=1 pol1_3_1=1 pbl_2_1=12 pil3_1_1=1 pil1_2_1=1 pol1_2_1=1 pbl_1_1=12 pol2_1_1=1 pil2_1_1=1 pil1_1_1=1 pol1_1_1=1 ]
ITS tools runner thread asked to quit. Dying gracefully.
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527371307334

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 26, 2018 9:47:09 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 26, 2018 9:47:09 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 26, 2018 9:47:09 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 69 ms
May 26, 2018 9:47:09 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 108 places.
May 26, 2018 9:47:09 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 90 transitions.
May 26, 2018 9:47:09 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 14 ms
May 26, 2018 9:47:09 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 88 ms
May 26, 2018 9:47:09 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 4 ms
May 26, 2018 9:47:10 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 90 transitions.
May 26, 2018 9:47:10 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 3 ms
May 26, 2018 9:47:10 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 90 transitions.
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 46 place invariants in 32 ms
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 108 variables to be positive in 345 ms
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 90 transitions.
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/90 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 5 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 90 transitions.
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 5 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 26, 2018 9:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 90 transitions.
May 26, 2018 9:47:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/90) took 3296 ms. Total solver calls (SAT/UNSAT): 765(738/27)
May 26, 2018 9:47:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/90) took 6352 ms. Total solver calls (SAT/UNSAT): 1520(1487/33)
May 26, 2018 9:47:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/90) took 9505 ms. Total solver calls (SAT/UNSAT): 2175(2135/40)
May 26, 2018 9:47:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/90) took 12602 ms. Total solver calls (SAT/UNSAT): 2679(2633/46)
May 26, 2018 9:47:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/90) took 15689 ms. Total solver calls (SAT/UNSAT): 3339(3282/57)
May 26, 2018 9:47:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/90) took 18753 ms. Total solver calls (SAT/UNSAT): 3960(3897/63)
May 26, 2018 9:47:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 19125 ms. Total solver calls (SAT/UNSAT): 4005(3942/63)
May 26, 2018 9:47:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 90 transitions.
May 26, 2018 9:47:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 3750 ms. Total solver calls (SAT/UNSAT): 189(0/189)
May 26, 2018 9:47:33 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 23393ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TriangularGrid-PT-3026"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/TriangularGrid-PT-3026.tgz
mv TriangularGrid-PT-3026 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is TriangularGrid-PT-3026, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r176-smll-152708747200391"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;