About the Execution of ITS-Tools for SimpleLoadBal-PT-10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15748.890 | 149570.00 | 303974.00 | 615.60 | F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 700K
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.6K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 348 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 530K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is SimpleLoadBal-PT-10, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r176-smll-152708746900160
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SimpleLoadBal-PT-10-ReachabilityDeadlock-0
=== Now, execution of the tool begins
BK_START 1527228678801
Flatten gal took : 466 ms
Performed 2 Post agglomeration using F-continuation condition.
Constant places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 102 transition count 603
Performed 10 Post agglomeration using F-continuation condition.
Constant places removed 20 places and 0 transitions.
Iterating post reduction 1 with 20 rules applied. Total rules applied 22 place count 82 transition count 593
Performed 10 Post agglomeration using F-continuation condition.
Constant places removed 10 places and 0 transitions.
Iterating post reduction 2 with 10 rules applied. Total rules applied 32 place count 72 transition count 583
Applied a total of 32 rules in 107 ms. Remains 72 /104 variables (removed 32) and now considering 583/605 (removed 22) transitions.
Normalized transition count is 453
// Phase 1: matrix 453 rows 72 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]
its-ctl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 453
// Phase 1: matrix 453 rows 72 cols
invariant :P_client_request_1 + -1'P_server_waiting_2 + P_server_notification_ack_2 + P_server_request_1_1 + -1'P_server_request_2_2 + -1'P_server_request_3_2 + -1'P_server_request_4_2 + -1'P_server_request_5_2 + -1'P_server_request_6_2 + -1'P_server_request_7_2 + -1'P_server_request_8_2 + -1'P_server_request_9_2 + -1'P_server_request_10_2 + P_lb_routing_1_1 + -6'P_lb_load_2_0 + -5'P_lb_load_2_1 + -4'P_lb_load_2_2 + -3'P_lb_load_2_3 + -2'P_lb_load_2_4 + -1'P_lb_load_2_5 + P_lb_load_2_7 + 2'P_lb_load_2_8 + 3'P_lb_load_2_9 + 4'P_lb_load_2_10 = -5
invariant :P_client_request_8 + P_server_request_8_1 + P_server_request_8_2 + P_lb_routing_1_8 = 1
invariant :P_client_request_3 + P_server_request_3_1 + P_server_request_3_2 + P_lb_routing_1_3 = 1
invariant :P_client_request_2 + P_server_request_2_1 + P_server_request_2_2 + P_lb_routing_1_2 = 1
invariant :-1'P_server_waiting_1 + P_server_notification_1 + P_server_notification_ack_1 = 0
invariant :P_client_request_6 + P_server_request_6_1 + P_server_request_6_2 + P_lb_routing_1_6 = 1
invariant :P_client_request_4 + P_server_request_4_1 + P_server_request_4_2 + P_lb_routing_1_4 = 1
invariant :P_server_waiting_2 + -1'P_server_notification_ack_2 + P_server_request_1_2 + P_server_request_2_2 + P_server_request_3_2 + P_server_request_4_2 + P_server_request_5_2 + P_server_request_6_2 + P_server_request_7_2 + P_server_request_8_2 + P_server_request_9_2 + P_server_request_10_2 + 6'P_lb_load_2_0 + 5'P_lb_load_2_1 + 4'P_lb_load_2_2 + 3'P_lb_load_2_3 + 2'P_lb_load_2_4 + P_lb_load_2_5 + -1'P_lb_load_2_7 + -2'P_lb_load_2_8 + -3'P_lb_load_2_9 + -4'P_lb_load_2_10 = 6
invariant :P_client_request_7 + P_server_request_7_1 + P_server_request_7_2 + P_lb_routing_1_7 = 1
invariant :P_client_request_9 + P_server_request_9_1 + P_server_request_9_2 + P_lb_routing_1_9 = 1
invariant :P_client_request_5 + P_server_request_5_1 + P_server_request_5_2 + P_lb_routing_1_5 = 1
invariant :P_lb_load_2_0 + P_lb_load_2_1 + P_lb_load_2_2 + P_lb_load_2_3 + P_lb_load_2_4 + P_lb_load_2_5 + P_lb_load_2_6 + P_lb_load_2_7 + P_lb_load_2_8 + P_lb_load_2_9 + P_lb_load_2_10 = 1
invariant :P_server_idle_1 + P_server_waiting_1 = 1
invariant :-1'P_client_request_1 + -1'P_client_request_2 + -1'P_client_request_3 + -1'P_client_request_4 + -1'P_client_request_5 + -1'P_client_request_6 + -1'P_client_request_7 + -1'P_client_request_8 + -1'P_client_request_9 + -1'P_client_request_10 + P_server_waiting_1 + P_server_waiting_2 + -1'P_server_notification_ack_1 + -1'P_server_notification_ack_2 + -1'P_lb_routing_1_1 + -1'P_lb_routing_1_2 + -1'P_lb_routing_1_3 + -1'P_lb_routing_1_4 + -1'P_lb_routing_1_5 + -1'P_lb_routing_1_6 + -1'P_lb_routing_1_7 + -1'P_lb_routing_1_8 + -1'P_lb_routing_1_9 + -1'P_lb_routing_1_10 + 5'P_lb_load_1_0 + 4'P_lb_load_1_1 + 3'P_lb_load_1_2 + 2'P_lb_load_1_3 + P_lb_load_1_4 + -1'P_lb_load_1_6 + -2'P_lb_load_1_7 + -3'P_lb_load_1_8 + -4'P_lb_load_1_9 + -5'P_lb_load_1_10 + 6'P_lb_load_2_0 + 5'P_lb_load_2_1 + 4'P_lb_load_2_2 + 3'P_lb_load_2_3 + 2'P_lb_load_2_4 + P_lb_load_2_5 + -1'P_lb_load_2_7 + -2'P_lb_load_2_8 + -3'P_lb_load_2_9 + -4'P_lb_load_2_10 = 1
invariant :P_client_request_1 + P_client_request_2 + P_client_request_3 + P_client_request_4 + P_client_request_5 + P_client_request_6 + P_client_request_7 + P_client_request_8 + P_client_request_9 + P_client_request_10 + -1'P_server_waiting_1 + -1'P_server_waiting_2 + P_server_notification_ack_1 + P_server_notification_ack_2 + P_lb_routing_1_1 + P_lb_routing_1_2 + P_lb_routing_1_3 + P_lb_routing_1_4 + P_lb_routing_1_5 + P_lb_routing_1_6 + P_lb_routing_1_7 + P_lb_routing_1_8 + P_lb_routing_1_9 + P_lb_routing_1_10 + -4'P_lb_load_1_0 + -3'P_lb_load_1_1 + -2'P_lb_load_1_2 + -1'P_lb_load_1_3 + P_lb_load_1_5 + 2'P_lb_load_1_6 + 3'P_lb_load_1_7 + 4'P_lb_load_1_8 + 5'P_lb_load_1_9 + 6'P_lb_load_1_10 + -6'P_lb_load_2_0 + -5'P_lb_load_2_1 + -4'P_lb_load_2_2 + -3'P_lb_load_2_3 + -2'P_lb_load_2_4 + -1'P_lb_load_2_5 + P_lb_load_2_7 + 2'P_lb_load_2_8 + 3'P_lb_load_2_9 + 4'P_lb_load_2_10 = 0
invariant :P_server_idle_2 + P_server_waiting_2 = 1
invariant :P_client_request_10 + P_server_request_10_1 + P_server_request_10_2 + P_lb_routing_1_10 = 1
invariant :P_lb_idle_1 + P_lb_routing_1_1 + P_lb_routing_1_2 + P_lb_routing_1_3 + P_lb_routing_1_4 + P_lb_routing_1_5 + P_lb_routing_1_6 + P_lb_routing_1_7 + P_lb_routing_1_8 + P_lb_routing_1_9 + P_lb_routing_1_10 + P_lb_balancing_1 = 1
invariant :-1'P_server_waiting_2 + P_server_notification_2 + P_server_notification_ack_2 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 9654 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 52 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.47532e+06,44.5403,894992,2,343754,5,2.12402e+06,6,0,874,1.60667e+06,0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,0,141.81,2247676,1,0,6,7.88523e+06,9,1,6412,2.80759e+06,2
System contains 0 deadlocks (shown below if less than --print-limit option) !
FORMULA SimpleLoadBal-PT-10-ReachabilityDeadlock-0 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
EmptySet
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527228828371
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 6:11:21 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 25, 2018 6:11:21 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 6:11:22 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 234 ms
May 25, 2018 6:11:22 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 104 places.
May 25, 2018 6:11:22 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 605 transitions.
May 25, 2018 6:11:22 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 73 ms
May 25, 2018 6:11:22 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 459 ms
May 25, 2018 6:11:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 13 ms
May 25, 2018 6:11:23 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 605 transitions.
May 25, 2018 6:11:24 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 6 ms
May 25, 2018 6:11:24 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 583 transitions.
May 25, 2018 6:11:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 19 place invariants in 71 ms
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 72 variables to be positive in 1383 ms
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 583 transitions.
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/583 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 118 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 583 transitions.
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 42 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 6:11:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 583 transitions.
May 25, 2018 6:11:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/583) took 3065 ms. Total solver calls (SAT/UNSAT): 2273(1149/1124)
May 25, 2018 6:11:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/583) took 6404 ms. Total solver calls (SAT/UNSAT): 6172(1317/4855)
May 25, 2018 6:11:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/583) took 9445 ms. Total solver calls (SAT/UNSAT): 10076(1391/8685)
May 25, 2018 6:11:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/583) took 12802 ms. Total solver calls (SAT/UNSAT): 14486(1465/13021)
May 25, 2018 6:11:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/583) took 16116 ms. Total solver calls (SAT/UNSAT): 18836(1539/17297)
May 25, 2018 6:11:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(41/583) took 19483 ms. Total solver calls (SAT/UNSAT): 23128(1619/21509)
May 25, 2018 6:11:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(49/583) took 22687 ms. Total solver calls (SAT/UNSAT): 27336(1679/25657)
May 25, 2018 6:11:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/583) took 26018 ms. Total solver calls (SAT/UNSAT): 31500(1759/29741)
May 25, 2018 6:11:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/583) took 29130 ms. Total solver calls (SAT/UNSAT): 35580(1819/33761)
May 25, 2018 6:11:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/583) took 32364 ms. Total solver calls (SAT/UNSAT): 39616(1899/37717)
May 25, 2018 6:12:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/583) took 35434 ms. Total solver calls (SAT/UNSAT): 43588(1979/41609)
May 25, 2018 6:12:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/583) took 38492 ms. Total solver calls (SAT/UNSAT): 47476(2039/45437)
May 25, 2018 6:12:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/583) took 41701 ms. Total solver calls (SAT/UNSAT): 51796(2129/49667)
May 25, 2018 6:12:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(108/583) took 44917 ms. Total solver calls (SAT/UNSAT): 56481(2209/54272)
May 25, 2018 6:12:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(117/583) took 48215 ms. Total solver calls (SAT/UNSAT): 60630(2299/58331)
May 25, 2018 6:12:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(126/583) took 51263 ms. Total solver calls (SAT/UNSAT): 64678(2369/62309)
May 25, 2018 6:12:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(135/583) took 54390 ms. Total solver calls (SAT/UNSAT): 68665(2459/66206)
May 25, 2018 6:12:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(145/583) took 57686 ms. Total solver calls (SAT/UNSAT): 72980(2539/70441)
May 25, 2018 6:12:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(155/583) took 60982 ms. Total solver calls (SAT/UNSAT): 77215(2639/74576)
May 25, 2018 6:12:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(168/583) took 63989 ms. Total solver calls (SAT/UNSAT): 82551(2749/79802)
May 25, 2018 6:12:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(182/583) took 67040 ms. Total solver calls (SAT/UNSAT): 88130(2889/85241)
May 25, 2018 6:12:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(197/583) took 70096 ms. Total solver calls (SAT/UNSAT): 93870(3019/90851)
May 25, 2018 6:12:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(212/583) took 73306 ms. Total solver calls (SAT/UNSAT): 99384(3148/96236)
May 25, 2018 6:12:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(228/583) took 76324 ms. Total solver calls (SAT/UNSAT): 105020(3290/101730)
May 25, 2018 6:12:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(245/583) took 79459 ms. Total solver calls (SAT/UNSAT): 110739(3450/107289)
May 25, 2018 6:12:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(262/583) took 82482 ms. Total solver calls (SAT/UNSAT): 116159(3600/112559)
May 25, 2018 6:12:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(280/583) took 85512 ms. Total solver calls (SAT/UNSAT): 121584(3760/117824)
May 25, 2018 6:12:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(299/583) took 88615 ms. Total solver calls (SAT/UNSAT): 126960(3930/123030)
May 25, 2018 6:12:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(320/583) took 91707 ms. Total solver calls (SAT/UNSAT): 132386(4141/128245)
May 25, 2018 6:13:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(341/583) took 94791 ms. Total solver calls (SAT/UNSAT): 137446(4366/133080)
May 25, 2018 6:13:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(362/583) took 97794 ms. Total solver calls (SAT/UNSAT): 142054(4637/137417)
May 25, 2018 6:13:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(382/583) took 100806 ms. Total solver calls (SAT/UNSAT): 146082(4975/141107)
May 25, 2018 6:13:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(404/583) took 103949 ms. Total solver calls (SAT/UNSAT): 150049(5402/144647)
May 25, 2018 6:13:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(427/583) took 107052 ms. Total solver calls (SAT/UNSAT): 153681(5951/147730)
May 25, 2018 6:13:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(453/583) took 110058 ms. Total solver calls (SAT/UNSAT): 157149(6394/150755)
May 25, 2018 6:13:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(482/583) took 113131 ms. Total solver calls (SAT/UNSAT): 160221(6886/153335)
May 25, 2018 6:13:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(515/583) took 116142 ms. Total solver calls (SAT/UNSAT): 162671(7450/155221)
May 25, 2018 6:13:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 119085 ms. Total solver calls (SAT/UNSAT): 164211(8139/156072)
May 25, 2018 6:13:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 583 transitions.
May 25, 2018 6:13:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 522 ms. Total solver calls (SAT/UNSAT): 388(0/388)
May 25, 2018 6:13:26 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 122001ms conformant to PINS in folder :/home/mcc/execution
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SimpleLoadBal-PT-10"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/SimpleLoadBal-PT-10.tgz
mv SimpleLoadBal-PT-10 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is SimpleLoadBal-PT-10, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r176-smll-152708746900160"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;