Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 808K
-rw-r--r-- 1 mcc users 6.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 24K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.7K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 32K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 448K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is SafeBus-PT-06, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r152-smll-152685550400237
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SafeBus-PT-06-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527059930340

Flatten gal took : 248 ms
Applied a total of 0 rules in 23 ms. Remains 138 /138 variables (removed 0) and now considering 451/451 (removed 0) transitions.
Normalized transition count is 242
// Phase 1: matrix 242 rows 138 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 242
// Phase 1: matrix 242 rows 138 cols
invariant :Cpt1_1 + Cpt1_2 + Cpt1_3 + Cpt1_4 + Cpt1_5 + Cpt1_6 = 1
invariant :Cpt2_2 + AMC_1_1 + AMC_2_1 + AMC_3_1 + AMC_4_1 + AMC_5_1 + AMC_6_1 + -1'AMC_1_2 + -1'AMC_2_2 + -1'AMC_3_2 + -1'AMC_4_2 + -1'AMC_5_2 + -1'AMC_6_2 + -1'Cpt1_2 = 0
invariant :Cpt2_4 + AMC_1_3 + AMC_2_3 + AMC_3_3 + AMC_4_3 + AMC_5_3 + AMC_6_3 + -1'AMC_1_4 + -1'AMC_2_4 + -1'AMC_3_4 + -1'AMC_4_4 + -1'AMC_5_4 + -1'AMC_6_4 + -1'Cpt1_4 = 0
invariant :AMC_3_1 + AMC_3_2 + AMC_3_3 + AMC_3_4 + AMC_3_5 + AMC_3_6 + RMC_3 + PMC_3 + -1'wait_cable_3 = 0
invariant :wait_ack_5_1 + wait_ack_5_2 + wait_ack_5_3 + wait_ack_5_4 + wait_ack_5_6 + AMC_5_1 + AMC_5_2 + AMC_5_3 + AMC_5_4 + AMC_5_5 + AMC_5_6 + RMC_5 + PMC_5 + listen_5 + wait_msg_5 + loop_em_5 = 1
invariant :-1'wait_ack_1_2 + -1'wait_ack_1_3 + -1'wait_ack_1_4 + -1'wait_ack_1_5 + -1'wait_ack_1_6 + cable_used_1 + -1'FMC_1 + -1'PMC_1 = 0
invariant :AMC_2_1 + AMC_2_2 + AMC_2_3 + AMC_2_4 + AMC_2_5 + AMC_2_6 + RMC_2 + PMC_2 + -1'wait_cable_2 = 0
invariant :wait_ack_2_1 + wait_ack_2_3 + wait_ack_2_4 + wait_ack_2_5 + wait_ack_2_6 + listen_2 + wait_cable_2 + wait_msg_2 + loop_em_2 = 1
invariant :-1'wait_ack_6_1 + -1'wait_ack_6_2 + -1'wait_ack_6_3 + -1'wait_ack_6_4 + -1'wait_ack_6_5 + cable_used_6 + -1'FMC_6 + -1'PMC_6 = 0
invariant :wait_ack_4_1 + wait_ack_4_2 + wait_ack_4_3 + wait_ack_4_5 + wait_ack_4_6 + AMC_4_1 + AMC_4_2 + AMC_4_3 + AMC_4_4 + AMC_4_5 + AMC_4_6 + RMC_4 + PMC_4 + listen_4 + wait_msg_4 + loop_em_4 = 1
invariant :wait_ack_5_1 + wait_ack_5_2 + wait_ack_5_3 + wait_ack_5_4 + wait_ack_5_6 + listen_5 + wait_cable_5 + wait_msg_5 + loop_em_5 = 1
invariant :wait_ack_2_1 + wait_ack_3_1 + wait_ack_4_1 + wait_ack_5_1 + wait_ack_6_1 + wait_ack_1_2 + wait_ack_3_2 + wait_ack_4_2 + wait_ack_5_2 + wait_ack_6_2 + wait_ack_1_3 + wait_ack_2_3 + wait_ack_4_3 + wait_ack_5_3 + wait_ack_6_3 + wait_ack_1_4 + wait_ack_2_4 + wait_ack_3_4 + wait_ack_5_4 + wait_ack_6_4 + wait_ack_1_5 + wait_ack_2_5 + wait_ack_3_5 + wait_ack_4_5 + wait_ack_6_5 + wait_ack_1_6 + wait_ack_2_6 + wait_ack_3_6 + wait_ack_4_6 + wait_ack_5_6 + -1'AMC_3_1 + -1'AMC_3_2 + -1'AMC_3_3 + -1'AMC_3_4 + -1'AMC_3_5 + -1'AMC_3_6 + -1'RMC_3 + FMC_1 + FMC_2 + FMC_3 + FMC_4 + FMC_5 + FMC_6 + cable_free + PMC_1 + PMC_2 + PMC_4 + PMC_5 + PMC_6 + wait_cable_3 = 1
invariant :-1'wait_ack_2_1 + -1'wait_ack_2_3 + -1'wait_ack_2_4 + -1'wait_ack_2_5 + -1'wait_ack_2_6 + cable_used_2 + -1'FMC_2 + -1'PMC_2 = 0
invariant :wait_ack_3_1 + wait_ack_3_2 + wait_ack_3_4 + wait_ack_3_5 + wait_ack_3_6 + listen_3 + wait_cable_3 + wait_msg_3 + loop_em_3 = 1
invariant :-1'wait_ack_4_1 + -1'wait_ack_4_2 + -1'wait_ack_4_3 + -1'wait_ack_4_5 + -1'wait_ack_4_6 + cable_used_4 + -1'FMC_4 + -1'PMC_4 = 0
invariant :FMCb + FMC_1 + FMC_2 + FMC_3 + FMC_4 + FMC_5 + FMC_6 = 1
invariant :wait_ack_1_2 + wait_ack_1_3 + wait_ack_1_4 + wait_ack_1_5 + wait_ack_1_6 + listen_1 + wait_cable_1 + wait_msg_1 + loop_em_1 = 1
invariant :Cpt2_6 + AMC_1_5 + AMC_2_5 + AMC_3_5 + AMC_4_5 + AMC_5_5 + AMC_6_5 + -1'AMC_1_6 + -1'AMC_2_6 + -1'AMC_3_6 + -1'AMC_4_6 + -1'AMC_5_6 + -1'AMC_6_6 + -1'Cpt1_6 = 0
invariant :AMC_6_1 + AMC_6_2 + AMC_6_3 + AMC_6_4 + AMC_6_5 + AMC_6_6 + RMC_6 + PMC_6 + -1'wait_cable_6 = 0
invariant :wait_ack_6_1 + wait_ack_6_2 + wait_ack_6_3 + wait_ack_6_4 + wait_ack_6_5 + listen_6 + wait_cable_6 + wait_msg_6 + loop_em_6 = 1
invariant :AMC_1_1 + AMC_1_2 + AMC_1_3 + AMC_1_4 + AMC_1_5 + AMC_1_6 + RMC_1 + PMC_1 + -1'wait_cable_1 = 0
invariant :Cpt2_5 + AMC_1_4 + AMC_2_4 + AMC_3_4 + AMC_4_4 + AMC_5_4 + AMC_6_4 + -1'AMC_1_5 + -1'AMC_2_5 + -1'AMC_3_5 + -1'AMC_4_5 + -1'AMC_5_5 + -1'AMC_6_5 + -1'Cpt1_5 = 0
invariant :-1'wait_ack_3_1 + -1'wait_ack_3_2 + -1'wait_ack_3_4 + -1'wait_ack_3_5 + -1'wait_ack_3_6 + AMC_3_1 + AMC_3_2 + AMC_3_3 + AMC_3_4 + AMC_3_5 + AMC_3_6 + cable_used_3 + RMC_3 + -1'FMC_3 + -1'wait_cable_3 = 0
invariant :ACK + T_out + -1'wait_ack_2_1 + -1'wait_ack_3_1 + -1'wait_ack_4_1 + -1'wait_ack_5_1 + -1'wait_ack_6_1 + -1'wait_ack_1_2 + -1'wait_ack_3_2 + -1'wait_ack_4_2 + -1'wait_ack_5_2 + -1'wait_ack_6_2 + -1'wait_ack_1_3 + -1'wait_ack_2_3 + -1'wait_ack_4_3 + -1'wait_ack_5_3 + -1'wait_ack_6_3 + -1'wait_ack_1_4 + -1'wait_ack_2_4 + -1'wait_ack_3_4 + -1'wait_ack_5_4 + -1'wait_ack_6_4 + -1'wait_ack_1_5 + -1'wait_ack_2_5 + -1'wait_ack_3_5 + -1'wait_ack_4_5 + -1'wait_ack_6_5 + -1'wait_ack_1_6 + -1'wait_ack_2_6 + -1'wait_ack_3_6 + -1'wait_ack_4_6 + -1'wait_ack_5_6 + MSG_1 + MSG_2 + MSG_3 + MSG_4 + MSG_5 + MSG_6 = 0
invariant :Cpt2_1 + -1'AMC_1_1 + -1'AMC_2_1 + -1'AMC_3_1 + -1'AMC_4_1 + -1'AMC_5_1 + -1'AMC_6_1 + AMC_1_6 + AMC_2_6 + AMC_3_6 + AMC_4_6 + AMC_5_6 + AMC_6_6 + -1'Cpt1_1 = 0
invariant :wait_ack_4_1 + wait_ack_4_2 + wait_ack_4_3 + wait_ack_4_5 + wait_ack_4_6 + listen_4 + wait_cable_4 + wait_msg_4 + loop_em_4 = 1
invariant :Cpt2_3 + AMC_1_2 + AMC_2_2 + AMC_3_2 + AMC_4_2 + AMC_5_2 + AMC_6_2 + -1'AMC_1_3 + -1'AMC_2_3 + -1'AMC_3_3 + -1'AMC_4_3 + -1'AMC_5_3 + -1'AMC_6_3 + Cpt1_1 + Cpt1_2 + Cpt1_4 + Cpt1_5 + Cpt1_6 = 1
invariant :R_tout + S_tout = 1
invariant :-1'wait_ack_5_1 + -1'wait_ack_5_2 + -1'wait_ack_5_3 + -1'wait_ack_5_4 + -1'wait_ack_5_6 + cable_used_5 + -1'FMC_5 + -1'PMC_5 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 7515 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 56 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,6.81676e+06,299.691,3983320,2,235604,5,5.0505e+06,6,0,1006,5.12376e+06,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,0,378.781,4015504,1,0,6,9.12492e+06,9,1,6172,5.12376e+06,2

System contains 0 deadlocks (shown below if less than --print-limit option) !
FORMULA SafeBus-PT-06-ReachabilityDeadlock-0 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
EmptySet
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527060317028

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 23, 2018 7:18:52 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 23, 2018 7:18:52 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 23, 2018 7:18:52 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 144 ms
May 23, 2018 7:18:52 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 144 places.
May 23, 2018 7:18:53 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 451 transitions.
May 23, 2018 7:18:53 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 38 ms
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 6 fixed domain variables (out of 144 variables) in GAL type SafeBus_PT_06
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 6 constant array cells/variables (out of 144 variables) in type SafeBus_PT_06
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: msgl_2,msgl_4,msgl_3,msgl_5,msgl_1,msgl_6,
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed 6 constant variables :msgl_2=1, msgl_4=1, msgl_3=1, msgl_5=1, msgl_1=1, msgl_6=1
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 30 expressions due to constant valuations.
May 23, 2018 7:18:53 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 243 ms
May 23, 2018 7:18:53 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 7 ms
May 23, 2018 7:18:53 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 451 transitions.
May 23, 2018 7:18:54 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 4 ms
May 23, 2018 7:18:54 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 451 transitions.
May 23, 2018 7:18:54 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 29 place invariants in 52 ms
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 138 variables to be positive in 712 ms
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 451 transitions.
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/451 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 107 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 451 transitions.
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 43 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 23, 2018 7:18:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 451 transitions.
May 23, 2018 7:18:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/451) took 3138 ms. Total solver calls (SAT/UNSAT): 552(490/62)
May 23, 2018 7:19:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/451) took 7584 ms. Total solver calls (SAT/UNSAT): 1766(1481/285)
May 23, 2018 7:19:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/451) took 10933 ms. Total solver calls (SAT/UNSAT): 3461(2821/640)
May 23, 2018 7:19:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/451) took 16209 ms. Total solver calls (SAT/UNSAT): 4338(3594/744)
May 23, 2018 7:19:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/451) took 19365 ms. Total solver calls (SAT/UNSAT): 5442(4531/911)
May 23, 2018 7:19:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/451) took 23289 ms. Total solver calls (SAT/UNSAT): 6521(5447/1074)
May 23, 2018 7:19:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/451) took 26675 ms. Total solver calls (SAT/UNSAT): 8325(6889/1436)
May 23, 2018 7:19:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/451) took 33752 ms. Total solver calls (SAT/UNSAT): 9960(8282/1678)
May 23, 2018 7:19:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/451) took 36851 ms. Total solver calls (SAT/UNSAT): 11251(9405/1846)
May 23, 2018 7:19:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/451) took 40637 ms. Total solver calls (SAT/UNSAT): 11901(9945/1956)
May 23, 2018 7:19:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(51/451) took 47133 ms. Total solver calls (SAT/UNSAT): 13807(11543/2264)
May 23, 2018 7:19:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/451) took 51649 ms. Total solver calls (SAT/UNSAT): 15669(12857/2812)
May 23, 2018 7:19:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(63/451) took 54670 ms. Total solver calls (SAT/UNSAT): 17495(14142/3353)
May 23, 2018 7:19:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/451) took 58631 ms. Total solver calls (SAT/UNSAT): 19388(15727/3661)
May 23, 2018 7:19:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/451) took 62934 ms. Total solver calls (SAT/UNSAT): 21346(17389/3957)
May 23, 2018 7:20:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/451) took 67886 ms. Total solver calls (SAT/UNSAT): 23275(19052/4223)
May 23, 2018 7:20:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(87/451) took 74766 ms. Total solver calls (SAT/UNSAT): 25169(20656/4513)
May 23, 2018 7:20:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/451) took 79330 ms. Total solver calls (SAT/UNSAT): 27019(21976/5043)
May 23, 2018 7:20:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(100/451) took 82906 ms. Total solver calls (SAT/UNSAT): 29132(23500/5632)
May 23, 2018 7:20:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(106/451) took 86242 ms. Total solver calls (SAT/UNSAT): 30899(24983/5916)
May 23, 2018 7:20:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(111/451) took 91340 ms. Total solver calls (SAT/UNSAT): 32348(26214/6134)
May 23, 2018 7:20:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(117/451) took 95969 ms. Total solver calls (SAT/UNSAT): 34061(27673/6388)
May 23, 2018 7:20:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/451) took 102693 ms. Total solver calls (SAT/UNSAT): 35739(29079/6660)
May 23, 2018 7:20:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(129/451) took 106446 ms. Total solver calls (SAT/UNSAT): 37373(30231/7142)
May 23, 2018 7:20:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/451) took 109500 ms. Total solver calls (SAT/UNSAT): 39496(31759/7737)
May 23, 2018 7:20:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(146/451) took 112688 ms. Total solver calls (SAT/UNSAT): 41510(33477/8033)
May 23, 2018 7:20:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/451) took 117955 ms. Total solver calls (SAT/UNSAT): 43035(34644/8391)
May 23, 2018 7:20:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(159/451) took 121718 ms. Total solver calls (SAT/UNSAT): 44293(35648/8645)
May 23, 2018 7:21:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(169/451) took 124796 ms. Total solver calls (SAT/UNSAT): 46288(36964/9324)
May 23, 2018 7:21:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(179/451) took 128229 ms. Total solver calls (SAT/UNSAT): 48203(38407/9796)
May 23, 2018 7:21:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(185/451) took 131325 ms. Total solver calls (SAT/UNSAT): 49297(39259/10038)
May 23, 2018 7:21:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(192/451) took 134395 ms. Total solver calls (SAT/UNSAT): 50532(40252/10280)
May 23, 2018 7:21:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(201/451) took 137518 ms. Total solver calls (SAT/UNSAT): 52045(41281/10764)
May 23, 2018 7:21:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(212/451) took 140633 ms. Total solver calls (SAT/UNSAT): 53762(42517/11245)
May 23, 2018 7:21:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(222/451) took 143735 ms. Total solver calls (SAT/UNSAT): 55252(43583/11669)
May 23, 2018 7:21:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/451) took 147024 ms. Total solver calls (SAT/UNSAT): 56505(44496/12009)
May 23, 2018 7:21:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(243/451) took 150061 ms. Total solver calls (SAT/UNSAT): 58033(45415/12618)
May 23, 2018 7:21:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(255/451) took 153609 ms. Total solver calls (SAT/UNSAT): 59400(46142/13258)
May 23, 2018 7:21:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(261/451) took 157315 ms. Total solver calls (SAT/UNSAT): 60256(46842/13414)
May 23, 2018 7:21:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(267/451) took 161794 ms. Total solver calls (SAT/UNSAT): 61172(47604/13568)
May 23, 2018 7:21:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(274/451) took 164794 ms. Total solver calls (SAT/UNSAT): 62060(48307/13753)
May 23, 2018 7:21:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(283/451) took 167950 ms. Total solver calls (SAT/UNSAT): 62998(49052/13946)
May 23, 2018 7:21:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(296/451) took 171102 ms. Total solver calls (SAT/UNSAT): 64042(49790/14252)
May 23, 2018 7:21:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(312/451) took 174296 ms. Total solver calls (SAT/UNSAT): 65344(50646/14698)
May 23, 2018 7:21:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(333/451) took 177379 ms. Total solver calls (SAT/UNSAT): 66564(51378/15186)
May 23, 2018 7:21:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(391/451) took 180415 ms. Total solver calls (SAT/UNSAT): 69063(51937/17126)
May 23, 2018 7:21:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 181946 ms. Total solver calls (SAT/UNSAT): 70041(52128/17913)
May 23, 2018 7:21:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 451 transitions.
May 23, 2018 7:22:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 17041 ms. Total solver calls (SAT/UNSAT): 11925(0/11925)
May 23, 2018 7:22:14 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 200482ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SafeBus-PT-06"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/SafeBus-PT-06.tgz
mv SafeBus-PT-06 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is SafeBus-PT-06, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r152-smll-152685550400237"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;