Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................................................................................
/home/mcc/execution
total 268K
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 9 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 103K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ResAllocation-PT-R003C015, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r141-qhx2-152673583000357
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-00
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-01
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-02
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-03
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-04
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-05
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-06
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-07
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-08
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-09
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-10
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-11
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-12
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-13
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-14
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1527927793227

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph7866663703382485929.txt, -o, /tmp/graph7866663703382485929.bin, -w, /tmp/graph7866663703382485929.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph7866663703382485929.bin, -l, -1, -v, -w, /tmp/graph7866663703382485929.weights, -q, 0, -e, 0.001], workingDir=null]
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-01 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
invariant :p_6_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_12_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_0_2 + r_0_2 + -1'r_1_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_5_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_14_0 + r_14_0 = 1
invariant :p_13_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_7_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_13_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_2_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_1_0 + r_1_0 + -1'r_2_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-03 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
invariant :p_6_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_10_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_7_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_11_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_10_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_12_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_2_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_9_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_1_1 + r_1_1 + -1'r_2_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_3_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_9_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_10_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_4_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_14_1 + r_14_1 = 1
invariant :p_14_2 + r_14_2 = 1
invariant :p_2_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_1_2 + r_1_2 + -1'r_2_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_11_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_13_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_7_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_6_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_5_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_8_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_5_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_0_0 + r_0_0 + -1'r_1_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_0_1 + r_0_1 + -1'r_1_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_9_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_12_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_11_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityFireability.pnml.gal, -t, CGAL, -reachable-file, ReachabilityFireability.prop, --nowitness], workingDir=/home/mcc/execution]
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-09 TRUE TECHNIQUES SAT_SMT TAUTOLOGY

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityFireability.pnml.gal -t CGAL -reachable-file ReachabilityFireability.prop --nowitness
Loading property file ReachabilityFireability.prop.
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-00 with value :((!(((((i4.u26.p_12_0>=1)&&(i4.u29.r_12_1>=1))&&(i3.u24.r_11_1>=1))&&(i0.u6.p_3_0>=1))||(i0.u0.r_0_0>=1)))&&(((!(((i4.u28.r_13_0>=1)&&(i4.u29.p_13_1>=1))&&(i4.u26.r_12_0>=1)))&&((i2.u18.p_8_2>=1)&&(i3.u23.p_11_0>=1)))&&((i4.u31.r_14_0>=1)&&(i4.u28.r_13_0>=1))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-01 with value :((((!((i2.u13.r_6_0>=1)&&(i1.u10.r_5_0>=1)))&&(!(((i2.u14.r_7_0>=1)&&(i2.u15.p_7_1>=1))&&(i2.u13.r_6_0>=1))))||(!((i2.u18.p_8_2>=1)&&((i4.u26.r_12_0>=1)&&(i3.u23.r_11_0>=1)))))||((!(((i3.u22.r_10_0>=1)&&(i2.u19.r_9_0>=1))&&(i1.u11.p_4_2>=1)))||((i3.u22.r_10_0>=1)&&(i2.u19.r_9_0>=1))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-02 with value :(!(((!(((i0.u4.p_2_1>=1)&&(i0.u8.r_2_2>=1))&&(i0.u5.r_1_2>=1)))||(!(((i4.u32.p_14_1>=1)&&(i4.u33.r_14_2>=1))&&(i4.u30.r_13_2>=1))))||(i0.u0.r_0_0>=1)))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-03 with value :((((i3.u23.r_11_0>=1)&&(i3.u24.p_11_1>=1))&&(i3.u22.r_10_0>=1))||(!(((i3.u23.r_11_0>=1)&&(i3.u24.p_11_1>=1))&&(i3.u22.r_10_0>=1))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-04 with value :(((((i0.u9.r_3_2>=1)&&(i0.u8.r_2_2>=1))&&(((i0.u3.r_1_0>=1)&&(i0.u4.p_1_1>=1))&&(i0.u0.r_0_0>=1)))||(((((i1.u10.r_3_0>=1)&&(i0.u7.p_3_1>=1))&&(i0.u6.r_2_0>=1))&&((i4.u30.r_13_2>=1)&&(i3.u27.r_12_2>=1)))&&((((i2.u13.p_6_0>=1)&&(i1.u12.r_6_1>=1))&&(i1.u12.r_5_1>=1))||((i2.u17.r_8_0>=1)&&(i2.u14.r_7_0>=1)))))||(!((((i0.u9.r_3_2>=1)&&(i0.u8.r_2_2>=1))&&(i4.u28.p_13_0>=1))&&((((i2.u19.r_9_0>=1)&&(i2.u20.p_9_1>=1))&&(i2.u17.r_8_0>=1))||(((i2.u14.r_7_0>=1)&&(i2.u15.p_7_1>=1))&&(i2.u13.r_6_0>=1))))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-05 with value :((!(i1.u12.p_6_2>=1))||(!(((i3.u21.p_10_1>=1)&&(i3.u21.r_10_2>=1))&&(i3.u21.r_9_2>=1))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-06 with value :((!(i3.u27.p_12_2>=1))&&((((i1.u12.r_5_1>=1)&&(i1.u11.p_5_2>=1))&&(i1.u10.r_4_1>=1))&&(i1.u12.p_6_2>=1)))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-07 with value :(((i2.u14.p_7_0>=1)&&(((((i0.u3.p_2_0>=1)&&(i0.u7.r_2_1>=1))&&(i0.u4.r_1_1>=1))||(((i0.u4.p_2_1>=1)&&(i0.u8.r_2_2>=1))&&(i0.u5.r_1_2>=1)))||(((i1.u12.r_5_1>=1)&&(i1.u11.p_5_2>=1))&&(i1.u10.r_4_1>=1))))&&(!((!((i4.u31.r_14_0>=1)&&(i4.u28.r_13_0>=1)))||((i0.u5.r_1_2>=1)&&(i0.u2.r_0_2>=1)))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-08 with value :((i4.u28.p_13_0>=1)&&(!((!(((i3.u24.r_11_1>=1)&&(i3.u25.p_11_2>=1))&&(i3.u21.r_10_1>=1)))||(((i0.u5.r_1_2>=1)&&(i0.u2.r_0_2>=1))&&(((i2.u14.r_7_0>=1)&&(i2.u15.p_7_1>=1))&&(i2.u13.r_6_0>=1))))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-09 with value :(((i3.u23.p_11_0>=1)||(((((i3.u21.r_9_1>=1)&&(i2.u18.p_9_2>=1))&&(i2.u20.r_8_1>=1))&&((i3.u21.r_9_2>=1)&&(i2.u18.r_8_2>=1)))||((i1.u12.r_5_2>=1)&&(i1.u11.r_4_2>=1))))||(((!((i4.u26.r_12_0>=1)&&(i3.u23.r_11_0>=1)))||(!(i3.u23.p_11_0>=1)))||(((i1.u12.r_5_1>=1)&&(i1.u11.p_5_2>=1))&&(i1.u10.r_4_1>=1))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-10 with value :(((!(i2.u14.p_7_0>=1))||((((i0.u6.r_2_0>=1)&&(i0.u3.r_1_0>=1))&&(i0.u8.p_2_2>=1))||(!(((i0.u3.p_2_0>=1)&&(i0.u7.r_2_1>=1))&&(i0.u4.r_1_1>=1)))))||((!((((i1.u10.p_4_0>=1)&&(i1.u10.r_4_1>=1))&&(i1.u10.r_3_1>=1))&&(((i3.u21.r_9_1>=1)&&(i2.u18.p_9_2>=1))&&(i2.u20.r_8_1>=1))))||(!((i3.u21.p_10_2>=1)||((i4.u30.r_13_2>=1)&&(i3.u27.r_12_2>=1))))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-11 with value :(!((i1.u10.p_5_0>=1)&&(i1.u12.p_6_2>=1)))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-12 with value :((i0.u8.p_2_2>=1)&&(!((((i0.u9.r_3_2>=1)&&(i0.u8.r_2_2>=1))&&((i0.u5.r_1_2>=1)&&(i0.u2.r_0_2>=1)))||(!(((i2.u15.r_7_1>=1)&&(i2.u16.p_7_2>=1))&&(i1.u12.r_6_1>=1))))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-13 with value :(!((!((i2.u19.p_9_0>=1)&&(((i0.u4.p_2_1>=1)&&(i0.u8.r_2_2>=1))&&(i0.u5.r_1_2>=1))))||(((i2.u19.r_9_0>=1)&&(i2.u20.p_9_1>=1))&&(i2.u17.r_8_0>=1))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityFireability-14 with value :((!((((i3.u22.r_10_0>=1)&&(i2.u19.r_9_0>=1))||(((i2.u15.p_8_1>=1)&&(i2.u18.r_8_2>=1))&&(i2.u16.r_7_2>=1)))&&((i0.u0.r_0_0>=1)&&(i2.u19.p_9_0>=1))))||((!((i0.u6.r_2_0>=1)&&(i0.u3.r_1_0>=1)))||(((((i0.u3.p_2_0>=1)&&(i0.u7.r_2_1>=1))&&(i0.u4.r_1_1>=1))&&((i0.u9.r_3_2>=1)&&(i0.u8.r_2_2>=1)))&&(!(((i4.u28.r_13_0>=1)&&(i4.u29.p_13_1>=1))&&(i4.u26.r_12_0>=1))))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityFireability-15 with value :((i2.u19.p_9_0>=1)&&((((((i0.u4.r_1_1>=1)&&(i0.u5.p_1_2>=1))&&(i0.u1.r_0_1>=1))||(((i2.u15.r_7_1>=1)&&(i2.u16.p_7_2>=1))&&(i1.u12.r_6_1>=1)))&&(((i4.u26.r_12_0>=1)&&(i3.u23.r_11_0>=1))&&(((i2.u13.p_6_0>=1)&&(i1.u12.r_6_1>=1))&&(i1.u12.r_5_1>=1))))&&(!((i2.u18.p_8_2>=1)||((i0.u0.p_0_0>=1)&&(i0.u1.r_0_1>=1))))))
built 9 ordering constraints for composite.
built 16 ordering constraints for composite.
built 13 ordering constraints for composite.
built 16 ordering constraints for composite.
built 15 ordering constraints for composite.
built 11 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
invariant :p_6_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_12_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_0_2 + r_0_2 + -1'r_1_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_5_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_14_0 + r_14_0 = 1
invariant :p_13_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_7_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_13_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_2_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_1_0 + r_1_0 + -1'r_2_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_6_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_10_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_7_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_11_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_10_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_12_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_2_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_9_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_1_1 + r_1_1 + -1'r_2_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_3_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_9_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_10_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_4_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_14_1 + r_14_1 = 1
invariant :p_14_2 + r_14_2 = 1
invariant :p_2_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_1_2 + r_1_2 + -1'r_2_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_11_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_13_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_7_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_6_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_5_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_8_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_5_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_0_0 + r_0_0 + -1'r_1_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_0_1 + r_0_1 + -1'r_1_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_9_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_12_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_11_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation\_PT\_R003C015\_flat\_flat\_flat\_flat\_mod,5.78878e+08,0.354109,7628,1066,127,7733,575,240,13825,62,1476,0
Total reachable state count : 578878464

Verifying 16 reachability properties.
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-00 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-00,64512,0.369035,7660,159,54,7733,575,300,13825,65,1476,507
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-01 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-01,0,0.387986,7868,1,0,7733,575,339,13825,66,1476,2511
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-02 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-02,3.5625e+06,0.393665,7868,824,81,7733,575,378,13825,67,1476,2691
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-03 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-03,0,0.396382,7868,1,0,7733,575,397,13825,67,1476,3355
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-04 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-04,2.3017e+06,0.423712,7868,643,156,7733,575,485,18594,69,1476,5289
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-05 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-05,307200,0.429598,7868,192,55,7733,575,514,19369,83,1476,5563
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-06 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityFireability-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-06,0,0.43114,7868,1,0,7733,575,541,19372,85,1476,5694
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-07 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-07,1296,0.436395,7868,94,23,7733,575,570,20370,86,1476,5917
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-08 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-08,4.3529e+06,0.440882,7868,687,127,7733,575,584,21306,86,1484,6070
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-09 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-09,0,0.450174,7868,1,0,7733,575,634,22399,91,1663,7544
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-10 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-10,94080,0.49202,8392,209,40,7733,637,679,26867,96,2054,9331
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-11 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-11,0,0.495784,8800,1,0,7733,637,686,26867,96,2054,9341
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-12 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-12,6144,0.499144,8808,78,36,7809,643,702,27183,96,2084,9489
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-13 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-13,155648,0.501853,8824,195,81,7906,643,708,27408,96,2084,9542
Invariant property ResAllocation-PT-R003C015-ReachabilityFireability-14 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-14,0,0.507248,8880,1,0,8070,643,740,27732,96,2084,10265
Reachability property ResAllocation-PT-R003C015-ReachabilityFireability-15 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityFireability-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityFireability-15,6912,0.511524,8936,109,36,8329,643,771,28027,96,2084,10502
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527927800293

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 8:23:16 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 02, 2018 8:23:16 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 8:23:16 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 100 ms
Jun 02, 2018 8:23:16 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 90 places.
Jun 02, 2018 8:23:16 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 60 transitions.
Jun 02, 2018 8:23:17 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 18 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 61 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 41 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 38 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 66 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
Begin: Sat Jun 2 08:23:17 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Sat Jun 2 08:23:17 2018
network size: 90 nodes, 406 links, 120 weight
quality increased from -0.0119676 to 0.446937
end computation: Sat Jun 2 08:23:17 2018
level 1:
start computation: Sat Jun 2 08:23:17 2018
network size: 34 nodes, 204 links, 120 weight
quality increased from 0.446937 to 0.631169
end computation: Sat Jun 2 08:23:17 2018
level 2:
start computation: Sat Jun 2 08:23:17 2018
network size: 11 nodes, 47 links, 120 weight
quality increased from 0.631169 to 0.649198
end computation: Sat Jun 2 08:23:17 2018
level 3:
start computation: Sat Jun 2 08:23:17 2018
network size: 5 nodes, 13 links, 120 weight
quality increased from 0.649198 to 0.649198
end computation: Sat Jun 2 08:23:17 2018
End: Sat Jun 2 08:23:17 2018
Total duration: 0 sec
0.649198
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 25 ms
Jun 02, 2018 8:23:17 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Result for false tautology is UNSAT, invariant/never predicate is unrealizable ResAllocation-PT-R003C015-ReachabilityFireability-01
Jun 02, 2018 8:23:18 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityFireability.pnml.gal : 13 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Result for false tautology is UNSAT, invariant/never predicate is unrealizable ResAllocation-PT-R003C015-ReachabilityFireability-03
Jun 02, 2018 8:23:18 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityFireability.prop : 4 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 98 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Result for false tautology is UNSAT, invariant/never predicate is unrealizable ResAllocation-PT-R003C015-ReachabilityFireability-09
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 3 / 16 in 869 ms.
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-00(UNSAT) depth K=0 took 12 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-02(UNSAT) depth K=0 took 16 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-04(UNSAT) depth K=0 took 25 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-05(UNSAT) depth K=0 took 18 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-06(UNSAT) depth K=0 took 26 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-07(UNSAT) depth K=0 took 16 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-08(UNSAT) depth K=0 took 22 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-10(UNSAT) depth K=0 took 15 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-11(UNSAT) depth K=0 took 18 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-12(UNSAT) depth K=0 took 8 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-13(UNSAT) depth K=0 took 16 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-14(UNSAT) depth K=0 took 34 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-15(UNSAT) depth K=0 took 22 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-00(UNSAT) depth K=1 took 59 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-02(UNSAT) depth K=1 took 24 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-04(UNSAT) depth K=1 took 16 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-05(UNSAT) depth K=1 took 15 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 63 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-06(UNSAT) depth K=1 took 18 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-07(UNSAT) depth K=1 took 16 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-08(UNSAT) depth K=1 took 20 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-10(UNSAT) depth K=1 took 14 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-11(UNSAT) depth K=1 took 3 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-12(UNSAT) depth K=1 took 8 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-13(UNSAT) depth K=1 took 3 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-14(UNSAT) depth K=1 took 25 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-15(UNSAT) depth K=1 took 23 ms
Jun 02, 2018 8:23:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityFireability-02(UNSAT) depth K=2 took 179 ms
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Exception in thread "Thread-8" java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying ResAllocation-PT-R003C015-ReachabilityFireability-04 SMT depth 2
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 2
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 2
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 3/ 16 properties. Interrupting other analysis methods.
Jun 02, 2018 8:23:19 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1610ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ResAllocation-PT-R003C015, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r141-qhx2-152673583000357"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;