Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................
/home/mcc/execution
total 268K
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 9 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 103K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ResAllocation-PT-R003C015, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r140-qhx2-152673582200355
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-00
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-01
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-02
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-03
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-04
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-05
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-06
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-07
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-08
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-09
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-10
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-11
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-12
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-13
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-14
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527860234289

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-00 with value :(!(p_1_2>=3))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-01 with value :(p_12_0>=3)
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-02 with value :(((!(p_14_2<=r_6_0))&&(r_11_1>=2))&&(p_13_2>=1))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-03 with value :((!((r_10_1<=p_11_0)||(p_10_1>=2)))&&(p_3_2>=2))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-04 with value :(!(((r_11_1<=r_3_0)&&(r_7_1>=2))&&(!(p_3_1<=r_7_2))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-05 with value :((!((r_8_0<=p_1_0)&&(p_9_0>=1)))||(p_13_1<=p_11_2))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-06 with value :((((p_3_1>=2)&&(p_0_0>=2))||((p_12_0>=2)&&(r_4_0<=p_0_2)))&&(r_1_1<=p_1_1))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-07 with value :((((r_6_2<=p_0_0)||(p_7_2<=p_9_2))&&((r_8_2>=2)||(p_0_1>=2)))&&((p_5_0<=p_14_2)||(!(r_14_2>=1))))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-08 with value :(((!(r_13_1<=r_13_0))||(!(r_11_0>=1)))||(!(p_5_1>=2)))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-09 with value :((((r_8_1>=3)||(r_1_2>=3))&&(!(p_14_0<=p_8_0)))&&(r_10_2<=r_8_0))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-10 with value :((r_3_2>=3)||(((p_7_2<=r_10_2)||(p_11_1<=p_2_2))||((p_12_2>=2)&&(p_1_0>=1))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-11 with value :((((p_2_0>=1)&&(p_14_2>=2))&&(!(r_4_1<=r_5_2)))&&(p_11_1>=3))
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-12 with value :(((!(r_11_0>=2))||((r_13_1<=p_6_0)&&(p_4_1>=1)))&&(!((p_13_2<=p_8_2)&&(r_11_2>=2))))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-13 with value :(r_10_1>=3)
Read [invariant] property : ResAllocation-PT-R003C015-ReachabilityCardinality-14 with value :(!(((p_3_2<=p_8_2)||(r_8_1<=r_1_2))&&(r_12_2>=3)))
Read [reachable] property : ResAllocation-PT-R003C015-ReachabilityCardinality-15 with value :(p_14_0>=2)
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
invariant :p_6_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_12_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_0_2 + r_0_2 + -1'r_1_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_5_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_14_0 + r_14_0 = 1
invariant :p_13_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_7_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_13_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_2_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_1_0 + r_1_0 + -1'r_2_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_6_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_10_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_7_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_11_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_10_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_12_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_2_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_9_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_1_1 + r_1_1 + -1'r_2_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_3_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_9_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_10_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_4_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_14_1 + r_14_1 = 1
invariant :p_14_2 + r_14_2 = 1
invariant :p_2_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_1_2 + r_1_2 + -1'r_2_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_11_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_13_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_7_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_6_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_5_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_8_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_5_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_0_0 + r_0_0 + -1'r_1_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_0_1 + r_0_1 + -1'r_1_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_9_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_12_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_11_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation\_PT\_R003C015\_flat\_flat,5.78878e+08,0.984781,20588,2,6564,5,76517,6,0,423,106011,0
Total reachable state count : 578878464

Verifying 16 reachability properties.
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-00 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-00,0,0.988078,20740,1,0,5,76517,7,0,425,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-01 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-01

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-01,0,0.993915,20860,1,0,5,76517,8,0,426,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-02 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-02,0,0.998526,20860,1,0,5,76517,9,0,429,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-03 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-03

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-03,0,1.00114,20860,1,0,5,76517,10,0,434,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-04 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-04,0,1.00499,20860,1,0,5,76517,11,0,442,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-05 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-05,64000,1.01233,20860,2,469,6,76517,12,0,457,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-06 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-06,0,1.03452,20860,1,0,6,76517,13,0,475,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-07 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-07

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-07,0,1.03973,20860,1,0,6,76517,14,0,488,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-08 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-08,0,1.0426,20860,1,0,6,76517,15,0,491,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-09 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-09,0,1.04608,20860,1,0,6,76517,16,0,505,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-10 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-10,1.14962e+07,1.05804,20860,2,2167,7,76517,17,0,528,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-11 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-11,0,1.06921,20860,1,0,7,76517,18,0,535,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-12 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-12,0,1.08404,20860,1,0,7,76517,19,0,550,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-13 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-13,0,1.08767,20860,1,0,7,76517,20,0,551,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-14 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-14,0,1.08991,20860,1,0,7,76517,21,0,556,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-15 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-15,0,1.09456,20860,1,0,7,76517,22,0,557,106011,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
invariant :p_6_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_12_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_0_2 + r_0_2 + -1'r_1_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_5_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_14_0 + r_14_0 = 1
invariant :p_13_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_7_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_13_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_2_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_1_0 + r_1_0 + -1'r_2_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_6_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_10_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_7_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_11_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_10_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_3_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_12_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_2_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_9_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_1_1 + r_1_1 + -1'r_2_1 + r_3_1 + -1'r_4_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_3_0 + r_3_0 + -1'r_4_0 + r_5_0 + -1'r_6_0 + r_7_0 + -1'r_8_0 + r_9_0 + -1'r_10_0 + r_11_0 + -1'r_12_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_9_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_10_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_4_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_14_1 + r_14_1 = 1
invariant :p_14_2 + r_14_2 = 1
invariant :p_2_2 + r_2_2 + -1'r_3_2 + r_4_2 + -1'r_5_2 + r_6_2 + -1'r_7_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1
invariant :p_1_2 + r_1_2 + -1'r_2_2 + r_3_2 + -1'r_4_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_11_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_13_0 + r_13_0 + -1'r_14_0 = 0
invariant :p_7_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_6_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_5_1 + r_5_1 + -1'r_6_1 + r_7_1 + -1'r_8_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_8_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_5_2 + r_5_2 + -1'r_6_2 + r_7_2 + -1'r_8_2 + r_9_2 + -1'r_10_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_0_0 + r_0_0 + -1'r_1_0 + r_2_0 + -1'r_3_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_0_1 + r_0_1 + -1'r_1_1 + r_2_1 + -1'r_3_1 + r_4_1 + -1'r_5_1 + r_6_1 + -1'r_7_1 + r_8_1 + -1'r_9_1 + r_10_1 + -1'r_11_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_9_1 + r_9_1 + -1'r_10_1 + r_11_1 + -1'r_12_1 + r_13_1 + -1'r_14_1 = 0
invariant :p_12_1 + r_12_1 + -1'r_13_1 + r_14_1 = 1
invariant :p_11_2 + r_11_2 + -1'r_12_2 + r_13_2 + -1'r_14_2 = 0
invariant :p_4_0 + r_4_0 + -1'r_5_0 + r_6_0 + -1'r_7_0 + r_8_0 + -1'r_9_0 + r_10_0 + -1'r_11_0 + r_12_0 + -1'r_13_0 + r_14_0 = 1
invariant :p_8_2 + r_8_2 + -1'r_9_2 + r_10_2 + -1'r_11_2 + r_12_2 + -1'r_13_2 + r_14_2 = 1

BK_STOP 1527860242335

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 105 ms
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 90 places.
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 60 transitions.
Jun 01, 2018 1:37:18 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 16 ms
Jun 01, 2018 1:37:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 124 ms
Jun 01, 2018 1:37:19 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 33 ms
Jun 01, 2018 1:37:19 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 4 ms
Jun 01, 2018 1:37:19 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
Jun 01, 2018 1:37:19 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 73 ms
Jun 01, 2018 1:37:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
Jun 01, 2018 1:37:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 73 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1019 ms.
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-00(UNSAT) depth K=0 took 36 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-01(UNSAT) depth K=0 took 68 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-02(UNSAT) depth K=0 took 20 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-03(UNSAT) depth K=0 took 25 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Failed to check-sat")
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 60 transitions.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying ResAllocation-PT-R003C015-ReachabilityCardinality-04 SMT depth 0
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 0
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 0
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1019ms conformant to PINS in folder :/home/mcc/execution
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 32 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 90 variables to be positive in 222 ms
Jun 01, 2018 1:37:20 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ResAllocation-PT-R003C015, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r140-qhx2-152673582200355"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;